src/cpu/simple/base.cc

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  */
  30
  31 #include "arch/utility.hh"
  32 #include "sim/faults.hh"
  33 #include "base/cprintf.hh"
  34 #include "base/inifile.hh"
  35 #include "base/loader/symtab.hh"
  36 #include "base/misc.hh"
  37 #include "base/pollevent.hh"
  38 #include "base/range.hh"
  39 #include "base/stats/events.hh"
  40 #include "base/trace.hh"
  41 #include "cpu/base.hh"
  42 #include "cpu/exetrace.hh"
  43 #include "cpu/profile.hh"
  44 #include "cpu/simple/base.hh"
  45 #include "cpu/simple_thread.hh"
  46 #include "cpu/smt.hh"
  47 #include "cpu/static_inst.hh"
  48 #include "cpu/thread_context.hh"
  49 #include "kern/kernel_stats.hh"
  50 #include "mem/packet.hh"
  51 #include "sim/builder.hh"
  52 #include "sim/byteswap.hh"
  53 #include "sim/debug.hh"
  54 #include "sim/host.hh"
  55 #include "sim/sim_events.hh"
  56 #include "sim/sim_object.hh"
  57 #include "sim/stats.hh"
  58 #include "sim/system.hh"
  59
  60 #if FULL_SYSTEM
  61 #include "base/remote_gdb.hh"
  62 #include "arch/tlb.hh"
  63 #include "arch/stacktrace.hh"
  64 #include "arch/vtophys.hh"
  65 #else // !FULL_SYSTEM
  66 #include "mem/mem_object.hh"
  67 #endif // FULL_SYSTEM
  68
  69 using namespace std;
  70 using namespace TheISA;
  71
  72 BaseSimpleCPU::BaseSimpleCPU(Params *p)
  73     : BaseCPU(p), mem(p->mem), thread(NULL)
  74 {
  75 #if FULL_SYSTEM
  76     thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
  77 #else
  78     thread = new SimpleThread(this, /* thread_num */ 0, p->process,
  79             /* asid */ 0, mem);
  80 #endif // !FULL_SYSTEM
  81
  82     thread->setStatus(ThreadContext::Suspended);
  83
  84     tc = thread->getTC();
  85
  86     numInst = 0;
  87     startNumInst = 0;
  88     numLoad = 0;
  89     startNumLoad = 0;
  90     lastIcacheStall = 0;
  91     lastDcacheStall = 0;
  92
  93     threadContexts.push_back(tc);
  94 }
  95
  96 BaseSimpleCPU::~BaseSimpleCPU()
  97 {
  98 }
  99
 100 void
 101 BaseSimpleCPU::deallocateContext(int thread_num)
 102 {
 103     // for now, these are equivalent
 104     suspendContext(thread_num);
 105 }
 106
 107
 108 void
 109 BaseSimpleCPU::haltContext(int thread_num)
 110 {
 111     // for now, these are equivalent
 112     suspendContext(thread_num);
 113 }
 114
 115
 116 void
 117 BaseSimpleCPU::regStats()
 118 {
 119     using namespace Stats;
 120
 121     BaseCPU::regStats();
 122
 123     numInsts
 124         .name(name() + ".num_insts")
 125         .desc("Number of instructions executed")
 126         ;
 127
 128     numMemRefs
 129         .name(name() + ".num_refs")
 130         .desc("Number of memory references")
 131         ;
 132
 133     notIdleFraction
 134         .name(name() + ".not_idle_fraction")
 135         .desc("Percentage of non-idle cycles")
 136         ;
 137
 138     idleFraction
 139         .name(name() + ".idle_fraction")
 140         .desc("Percentage of idle cycles")
 141         ;
 142
 143     icacheStallCycles
 144         .name(name() + ".icache_stall_cycles")
 145         .desc("ICache total stall cycles")
 146         .prereq(icacheStallCycles)
 147         ;
 148
 149     dcacheStallCycles
 150         .name(name() + ".dcache_stall_cycles")
 151         .desc("DCache total stall cycles")
 152         .prereq(dcacheStallCycles)
 153         ;
 154
 155     icacheRetryCycles
 156         .name(name() + ".icache_retry_cycles")
 157         .desc("ICache total retry cycles")
 158         .prereq(icacheRetryCycles)
 159         ;
 160
 161     dcacheRetryCycles
 162         .name(name() + ".dcache_retry_cycles")
 163         .desc("DCache total retry cycles")
 164         .prereq(dcacheRetryCycles)
 165         ;
 166
 167     idleFraction = constant(1.0) - notIdleFraction;
 168 }
 169
 170 void
 171 BaseSimpleCPU::resetStats()
 172 {
 173 //    startNumInst = numInst;
 174     // notIdleFraction = (_status != Idle);
 175 }
 176
 177 void
 178 BaseSimpleCPU::serialize(ostream &os)
 179 {
 180     BaseCPU::serialize(os);
 181 //    SERIALIZE_SCALAR(inst);
 182     nameOut(os, csprintf("%s.xc.0", name()));
 183     thread->serialize(os);
 184 }
 185
 186 void
 187 BaseSimpleCPU::unserialize(Checkpoint *cp, const string &section)
 188 {
 189     BaseCPU::unserialize(cp, section);
 190 //    UNSERIALIZE_SCALAR(inst);
 191     thread->unserialize(cp, csprintf("%s.xc.0", section));
 192 }
 193
 194 void
 195 change_thread_state(int thread_number, int activate, int priority)
 196 {
 197 }
 198
 199 Fault
 200 BaseSimpleCPU::copySrcTranslate(Addr src)
 201 {
 202 #if 0
 203     static bool no_warn = true;
 204     int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
 205     // Only support block sizes of 64 atm.
 206     assert(blk_size == 64);
 207     int offset = src & (blk_size - 1);
 208
 209     // Make sure block doesn't span page
 210     if (no_warn &&
 211         (src & PageMask) != ((src + blk_size) & PageMask) &&
 212         (src >> 40) != 0xfffffc) {
 213         warn("Copied block source spans pages %x.", src);
 214         no_warn = false;
 215     }
 216
 217     memReq->reset(src & ~(blk_size - 1), blk_size);
 218
 219     // translate to physical address
 220     Fault fault = thread->translateDataReadReq(req);
 221
 222     if (fault == NoFault) {
 223         thread->copySrcAddr = src;
 224         thread->copySrcPhysAddr = memReq->paddr + offset;
 225     } else {
 226         assert(!fault->isAlignmentFault());
 227
 228         thread->copySrcAddr = 0;
 229         thread->copySrcPhysAddr = 0;
 230     }
 231     return fault;
 232 #else
 233     return NoFault;
 234 #endif
 235 }
 236
 237 Fault
 238 BaseSimpleCPU::copy(Addr dest)
 239 {
 240 #if 0
 241     static bool no_warn = true;
 242     int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
 243     // Only support block sizes of 64 atm.
 244     assert(blk_size == 64);
 245     uint8_t data[blk_size];
 246     //assert(thread->copySrcAddr);
 247     int offset = dest & (blk_size - 1);
 248
 249     // Make sure block doesn't span page
 250     if (no_warn &&
 251         (dest & PageMask) != ((dest + blk_size) & PageMask) &&
 252         (dest >> 40) != 0xfffffc) {
 253         no_warn = false;
 254         warn("Copied block destination spans pages %x. ", dest);
 255     }
 256
 257     memReq->reset(dest & ~(blk_size -1), blk_size);
 258     // translate to physical address
 259     Fault fault = thread->translateDataWriteReq(req);
 260
 261     if (fault == NoFault) {
 262         Addr dest_addr = memReq->paddr + offset;
 263         // Need to read straight from memory since we have more than 8 bytes.
 264         memReq->paddr = thread->copySrcPhysAddr;
 265         thread->mem->read(memReq, data);
 266         memReq->paddr = dest_addr;
 267         thread->mem->write(memReq, data);
 268         if (dcacheInterface) {
 269             memReq->cmd = Copy;
 270             memReq->completionEvent = NULL;
 271             memReq->paddr = thread->copySrcPhysAddr;
 272             memReq->dest = dest_addr;
 273             memReq->size = 64;
 274             memReq->time = curTick;
 275             memReq->flags &= ~INST_READ;
 276             dcacheInterface->access(memReq);
 277         }
 278     }
 279     else
 280         assert(!fault->isAlignmentFault());
 281
 282     return fault;
 283 #else
 284     panic("copy not implemented");
 285     return NoFault;
 286 #endif
 287 }
 288
 289 #if FULL_SYSTEM
 290 Addr
 291 BaseSimpleCPU::dbg_vtophys(Addr addr)
 292 {
 293     return vtophys(tc, addr);
 294 }
 295 #endif // FULL_SYSTEM
 296
 297 #if FULL_SYSTEM
 298 void
 299 BaseSimpleCPU::post_interrupt(int int_num, int index)
 300 {
 301     BaseCPU::post_interrupt(int_num, index);
 302
 303     if (thread->status() == ThreadContext::Suspended) {
 304                 DPRINTF(IPI,"Suspended Processor awoke\n");
 305         thread->activate();
 306     }
 307 }
 308 #endif // FULL_SYSTEM
 309
 310 void
 311 BaseSimpleCPU::checkForInterrupts()
 312 {
 313 #if FULL_SYSTEM
 314     if (checkInterrupts && check_interrupts() && !thread->inPalMode()) {
 315         int ipl = 0;
 316         int summary = 0;
 317         checkInterrupts = false;
 318
 319         if (thread->readMiscReg(IPR_SIRR)) {
 320             for (int i = INTLEVEL_SOFTWARE_MIN;
 321                  i < INTLEVEL_SOFTWARE_MAX; i++) {
 322                 if (thread->readMiscReg(IPR_SIRR) & (ULL(1) << i)) {
 323                     // See table 4-19 of 21164 hardware reference
 324                     ipl = (i - INTLEVEL_SOFTWARE_MIN) + 1;
 325                     summary |= (ULL(1) << i);
 326                 }
 327             }
 328         }
 329
 330         uint64_t interrupts = thread->cpu->intr_status();
 331         for (int i = INTLEVEL_EXTERNAL_MIN;
 332             i < INTLEVEL_EXTERNAL_MAX; i++) {
 333             if (interrupts & (ULL(1) << i)) {
 334                 // See table 4-19 of 21164 hardware reference
 335                 ipl = i;
 336                 summary |= (ULL(1) << i);
 337             }
 338         }
 339
 340         if (thread->readMiscReg(IPR_ASTRR))
 341             panic("asynchronous traps not implemented\n");
 342
 343         if (ipl && ipl > thread->readMiscReg(IPR_IPLR)) {
 344             thread->setMiscReg(IPR_ISR, summary);
 345             thread->setMiscReg(IPR_INTID, ipl);
 346
 347             Fault(new InterruptFault)->invoke(tc);
 348
 349             DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
 350                     thread->readMiscReg(IPR_IPLR), ipl, summary);
 351         }
 352     }
 353 #endif
 354 }
 355
 356
 357 Fault
 358 BaseSimpleCPU::setupFetchRequest(Request *req)
 359 {
 360     // set up memory request for instruction fetch
 361 #if ISA_HAS_DELAY_SLOT
 362     DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",thread->readPC(),
 363             thread->readNextPC(),thread->readNextNPC());
 364 #else
 365     DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p",thread->readPC(),
 366             thread->readNextPC());
 367 #endif
 368
 369     req->setVirt(0, thread->readPC() & ~3, sizeof(MachInst),
 370                  (FULL_SYSTEM && (thread->readPC() & 1)) ? PHYSICAL : 0,
 371                  thread->readPC());
 372
 373     Fault fault = thread->translateInstReq(req);
 374
 375     return fault;
 376 }
 377
 378
 379 void
 380 BaseSimpleCPU::preExecute()
 381 {
 382     // maintain $r0 semantics
 383     thread->setIntReg(ZeroReg, 0);
 384 #if THE_ISA == ALPHA_ISA
 385     thread->setFloatReg(ZeroReg, 0.0);
 386 #endif // ALPHA_ISA
 387
 388     // keep an instruction count
 389     numInst++;
 390     numInsts++;
 391
 392     thread->funcExeInst++;
 393
 394     // check for instruction-count-based events
 395     comInstEventQueue[0]->serviceEvents(numInst);
 396
 397     // decode the instruction
 398     inst = gtoh(inst);
 399     //If we're not in the middle of a macro instruction
 400     if (!curMacroStaticInst) {
 401         StaticInstPtr instPtr = StaticInst::decode(makeExtMI(inst, thread->getTC()));
 402         if (instPtr->isMacroOp()) {
 403             curMacroStaticInst = instPtr;
 404             curStaticInst = curMacroStaticInst->fetchMicroOp(0);
 405         } else {
 406             curStaticInst = instPtr;
 407         }
 408     } else {
 409         //Read the next micro op from the macro op
 410         curStaticInst = curMacroStaticInst->fetchMicroOp(thread->readMicroPC());
 411     }
 412
 413
 414     traceData = Trace::getInstRecord(curTick, tc, curStaticInst,
 415                                      thread->readPC());
 416
 417     DPRINTF(Decode,"Decode: Decoded %s instruction (opcode: 0x%x): 0x%x\n",
 418             curStaticInst->getName(), curStaticInst->getOpcode(),
 419             curStaticInst->machInst);
 420
 421 #if FULL_SYSTEM
 422     thread->setInst(inst);
 423 #endif // FULL_SYSTEM
 424 }
 425
 426 void
 427 BaseSimpleCPU::postExecute()
 428 {
 429 #if FULL_SYSTEM
 430     if (thread->profile) {
 431         bool usermode =
 432             (thread->readMiscReg(AlphaISA::IPR_DTB_CM) & 0x18) != 0;
 433         thread->profilePC = usermode ? 1 : thread->readPC();
 434         ProfileNode *node = thread->profile->consume(tc, inst);
 435         if (node)
 436             thread->profileNode = node;
 437     }
 438 #endif
 439
 440     if (curStaticInst->isMemRef()) {
 441         numMemRefs++;
 442     }
 443
 444     if (curStaticInst->isLoad()) {
 445         ++numLoad;
 446         comLoadEventQueue[0]->serviceEvents(numLoad);
 447     }
 448
 449     traceFunctions(thread->readPC());
 450
 451     if (traceData) {
 452         traceData->finalize();
 453     }
 454 }
 455
 456
 457 void
 458 BaseSimpleCPU::advancePC(Fault fault)
 459 {
 460     if (fault != NoFault) {
 461         fault->invoke(tc);
 462     } else {
 463         //If we're at the last micro op for this instruction
 464         if (curStaticInst->isLastMicroOp()) {
 465             //We should be working with a macro op
 466             assert(curMacroStaticInst);
 467             //Close out this macro op, and clean up the
 468             //microcode state
 469             curMacroStaticInst = StaticInst::nullStaticInstPtr;
 470             thread->setMicroPC(0);
 471             thread->setNextMicroPC(1);
 472         }
 473         //If we're still in a macro op
 474         if (curMacroStaticInst) {
 475             //Advance the micro pc
 476             thread->setMicroPC(thread->readNextMicroPC());
 477             //Advance the "next" micro pc. Note that there are no delay
 478             //slots, and micro ops are "word" addressed.
 479             thread->setNextMicroPC(thread->readNextMicroPC() + 1);
 480         } else {
 481             // go to the next instruction
 482             thread->setPC(thread->readNextPC());
 483 #if ISA_HAS_DELAY_SLOT
 484             thread->setNextPC(thread->readNextNPC());
 485             thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
 486             assert(thread->readNextPC() != thread->readNextNPC());
 487 #else
 488             thread->setNextPC(thread->readNextPC() + sizeof(MachInst));
 489 #endif
 490         }
 491     }
 492
 493 #if FULL_SYSTEM
 494     Addr oldpc;
 495     do {
 496         oldpc = thread->readPC();
 497         system->pcEventQueue.service(tc);
 498     } while (oldpc != thread->readPC());
 499 #endif
 500 }
 501