src/cpu/simple/base.cc

   1 /*
   2  * Copyright (c) 2010-2012, 2015, 2017, 2018 ARM Limited
   3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
   4  * All rights reserved
   5  *
   6  * The license below extends only to copyright in the software and shall
   7  * not be construed as granting a license to any other intellectual
   8  * property including but not limited to intellectual property relating
   9  * to a hardware implementation of the functionality of the software
  10  * licensed hereunder.  You may use the software subject to the license
  11  * terms below provided that you ensure that this notice is replicated
  12  * unmodified and in its entirety in all distributions of the software,
  13  * modified or unmodified, in source code or in binary form.
  14  *
  15  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
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  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  */
  41
  42 #include "cpu/simple/base.hh"
  43
  44 #include "arch/stacktrace.hh"
  45 #include "arch/utility.hh"
  46 #include "base/cp_annotate.hh"
  47 #include "base/cprintf.hh"
  48 #include "base/inifile.hh"
  49 #include "base/loader/symtab.hh"
  50 #include "base/logging.hh"
  51 #include "base/pollevent.hh"
  52 #include "base/trace.hh"
  53 #include "base/types.hh"
  54 #include "config/the_isa.hh"
  55 #include "cpu/base.hh"
  56 #include "cpu/checker/cpu.hh"
  57 #include "cpu/checker/thread_context.hh"
  58 #include "cpu/exetrace.hh"
  59 #include "cpu/pred/bpred_unit.hh"
  60 #include "cpu/profile.hh"
  61 #include "cpu/simple/exec_context.hh"
  62 #include "cpu/simple_thread.hh"
  63 #include "cpu/smt.hh"
  64 #include "cpu/static_inst.hh"
  65 #include "cpu/thread_context.hh"
  66 #include "debug/Decode.hh"
  67 #include "debug/Fetch.hh"
  68 #include "debug/Quiesce.hh"
  69 #include "mem/packet.hh"
  70 #include "mem/request.hh"
  71 #include "params/BaseSimpleCPU.hh"
  72 #include "sim/byteswap.hh"
  73 #include "sim/debug.hh"
  74 #include "sim/faults.hh"
  75 #include "sim/full_system.hh"
  76 #include "sim/sim_events.hh"
  77 #include "sim/sim_object.hh"
  78 #include "sim/stats.hh"
  79 #include "sim/system.hh"
  80
  81 using namespace std;
  82 using namespace TheISA;
  83
  84 BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
  85     : BaseCPU(p),
  86       curThread(0),
  87       branchPred(p->branchPred),
  88       traceData(NULL),
  89       inst(),
  90       _status(Idle)
  91 {
  92     SimpleThread *thread;
  93
  94     for (unsigned i = 0; i < numThreads; i++) {
  95         if (FullSystem) {
  96             thread = new SimpleThread(this, i, p->system,
  97                                       p->itb, p->dtb, p->isa[i]);
  98         } else {
  99             thread = new SimpleThread(this, i, p->system, p->workload[i],
 100                                       p->itb, p->dtb, p->isa[i]);
 101         }
 102         threadInfo.push_back(new SimpleExecContext(this, thread));
 103         ThreadContext *tc = thread->getTC();
 104         threadContexts.push_back(tc);
 105     }
 106
 107     if (p->checker) {
 108         if (numThreads != 1)
 109             fatal("Checker currently does not support SMT");
 110
 111         BaseCPU *temp_checker = p->checker;
 112         checker = dynamic_cast<CheckerCPU *>(temp_checker);
 113         checker->setSystem(p->system);
 114         // Manipulate thread context
 115         ThreadContext *cpu_tc = threadContexts[0];
 116         threadContexts[0] = new CheckerThreadContext<ThreadContext>(cpu_tc, this->checker);
 117     } else {
 118         checker = NULL;
 119     }
 120 }
 121
 122 void
 123 BaseSimpleCPU::init()
 124 {
 125     BaseCPU::init();
 126
 127     for (auto tc : threadContexts) {
 128         // Initialise the ThreadContext's memory proxies
 129         tc->initMemProxies(tc);
 130     }
 131 }
 132
 133 void
 134 BaseSimpleCPU::checkPcEventQueue()
 135 {
 136     Addr oldpc, pc = threadInfo[curThread]->thread->instAddr();
 137     do {
 138         oldpc = pc;
 139         threadInfo[curThread]->thread->pcEventQueue.service(
 140                 oldpc, threadContexts[curThread]);
 141         pc = threadInfo[curThread]->thread->instAddr();
 142     } while (oldpc != pc);
 143 }
 144
 145 void
 146 BaseSimpleCPU::swapActiveThread()
 147 {
 148     if (numThreads > 1) {
 149         if ((!curStaticInst || !curStaticInst->isDelayedCommit()) &&
 150              !threadInfo[curThread]->stayAtPC) {
 151             // Swap active threads
 152             if (!activeThreads.empty()) {
 153                 curThread = activeThreads.front();
 154                 activeThreads.pop_front();
 155                 activeThreads.push_back(curThread);
 156             }
 157         }
 158     }
 159 }
 160
 161 void
 162 BaseSimpleCPU::countInst()
 163 {
 164     SimpleExecContext& t_info = *threadInfo[curThread];
 165
 166     if (!curStaticInst->isMicroop() || curStaticInst->isLastMicroop()) {
 167         t_info.numInst++;
 168         t_info.numInsts++;
 169
 170         system->totalNumInsts++;
 171         t_info.thread->funcExeInst++;
 172     }
 173     t_info.numOp++;
 174     t_info.numOps++;
 175 }
 176
 177 Counter
 178 BaseSimpleCPU::totalInsts() const
 179 {
 180     Counter total_inst = 0;
 181     for (auto& t_info : threadInfo) {
 182         total_inst += t_info->numInst;
 183     }
 184
 185     return total_inst;
 186 }
 187
 188 Counter
 189 BaseSimpleCPU::totalOps() const
 190 {
 191     Counter total_op = 0;
 192     for (auto& t_info : threadInfo) {
 193         total_op += t_info->numOp;
 194     }
 195
 196     return total_op;
 197 }
 198
 199 BaseSimpleCPU::~BaseSimpleCPU()
 200 {
 201 }
 202
 203 void
 204 BaseSimpleCPU::haltContext(ThreadID thread_num)
 205 {
 206     // for now, these are equivalent
 207     suspendContext(thread_num);
 208     updateCycleCounters(BaseCPU::CPU_STATE_SLEEP);
 209 }
 210
 211
 212 void
 213 BaseSimpleCPU::regStats()
 214 {
 215     using namespace Stats;
 216
 217     BaseCPU::regStats();
 218
 219     for (ThreadID tid = 0; tid < numThreads; tid++) {
 220         SimpleExecContext& t_info = *threadInfo[tid];
 221
 222         std::string thread_str = name();
 223         if (numThreads > 1)
 224             thread_str += ".thread" + std::to_string(tid);
 225
 226         t_info.numInsts
 227             .name(thread_str + ".committedInsts")
 228             .desc("Number of instructions committed")
 229             ;
 230
 231         t_info.numOps
 232             .name(thread_str + ".committedOps")
 233             .desc("Number of ops (including micro ops) committed")
 234             ;
 235
 236         t_info.numIntAluAccesses
 237             .name(thread_str + ".num_int_alu_accesses")
 238             .desc("Number of integer alu accesses")
 239             ;
 240
 241         t_info.numFpAluAccesses
 242             .name(thread_str + ".num_fp_alu_accesses")
 243             .desc("Number of float alu accesses")
 244             ;
 245
 246         t_info.numVecAluAccesses
 247             .name(thread_str + ".num_vec_alu_accesses")
 248             .desc("Number of vector alu accesses")
 249             ;
 250
 251         t_info.numCallsReturns
 252             .name(thread_str + ".num_func_calls")
 253             .desc("number of times a function call or return occured")
 254             ;
 255
 256         t_info.numCondCtrlInsts
 257             .name(thread_str + ".num_conditional_control_insts")
 258             .desc("number of instructions that are conditional controls")
 259             ;
 260
 261         t_info.numIntInsts
 262             .name(thread_str + ".num_int_insts")
 263             .desc("number of integer instructions")
 264             ;
 265
 266         t_info.numFpInsts
 267             .name(thread_str + ".num_fp_insts")
 268             .desc("number of float instructions")
 269             ;
 270
 271         t_info.numVecInsts
 272             .name(thread_str + ".num_vec_insts")
 273             .desc("number of vector instructions")
 274             ;
 275
 276         t_info.numIntRegReads
 277             .name(thread_str + ".num_int_register_reads")
 278             .desc("number of times the integer registers were read")
 279             ;
 280
 281         t_info.numIntRegWrites
 282             .name(thread_str + ".num_int_register_writes")
 283             .desc("number of times the integer registers were written")
 284             ;
 285
 286         t_info.numFpRegReads
 287             .name(thread_str + ".num_fp_register_reads")
 288             .desc("number of times the floating registers were read")
 289             ;
 290
 291         t_info.numFpRegWrites
 292             .name(thread_str + ".num_fp_register_writes")
 293             .desc("number of times the floating registers were written")
 294             ;
 295
 296         t_info.numVecRegReads
 297             .name(thread_str + ".num_vec_register_reads")
 298             .desc("number of times the vector registers were read")
 299             ;
 300
 301         t_info.numVecRegWrites
 302             .name(thread_str + ".num_vec_register_writes")
 303             .desc("number of times the vector registers were written")
 304             ;
 305
 306         t_info.numCCRegReads
 307             .name(thread_str + ".num_cc_register_reads")
 308             .desc("number of times the CC registers were read")
 309             .flags(nozero)
 310             ;
 311
 312         t_info.numCCRegWrites
 313             .name(thread_str + ".num_cc_register_writes")
 314             .desc("number of times the CC registers were written")
 315             .flags(nozero)
 316             ;
 317
 318         t_info.numMemRefs
 319             .name(thread_str + ".num_mem_refs")
 320             .desc("number of memory refs")
 321             ;
 322
 323         t_info.numStoreInsts
 324             .name(thread_str + ".num_store_insts")
 325             .desc("Number of store instructions")
 326             ;
 327
 328         t_info.numLoadInsts
 329             .name(thread_str + ".num_load_insts")
 330             .desc("Number of load instructions")
 331             ;
 332
 333         t_info.notIdleFraction
 334             .name(thread_str + ".not_idle_fraction")
 335             .desc("Percentage of non-idle cycles")
 336             ;
 337
 338         t_info.idleFraction
 339             .name(thread_str + ".idle_fraction")
 340             .desc("Percentage of idle cycles")
 341             ;
 342
 343         t_info.numBusyCycles
 344             .name(thread_str + ".num_busy_cycles")
 345             .desc("Number of busy cycles")
 346             ;
 347
 348         t_info.numIdleCycles
 349             .name(thread_str + ".num_idle_cycles")
 350             .desc("Number of idle cycles")
 351             ;
 352
 353         t_info.icacheStallCycles
 354             .name(thread_str + ".icache_stall_cycles")
 355             .desc("ICache total stall cycles")
 356             .prereq(t_info.icacheStallCycles)
 357             ;
 358
 359         t_info.dcacheStallCycles
 360             .name(thread_str + ".dcache_stall_cycles")
 361             .desc("DCache total stall cycles")
 362             .prereq(t_info.dcacheStallCycles)
 363             ;
 364
 365         t_info.statExecutedInstType
 366             .init(Enums::Num_OpClass)
 367             .name(thread_str + ".op_class")
 368             .desc("Class of executed instruction")
 369             .flags(total | pdf | dist)
 370             ;
 371
 372         for (unsigned i = 0; i < Num_OpClasses; ++i) {
 373             t_info.statExecutedInstType.subname(i, Enums::OpClassStrings[i]);
 374         }
 375
 376         t_info.idleFraction = constant(1.0) - t_info.notIdleFraction;
 377         t_info.numIdleCycles = t_info.idleFraction * numCycles;
 378         t_info.numBusyCycles = t_info.notIdleFraction * numCycles;
 379
 380         t_info.numBranches
 381             .name(thread_str + ".Branches")
 382             .desc("Number of branches fetched")
 383             .prereq(t_info.numBranches);
 384
 385         t_info.numPredictedBranches
 386             .name(thread_str + ".predictedBranches")
 387             .desc("Number of branches predicted as taken")
 388             .prereq(t_info.numPredictedBranches);
 389
 390         t_info.numBranchMispred
 391             .name(thread_str + ".BranchMispred")
 392             .desc("Number of branch mispredictions")
 393             .prereq(t_info.numBranchMispred);
 394     }
 395 }
 396
 397 void
 398 BaseSimpleCPU::resetStats()
 399 {
 400     for (auto &thread_info : threadInfo) {
 401         thread_info->notIdleFraction = (_status != Idle);
 402     }
 403 }
 404
 405 void
 406 BaseSimpleCPU::serializeThread(CheckpointOut &cp, ThreadID tid) const
 407 {
 408     assert(_status == Idle || _status == Running);
 409
 410     threadInfo[tid]->thread->serialize(cp);
 411 }
 412
 413 void
 414 BaseSimpleCPU::unserializeThread(CheckpointIn &cp, ThreadID tid)
 415 {
 416     threadInfo[tid]->thread->unserialize(cp);
 417 }
 418
 419 void
 420 change_thread_state(ThreadID tid, int activate, int priority)
 421 {
 422 }
 423
 424 void
 425 BaseSimpleCPU::wakeup(ThreadID tid)
 426 {
 427     getCpuAddrMonitor(tid)->gotWakeup = true;
 428
 429     if (threadInfo[tid]->thread->status() == ThreadContext::Suspended) {
 430         DPRINTF(Quiesce,"[tid:%d] Suspended Processor awoke\n", tid);
 431         threadInfo[tid]->thread->activate();
 432     }
 433 }
 434
 435 void
 436 BaseSimpleCPU::checkForInterrupts()
 437 {
 438     SimpleExecContext&t_info = *threadInfo[curThread];
 439     SimpleThread* thread = t_info.thread;
 440     ThreadContext* tc = thread->getTC();
 441
 442     if (checkInterrupts(curThread)) {
 443         Fault interrupt = interrupts[curThread]->getInterrupt();
 444
 445         if (interrupt != NoFault) {
 446             t_info.fetchOffset = 0;
 447             interrupts[curThread]->updateIntrInfo();
 448             interrupt->invoke(tc);
 449             thread->decoder.reset();
 450         }
 451     }
 452 }
 453
 454
 455 void
 456 BaseSimpleCPU::setupFetchRequest(const RequestPtr &req)
 457 {
 458     SimpleExecContext &t_info = *threadInfo[curThread];
 459     SimpleThread* thread = t_info.thread;
 460
 461     Addr instAddr = thread->instAddr();
 462     Addr fetchPC = (instAddr & PCMask) + t_info.fetchOffset;
 463
 464     // set up memory request for instruction fetch
 465     DPRINTF(Fetch, "Fetch: Inst PC:%08p, Fetch PC:%08p\n", instAddr, fetchPC);
 466
 467     req->setVirt(fetchPC, sizeof(MachInst), Request::INST_FETCH,
 468                  instMasterId(), instAddr);
 469 }
 470
 471
 472 void
 473 BaseSimpleCPU::preExecute()
 474 {
 475     SimpleExecContext &t_info = *threadInfo[curThread];
 476     SimpleThread* thread = t_info.thread;
 477
 478     // maintain $r0 semantics
 479     thread->setIntReg(ZeroReg, 0);
 480
 481     // resets predicates
 482     t_info.setPredicate(true);
 483     t_info.setMemAccPredicate(true);
 484
 485     // check for instruction-count-based events
 486     thread->comInstEventQueue.serviceEvents(t_info.numInst);
 487
 488     // decode the instruction
 489     TheISA::PCState pcState = thread->pcState();
 490
 491     if (isRomMicroPC(pcState.microPC())) {
 492         t_info.stayAtPC = false;
 493         curStaticInst = microcodeRom.fetchMicroop(pcState.microPC(),
 494                                                   curMacroStaticInst);
 495     } else if (!curMacroStaticInst) {
 496         //We're not in the middle of a macro instruction
 497         StaticInstPtr instPtr = NULL;
 498
 499         TheISA::Decoder *decoder = &(thread->decoder);
 500
 501         //Predecode, ie bundle up an ExtMachInst
 502         //If more fetch data is needed, pass it in.
 503         Addr fetchPC = (pcState.instAddr() & PCMask) + t_info.fetchOffset;
 504         //if (decoder->needMoreBytes())
 505             decoder->moreBytes(pcState, fetchPC, inst);
 506         //else
 507         //    decoder->process();
 508
 509         //Decode an instruction if one is ready. Otherwise, we'll have to
 510         //fetch beyond the MachInst at the current pc.
 511         instPtr = decoder->decode(pcState);
 512         if (instPtr) {
 513             t_info.stayAtPC = false;
 514             thread->pcState(pcState);
 515         } else {
 516             t_info.stayAtPC = true;
 517             t_info.fetchOffset += sizeof(MachInst);
 518         }
 519
 520         //If we decoded an instruction and it's microcoded, start pulling
 521         //out micro ops
 522         if (instPtr && instPtr->isMacroop()) {
 523             curMacroStaticInst = instPtr;
 524             curStaticInst =
 525                 curMacroStaticInst->fetchMicroop(pcState.microPC());
 526         } else {
 527             curStaticInst = instPtr;
 528         }
 529     } else {
 530         //Read the next micro op from the macro op
 531         curStaticInst = curMacroStaticInst->fetchMicroop(pcState.microPC());
 532     }
 533
 534     //If we decoded an instruction this "tick", record information about it.
 535     if (curStaticInst) {
 536 #if TRACING_ON
 537         traceData = tracer->getInstRecord(curTick(), thread->getTC(),
 538                 curStaticInst, thread->pcState(), curMacroStaticInst);
 539
 540         DPRINTF(Decode,"Decode: Decoded %s instruction: %#x\n",
 541                 curStaticInst->getName(), curStaticInst->machInst);
 542 #endif // TRACING_ON
 543     }
 544
 545     if (branchPred && curStaticInst &&
 546         curStaticInst->isControl()) {
 547         // Use a fake sequence number since we only have one
 548         // instruction in flight at the same time.
 549         const InstSeqNum cur_sn(0);
 550         t_info.predPC = thread->pcState();
 551         const bool predict_taken(
 552             branchPred->predict(curStaticInst, cur_sn, t_info.predPC,
 553                                 curThread));
 554
 555         if (predict_taken)
 556             ++t_info.numPredictedBranches;
 557     }
 558 }
 559
 560 void
 561 BaseSimpleCPU::postExecute()
 562 {
 563     SimpleExecContext &t_info = *threadInfo[curThread];
 564     SimpleThread* thread = t_info.thread;
 565
 566     assert(curStaticInst);
 567
 568     TheISA::PCState pc = threadContexts[curThread]->pcState();
 569     Addr instAddr = pc.instAddr();
 570     if (FullSystem && thread->profile) {
 571         bool usermode = TheISA::inUserMode(threadContexts[curThread]);
 572         thread->profilePC = usermode ? 1 : instAddr;
 573         ProfileNode *node = thread->profile->consume(threadContexts[curThread],
 574                                                      curStaticInst);
 575         if (node)
 576             thread->profileNode = node;
 577     }
 578
 579     if (curStaticInst->isMemRef()) {
 580         t_info.numMemRefs++;
 581     }
 582
 583     if (curStaticInst->isLoad()) {
 584         ++t_info.numLoad;
 585     }
 586
 587     if (CPA::available()) {
 588         CPA::cpa()->swAutoBegin(threadContexts[curThread], pc.nextInstAddr());
 589     }
 590
 591     if (curStaticInst->isControl()) {
 592         ++t_info.numBranches;
 593     }
 594
 595     /* Power model statistics */
 596     //integer alu accesses
 597     if (curStaticInst->isInteger()){
 598         t_info.numIntAluAccesses++;
 599         t_info.numIntInsts++;
 600     }
 601
 602     //float alu accesses
 603     if (curStaticInst->isFloating()){
 604         t_info.numFpAluAccesses++;
 605         t_info.numFpInsts++;
 606     }
 607
 608     //vector alu accesses
 609     if (curStaticInst->isVector()){
 610         t_info.numVecAluAccesses++;
 611         t_info.numVecInsts++;
 612     }
 613
 614     //number of function calls/returns to get window accesses
 615     if (curStaticInst->isCall() || curStaticInst->isReturn()){
 616         t_info.numCallsReturns++;
 617     }
 618
 619     //the number of branch predictions that will be made
 620     if (curStaticInst->isCondCtrl()){
 621         t_info.numCondCtrlInsts++;
 622     }
 623
 624     //result bus acceses
 625     if (curStaticInst->isLoad()){
 626         t_info.numLoadInsts++;
 627     }
 628
 629     if (curStaticInst->isStore() || curStaticInst->isAtomic()){
 630         t_info.numStoreInsts++;
 631     }
 632     /* End power model statistics */
 633
 634     t_info.statExecutedInstType[curStaticInst->opClass()]++;
 635
 636     if (FullSystem)
 637         traceFunctions(instAddr);
 638
 639     if (traceData) {
 640         traceData->dump();
 641         delete traceData;
 642         traceData = NULL;
 643     }
 644
 645     // Call CPU instruction commit probes
 646     probeInstCommit(curStaticInst, instAddr);
 647 }
 648
 649 void
 650 BaseSimpleCPU::advancePC(const Fault &fault)
 651 {
 652     SimpleExecContext &t_info = *threadInfo[curThread];
 653     SimpleThread* thread = t_info.thread;
 654
 655     const bool branching(thread->pcState().branching());
 656
 657     //Since we're moving to a new pc, zero out the offset
 658     t_info.fetchOffset = 0;
 659     if (fault != NoFault) {
 660         curMacroStaticInst = StaticInst::nullStaticInstPtr;
 661         fault->invoke(threadContexts[curThread], curStaticInst);
 662         thread->decoder.reset();
 663     } else {
 664         if (curStaticInst) {
 665             if (curStaticInst->isLastMicroop())
 666                 curMacroStaticInst = StaticInst::nullStaticInstPtr;
 667             TheISA::PCState pcState = thread->pcState();
 668             TheISA::advancePC(pcState, curStaticInst);
 669             thread->pcState(pcState);
 670         }
 671     }
 672
 673     if (branchPred && curStaticInst && curStaticInst->isControl()) {
 674         // Use a fake sequence number since we only have one
 675         // instruction in flight at the same time.
 676         const InstSeqNum cur_sn(0);
 677
 678         if (t_info.predPC == thread->pcState()) {
 679             // Correctly predicted branch
 680             branchPred->update(cur_sn, curThread);
 681         } else {
 682             // Mis-predicted branch
 683             branchPred->squash(cur_sn, thread->pcState(), branching, curThread);
 684             ++t_info.numBranchMispred;
 685         }
 686     }
 687 }