2 * Copyright (c) 2010-2011 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Steve Reinhardt
43 #include "arch/kernel_stats.hh"
44 #include "arch/stacktrace.hh"
45 #include "arch/tlb.hh"
46 #include "arch/utility.hh"
47 #include "arch/vtophys.hh"
48 #include "base/loader/symtab.hh"
49 #include "base/cp_annotate.hh"
50 #include "base/cprintf.hh"
51 #include "base/inifile.hh"
52 #include "base/misc.hh"
53 #include "base/pollevent.hh"
54 #include "base/range.hh"
55 #include "base/trace.hh"
56 #include "base/types.hh"
57 #include "config/the_isa.hh"
58 #include "cpu/simple/base.hh"
59 #include "cpu/base.hh"
60 #include "cpu/checker/cpu.hh"
61 #include "cpu/checker/thread_context.hh"
62 #include "cpu/exetrace.hh"
63 #include "cpu/profile.hh"
64 #include "cpu/simple_thread.hh"
66 #include "cpu/static_inst.hh"
67 #include "cpu/thread_context.hh"
68 #include "debug/Decode.hh"
69 #include "debug/Fetch.hh"
70 #include "debug/Quiesce.hh"
71 #include "mem/mem_object.hh"
72 #include "mem/packet.hh"
73 #include "mem/request.hh"
74 #include "params/BaseSimpleCPU.hh"
75 #include "sim/byteswap.hh"
76 #include "sim/debug.hh"
77 #include "sim/faults.hh"
78 #include "sim/full_system.hh"
79 #include "sim/sim_events.hh"
80 #include "sim/sim_object.hh"
81 #include "sim/stats.hh"
82 #include "sim/system.hh"
85 using namespace TheISA
;
87 BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams
*p
)
88 : BaseCPU(p
), traceData(NULL
), thread(NULL
)
91 thread
= new SimpleThread(this, 0, p
->system
, p
->itb
, p
->dtb
);
93 thread
= new SimpleThread(this, /* thread_num */ 0, p
->system
,
94 p
->workload
[0], p
->itb
, p
->dtb
);
96 thread
->setStatus(ThreadContext::Halted
);
101 BaseCPU
*temp_checker
= p
->checker
;
102 checker
= dynamic_cast<CheckerCPU
*>(temp_checker
);
103 checker
->setSystem(p
->system
);
104 // Manipulate thread context
105 ThreadContext
*cpu_tc
= tc
;
106 tc
= new CheckerThreadContext
<ThreadContext
>(cpu_tc
, this->checker
);
120 threadContexts
.push_back(tc
);
127 BaseSimpleCPU::~BaseSimpleCPU()
132 BaseSimpleCPU::deallocateContext(ThreadID thread_num
)
134 // for now, these are equivalent
135 suspendContext(thread_num
);
140 BaseSimpleCPU::haltContext(ThreadID thread_num
)
142 // for now, these are equivalent
143 suspendContext(thread_num
);
148 BaseSimpleCPU::regStats()
150 using namespace Stats
;
155 .name(name() + ".committedInsts")
156 .desc("Number of instructions committed")
160 .name(name() + ".committedOps")
161 .desc("Number of ops (including micro ops) committed")
165 .name(name() + ".num_int_alu_accesses")
166 .desc("Number of integer alu accesses")
170 .name(name() + ".num_fp_alu_accesses")
171 .desc("Number of float alu accesses")
175 .name(name() + ".num_func_calls")
176 .desc("number of times a function call or return occured")
180 .name(name() + ".num_conditional_control_insts")
181 .desc("number of instructions that are conditional controls")
185 .name(name() + ".num_int_insts")
186 .desc("number of integer instructions")
190 .name(name() + ".num_fp_insts")
191 .desc("number of float instructions")
195 .name(name() + ".num_int_register_reads")
196 .desc("number of times the integer registers were read")
200 .name(name() + ".num_int_register_writes")
201 .desc("number of times the integer registers were written")
205 .name(name() + ".num_fp_register_reads")
206 .desc("number of times the floating registers were read")
210 .name(name() + ".num_fp_register_writes")
211 .desc("number of times the floating registers were written")
215 .name(name()+".num_mem_refs")
216 .desc("number of memory refs")
220 .name(name() + ".num_store_insts")
221 .desc("Number of store instructions")
225 .name(name() + ".num_load_insts")
226 .desc("Number of load instructions")
230 .name(name() + ".not_idle_fraction")
231 .desc("Percentage of non-idle cycles")
235 .name(name() + ".idle_fraction")
236 .desc("Percentage of idle cycles")
240 .name(name() + ".num_busy_cycles")
241 .desc("Number of busy cycles")
245 .name(name()+".num_idle_cycles")
246 .desc("Number of idle cycles")
250 .name(name() + ".icache_stall_cycles")
251 .desc("ICache total stall cycles")
252 .prereq(icacheStallCycles
)
256 .name(name() + ".dcache_stall_cycles")
257 .desc("DCache total stall cycles")
258 .prereq(dcacheStallCycles
)
262 .name(name() + ".icache_retry_cycles")
263 .desc("ICache total retry cycles")
264 .prereq(icacheRetryCycles
)
268 .name(name() + ".dcache_retry_cycles")
269 .desc("DCache total retry cycles")
270 .prereq(dcacheRetryCycles
)
273 idleFraction
= constant(1.0) - notIdleFraction
;
274 numIdleCycles
= idleFraction
* numCycles
;
275 numBusyCycles
= (notIdleFraction
)*numCycles
;
279 BaseSimpleCPU::resetStats()
281 // startNumInst = numInst;
282 notIdleFraction
= (_status
!= Idle
);
286 BaseSimpleCPU::serialize(ostream
&os
)
288 SERIALIZE_ENUM(_status
);
289 BaseCPU::serialize(os
);
290 // SERIALIZE_SCALAR(inst);
291 nameOut(os
, csprintf("%s.xc.0", name()));
292 thread
->serialize(os
);
296 BaseSimpleCPU::unserialize(Checkpoint
*cp
, const string
§ion
)
298 UNSERIALIZE_ENUM(_status
);
299 BaseCPU::unserialize(cp
, section
);
300 // UNSERIALIZE_SCALAR(inst);
301 thread
->unserialize(cp
, csprintf("%s.xc.0", section
));
305 change_thread_state(ThreadID tid
, int activate
, int priority
)
310 BaseSimpleCPU::dbg_vtophys(Addr addr
)
312 return vtophys(tc
, addr
);
316 BaseSimpleCPU::wakeup()
318 if (thread
->status() != ThreadContext::Suspended
)
321 DPRINTF(Quiesce
,"Suspended Processor awoke\n");
326 BaseSimpleCPU::checkForInterrupts()
328 if (checkInterrupts(tc
)) {
329 Fault interrupt
= interrupts
->getInterrupt(tc
);
331 if (interrupt
!= NoFault
) {
333 interrupts
->updateIntrInfo(tc
);
334 interrupt
->invoke(tc
);
335 thread
->decoder
.reset();
342 BaseSimpleCPU::setupFetchRequest(Request
*req
)
344 Addr instAddr
= thread
->instAddr();
346 // set up memory request for instruction fetch
347 DPRINTF(Fetch
, "Fetch: PC:%08p\n", instAddr
);
349 Addr fetchPC
= (instAddr
& PCMask
) + fetchOffset
;
350 req
->setVirt(0, fetchPC
, sizeof(MachInst
), Request::INST_FETCH
, instMasterId(),
356 BaseSimpleCPU::preExecute()
358 // maintain $r0 semantics
359 thread
->setIntReg(ZeroReg
, 0);
360 #if THE_ISA == ALPHA_ISA
361 thread
->setFloatReg(ZeroReg
, 0.0);
364 // check for instruction-count-based events
365 comInstEventQueue
[0]->serviceEvents(numInst
);
366 system
->instEventQueue
.serviceEvents(system
->totalNumInsts
);
368 // decode the instruction
371 TheISA::PCState pcState
= thread
->pcState();
373 if (isRomMicroPC(pcState
.microPC())) {
375 curStaticInst
= microcodeRom
.fetchMicroop(pcState
.microPC(),
377 } else if (!curMacroStaticInst
) {
378 //We're not in the middle of a macro instruction
379 StaticInstPtr instPtr
= NULL
;
381 TheISA::Decoder
*decoder
= &(thread
->decoder
);
383 //Predecode, ie bundle up an ExtMachInst
384 //This should go away once the constructor can be set up properly
385 decoder
->setTC(thread
->getTC());
386 //If more fetch data is needed, pass it in.
387 Addr fetchPC
= (pcState
.instAddr() & PCMask
) + fetchOffset
;
388 //if(decoder->needMoreBytes())
389 decoder
->moreBytes(pcState
, fetchPC
, inst
);
391 // decoder->process();
393 //Decode an instruction if one is ready. Otherwise, we'll have to
394 //fetch beyond the MachInst at the current pc.
395 instPtr
= decoder
->decode(pcState
);
398 thread
->pcState(pcState
);
401 fetchOffset
+= sizeof(MachInst
);
404 //If we decoded an instruction and it's microcoded, start pulling
406 if (instPtr
&& instPtr
->isMacroop()) {
407 curMacroStaticInst
= instPtr
;
408 curStaticInst
= curMacroStaticInst
->fetchMicroop(pcState
.microPC());
410 curStaticInst
= instPtr
;
413 //Read the next micro op from the macro op
414 curStaticInst
= curMacroStaticInst
->fetchMicroop(pcState
.microPC());
417 //If we decoded an instruction this "tick", record information about it.
420 traceData
= tracer
->getInstRecord(curTick(), tc
,
421 curStaticInst
, thread
->pcState(), curMacroStaticInst
);
423 DPRINTF(Decode
,"Decode: Decoded %s instruction: %#x\n",
424 curStaticInst
->getName(), curStaticInst
->machInst
);
430 BaseSimpleCPU::postExecute()
432 assert(curStaticInst
);
434 TheISA::PCState pc
= tc
->pcState();
435 Addr instAddr
= pc
.instAddr();
436 if (FullSystem
&& thread
->profile
) {
437 bool usermode
= TheISA::inUserMode(tc
);
438 thread
->profilePC
= usermode
? 1 : instAddr
;
439 ProfileNode
*node
= thread
->profile
->consume(tc
, curStaticInst
);
441 thread
->profileNode
= node
;
444 if (curStaticInst
->isMemRef()) {
448 if (curStaticInst
->isLoad()) {
450 comLoadEventQueue
[0]->serviceEvents(numLoad
);
453 if (CPA::available()) {
454 CPA::cpa()->swAutoBegin(tc
, pc
.nextInstAddr());
457 /* Power model statistics */
458 //integer alu accesses
459 if (curStaticInst
->isInteger()){
465 if (curStaticInst
->isFloating()){
470 //number of function calls/returns to get window accesses
471 if (curStaticInst
->isCall() || curStaticInst
->isReturn()){
475 //the number of branch predictions that will be made
476 if (curStaticInst
->isCondCtrl()){
481 if (curStaticInst
->isLoad()){
485 if (curStaticInst
->isStore()){
488 /* End power model statistics */
491 traceFunctions(instAddr
);
502 BaseSimpleCPU::advancePC(Fault fault
)
504 //Since we're moving to a new pc, zero out the offset
506 if (fault
!= NoFault
) {
507 curMacroStaticInst
= StaticInst::nullStaticInstPtr
;
508 fault
->invoke(tc
, curStaticInst
);
509 thread
->decoder
.reset();
512 if (curStaticInst
->isLastMicroop())
513 curMacroStaticInst
= StaticInst::nullStaticInstPtr
;
514 TheISA::PCState pcState
= thread
->pcState();
515 TheISA::advancePC(pcState
, curStaticInst
);
516 thread
->pcState(pcState
);
522 BaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr)
524 // translate to physical address
525 Fault fault = NoFault;
526 int CacheID = Op & 0x3; // Lower 3 bits identify Cache
527 int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation
530 warn("CacheOps not implemented for secondary/tertiary caches\n");
535 { // Fill Packet Type
536 case 0: warn("Invalidate Cache Op\n");
538 case 1: warn("Index Load Tag Cache Op\n");
540 case 2: warn("Index Store Tag Cache Op\n");
542 case 4: warn("Hit Invalidate Cache Op\n");
544 case 5: warn("Fill/Hit Writeback Invalidate Cache Op\n");
546 case 6: warn("Hit Writeback\n");
548 case 7: warn("Fetch & Lock Cache Op\n");
550 default: warn("Unimplemented Cache Op\n");