src/cpu/simple/base.cc

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  */
  30
  31 #include "arch/utility.hh"
  32 #include "arch/faults.hh"
  33 #include "base/cprintf.hh"
  34 #include "base/inifile.hh"
  35 #include "base/loader/symtab.hh"
  36 #include "base/misc.hh"
  37 #include "base/pollevent.hh"
  38 #include "base/range.hh"
  39 #include "base/stats/events.hh"
  40 #include "base/trace.hh"
  41 #include "cpu/base.hh"
  42 #include "cpu/exetrace.hh"
  43 #include "cpu/profile.hh"
  44 #include "cpu/simple/base.hh"
  45 #include "cpu/simple_thread.hh"
  46 #include "cpu/smt.hh"
  47 #include "cpu/static_inst.hh"
  48 #include "cpu/thread_context.hh"
  49 #include "mem/packet.hh"
  50 #include "sim/byteswap.hh"
  51 #include "sim/debug.hh"
  52 #include "sim/host.hh"
  53 #include "sim/sim_events.hh"
  54 #include "sim/sim_object.hh"
  55 #include "sim/stats.hh"
  56 #include "sim/system.hh"
  57
  58 #if FULL_SYSTEM
  59 #include "arch/kernel_stats.hh"
  60 #include "arch/stacktrace.hh"
  61 #include "arch/tlb.hh"
  62 #include "arch/vtophys.hh"
  63 #include "base/remote_gdb.hh"
  64 #else // !FULL_SYSTEM
  65 #include "mem/mem_object.hh"
  66 #endif // FULL_SYSTEM
  67
  68 #include "params/BaseSimpleCPU.hh"
  69
  70 using namespace std;
  71 using namespace TheISA;
  72
  73 BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
  74     : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL)
  75 {
  76 #if FULL_SYSTEM
  77     thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
  78 #else
  79     thread = new SimpleThread(this, /* thread_num */ 0, p->workload[0],
  80             p->itb, p->dtb, /* asid */ 0);
  81 #endif // !FULL_SYSTEM
  82
  83     thread->setStatus(ThreadContext::Unallocated);
  84
  85     tc = thread->getTC();
  86
  87     numInst = 0;
  88     startNumInst = 0;
  89     numLoad = 0;
  90     startNumLoad = 0;
  91     lastIcacheStall = 0;
  92     lastDcacheStall = 0;
  93
  94     threadContexts.push_back(tc);
  95
  96
  97     fetchOffset = 0;
  98     stayAtPC = false;
  99 }
 100
 101 BaseSimpleCPU::~BaseSimpleCPU()
 102 {
 103 }
 104
 105 void
 106 BaseSimpleCPU::deallocateContext(int thread_num)
 107 {
 108     // for now, these are equivalent
 109     suspendContext(thread_num);
 110 }
 111
 112
 113 void
 114 BaseSimpleCPU::haltContext(int thread_num)
 115 {
 116     // for now, these are equivalent
 117     suspendContext(thread_num);
 118 }
 119
 120
 121 void
 122 BaseSimpleCPU::regStats()
 123 {
 124     using namespace Stats;
 125
 126     BaseCPU::regStats();
 127
 128     numInsts
 129         .name(name() + ".num_insts")
 130         .desc("Number of instructions executed")
 131         ;
 132
 133     numMemRefs
 134         .name(name() + ".num_refs")
 135         .desc("Number of memory references")
 136         ;
 137
 138     notIdleFraction
 139         .name(name() + ".not_idle_fraction")
 140         .desc("Percentage of non-idle cycles")
 141         ;
 142
 143     idleFraction
 144         .name(name() + ".idle_fraction")
 145         .desc("Percentage of idle cycles")
 146         ;
 147
 148     icacheStallCycles
 149         .name(name() + ".icache_stall_cycles")
 150         .desc("ICache total stall cycles")
 151         .prereq(icacheStallCycles)
 152         ;
 153
 154     dcacheStallCycles
 155         .name(name() + ".dcache_stall_cycles")
 156         .desc("DCache total stall cycles")
 157         .prereq(dcacheStallCycles)
 158         ;
 159
 160     icacheRetryCycles
 161         .name(name() + ".icache_retry_cycles")
 162         .desc("ICache total retry cycles")
 163         .prereq(icacheRetryCycles)
 164         ;
 165
 166     dcacheRetryCycles
 167         .name(name() + ".dcache_retry_cycles")
 168         .desc("DCache total retry cycles")
 169         .prereq(dcacheRetryCycles)
 170         ;
 171
 172     idleFraction = constant(1.0) - notIdleFraction;
 173 }
 174
 175 void
 176 BaseSimpleCPU::resetStats()
 177 {
 178 //    startNumInst = numInst;
 179      notIdleFraction = (_status != Idle);
 180 }
 181
 182 void
 183 BaseSimpleCPU::serialize(ostream &os)
 184 {
 185     SERIALIZE_ENUM(_status);
 186     BaseCPU::serialize(os);
 187 //    SERIALIZE_SCALAR(inst);
 188     nameOut(os, csprintf("%s.xc.0", name()));
 189     thread->serialize(os);
 190 }
 191
 192 void
 193 BaseSimpleCPU::unserialize(Checkpoint *cp, const string &section)
 194 {
 195     UNSERIALIZE_ENUM(_status);
 196     BaseCPU::unserialize(cp, section);
 197 //    UNSERIALIZE_SCALAR(inst);
 198     thread->unserialize(cp, csprintf("%s.xc.0", section));
 199 }
 200
 201 void
 202 change_thread_state(int thread_number, int activate, int priority)
 203 {
 204 }
 205
 206 Fault
 207 BaseSimpleCPU::copySrcTranslate(Addr src)
 208 {
 209 #if 0
 210     static bool no_warn = true;
 211     int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
 212     // Only support block sizes of 64 atm.
 213     assert(blk_size == 64);
 214     int offset = src & (blk_size - 1);
 215
 216     // Make sure block doesn't span page
 217     if (no_warn &&
 218         (src & PageMask) != ((src + blk_size) & PageMask) &&
 219         (src >> 40) != 0xfffffc) {
 220         warn("Copied block source spans pages %x.", src);
 221         no_warn = false;
 222     }
 223
 224     memReq->reset(src & ~(blk_size - 1), blk_size);
 225
 226     // translate to physical address
 227     Fault fault = thread->translateDataReadReq(req);
 228
 229     if (fault == NoFault) {
 230         thread->copySrcAddr = src;
 231         thread->copySrcPhysAddr = memReq->paddr + offset;
 232     } else {
 233         assert(!fault->isAlignmentFault());
 234
 235         thread->copySrcAddr = 0;
 236         thread->copySrcPhysAddr = 0;
 237     }
 238     return fault;
 239 #else
 240     return NoFault;
 241 #endif
 242 }
 243
 244 Fault
 245 BaseSimpleCPU::copy(Addr dest)
 246 {
 247 #if 0
 248     static bool no_warn = true;
 249     int blk_size = (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
 250     // Only support block sizes of 64 atm.
 251     assert(blk_size == 64);
 252     uint8_t data[blk_size];
 253     //assert(thread->copySrcAddr);
 254     int offset = dest & (blk_size - 1);
 255
 256     // Make sure block doesn't span page
 257     if (no_warn &&
 258         (dest & PageMask) != ((dest + blk_size) & PageMask) &&
 259         (dest >> 40) != 0xfffffc) {
 260         no_warn = false;
 261         warn("Copied block destination spans pages %x. ", dest);
 262     }
 263
 264     memReq->reset(dest & ~(blk_size -1), blk_size);
 265     // translate to physical address
 266     Fault fault = thread->translateDataWriteReq(req);
 267
 268     if (fault == NoFault) {
 269         Addr dest_addr = memReq->paddr + offset;
 270         // Need to read straight from memory since we have more than 8 bytes.
 271         memReq->paddr = thread->copySrcPhysAddr;
 272         thread->mem->read(memReq, data);
 273         memReq->paddr = dest_addr;
 274         thread->mem->write(memReq, data);
 275         if (dcacheInterface) {
 276             memReq->cmd = Copy;
 277             memReq->completionEvent = NULL;
 278             memReq->paddr = thread->copySrcPhysAddr;
 279             memReq->dest = dest_addr;
 280             memReq->size = 64;
 281             memReq->time = curTick;
 282             memReq->flags &= ~INST_READ;
 283             dcacheInterface->access(memReq);
 284         }
 285     }
 286     else
 287         assert(!fault->isAlignmentFault());
 288
 289     return fault;
 290 #else
 291     panic("copy not implemented");
 292     return NoFault;
 293 #endif
 294 }
 295
 296 #if FULL_SYSTEM
 297 Addr
 298 BaseSimpleCPU::dbg_vtophys(Addr addr)
 299 {
 300     return vtophys(tc, addr);
 301 }
 302 #endif // FULL_SYSTEM
 303
 304 #if FULL_SYSTEM
 305 void
 306 BaseSimpleCPU::wakeup()
 307 {
 308     if (thread->status() != ThreadContext::Suspended)
 309         return;
 310
 311     DPRINTF(Quiesce,"Suspended Processor awoke\n");
 312     thread->activate();
 313 }
 314 #endif // FULL_SYSTEM
 315
 316 void
 317 BaseSimpleCPU::checkForInterrupts()
 318 {
 319 #if FULL_SYSTEM
 320     if (checkInterrupts(tc)) {
 321         Fault interrupt = interrupts->getInterrupt(tc);
 322
 323         if (interrupt != NoFault) {
 324             predecoder.reset();
 325             interrupts->updateIntrInfo(tc);
 326             interrupt->invoke(tc);
 327         }
 328     }
 329 #endif
 330 }
 331
 332
 333 void
 334 BaseSimpleCPU::setupFetchRequest(Request *req)
 335 {
 336     Addr threadPC = thread->readPC();
 337
 338     // set up memory request for instruction fetch
 339 #if ISA_HAS_DELAY_SLOT
 340     DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",threadPC,
 341             thread->readNextPC(),thread->readNextNPC());
 342 #else
 343     DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p\n",threadPC,
 344             thread->readNextPC());
 345 #endif
 346
 347     Addr fetchPC = (threadPC & PCMask) + fetchOffset;
 348     req->setVirt(0, fetchPC, sizeof(MachInst), 0, threadPC);
 349 }
 350
 351
 352 void
 353 BaseSimpleCPU::preExecute()
 354 {
 355     // maintain $r0 semantics
 356     thread->setIntReg(ZeroReg, 0);
 357 #if THE_ISA == ALPHA_ISA
 358     thread->setFloatReg(ZeroReg, 0.0);
 359 #endif // ALPHA_ISA
 360
 361     // check for instruction-count-based events
 362     comInstEventQueue[0]->serviceEvents(numInst);
 363
 364     // decode the instruction
 365     inst = gtoh(inst);
 366
 367     MicroPC upc = thread->readMicroPC();
 368
 369     if (isRomMicroPC(upc)) {
 370         stayAtPC = false;
 371         curStaticInst = microcodeRom.fetchMicroop(upc, curMacroStaticInst);
 372     } else if (!curMacroStaticInst) {
 373         //We're not in the middle of a macro instruction
 374         StaticInstPtr instPtr = NULL;
 375
 376         //Predecode, ie bundle up an ExtMachInst
 377         //This should go away once the constructor can be set up properly
 378         predecoder.setTC(thread->getTC());
 379         //If more fetch data is needed, pass it in.
 380         Addr fetchPC = (thread->readPC() & PCMask) + fetchOffset;
 381         //if(predecoder.needMoreBytes())
 382             predecoder.moreBytes(thread->readPC(), fetchPC, inst);
 383         //else
 384         //    predecoder.process();
 385
 386         //If an instruction is ready, decode it. Otherwise, we'll have to
 387         //fetch beyond the MachInst at the current pc.
 388         if (predecoder.extMachInstReady()) {
 389 #if THE_ISA == X86_ISA
 390             thread->setNextPC(thread->readPC() + predecoder.getInstSize());
 391 #endif // X86_ISA
 392             stayAtPC = false;
 393             instPtr = StaticInst::decode(predecoder.getExtMachInst(),
 394                                          thread->readPC());
 395         } else {
 396             stayAtPC = true;
 397             fetchOffset += sizeof(MachInst);
 398         }
 399
 400         //If we decoded an instruction and it's microcoded, start pulling
 401         //out micro ops
 402         if (instPtr && instPtr->isMacroop()) {
 403             curMacroStaticInst = instPtr;
 404             curStaticInst = curMacroStaticInst->fetchMicroop(upc);
 405         } else {
 406             curStaticInst = instPtr;
 407         }
 408     } else {
 409         //Read the next micro op from the macro op
 410         curStaticInst = curMacroStaticInst->fetchMicroop(upc);
 411     }
 412
 413     //If we decoded an instruction this "tick", record information about it.
 414     if(curStaticInst)
 415     {
 416 #if TRACING_ON
 417         traceData = tracer->getInstRecord(curTick, tc,
 418                 curStaticInst, thread->readPC(),
 419                 curMacroStaticInst, thread->readMicroPC());
 420
 421         DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n",
 422                 curStaticInst->getName(), curStaticInst->machInst);
 423 #endif // TRACING_ON
 424
 425 #if FULL_SYSTEM
 426         thread->setInst(inst);
 427 #endif // FULL_SYSTEM
 428     }
 429 }
 430
 431 void
 432 BaseSimpleCPU::postExecute()
 433 {
 434 #if FULL_SYSTEM
 435     if (thread->profile && curStaticInst) {
 436         bool usermode = TheISA::inUserMode(tc);
 437         thread->profilePC = usermode ? 1 : thread->readPC();
 438         ProfileNode *node = thread->profile->consume(tc, curStaticInst);
 439         if (node)
 440             thread->profileNode = node;
 441     }
 442 #endif
 443
 444     if (curStaticInst->isMemRef()) {
 445         numMemRefs++;
 446     }
 447
 448     if (curStaticInst->isLoad()) {
 449         ++numLoad;
 450         comLoadEventQueue[0]->serviceEvents(numLoad);
 451     }
 452
 453     traceFunctions(thread->readPC());
 454
 455     if (traceData) {
 456         traceData->dump();
 457         delete traceData;
 458         traceData = NULL;
 459     }
 460 }
 461
 462
 463 void
 464 BaseSimpleCPU::advancePC(Fault fault)
 465 {
 466     //Since we're moving to a new pc, zero out the offset
 467     fetchOffset = 0;
 468     if (fault != NoFault) {
 469         curMacroStaticInst = StaticInst::nullStaticInstPtr;
 470         predecoder.reset();
 471         fault->invoke(tc);
 472     } else {
 473         //If we're at the last micro op for this instruction
 474         if (curStaticInst && curStaticInst->isLastMicroop()) {
 475             //We should be working with a macro op or be in the ROM
 476             assert(curMacroStaticInst ||
 477                     isRomMicroPC(thread->readMicroPC()));
 478             //Close out this macro op, and clean up the
 479             //microcode state
 480             curMacroStaticInst = StaticInst::nullStaticInstPtr;
 481             thread->setMicroPC(normalMicroPC(0));
 482             thread->setNextMicroPC(normalMicroPC(1));
 483         }
 484         //If we're still in a macro op
 485         if (curMacroStaticInst || isRomMicroPC(thread->readMicroPC())) {
 486             //Advance the micro pc
 487             thread->setMicroPC(thread->readNextMicroPC());
 488             //Advance the "next" micro pc. Note that there are no delay
 489             //slots, and micro ops are "word" addressed.
 490             thread->setNextMicroPC(thread->readNextMicroPC() + 1);
 491         } else {
 492             // go to the next instruction
 493             thread->setPC(thread->readNextPC());
 494             thread->setNextPC(thread->readNextNPC());
 495             thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
 496             assert(thread->readNextPC() != thread->readNextNPC());
 497         }
 498     }
 499 }
 500
 501 /*Fault
 502 BaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr)
 503 {
 504     // translate to physical address
 505     Fault fault = NoFault;
 506     int CacheID = Op & 0x3; // Lower 3 bits identify Cache
 507     int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation
 508     if(CacheID > 1)
 509       {
 510         warn("CacheOps not implemented for secondary/tertiary caches\n");
 511       }
 512     else
 513       {
 514         switch(CacheOP)
 515           { // Fill Packet Type
 516           case 0: warn("Invalidate Cache Op\n");
 517             break;
 518           case 1: warn("Index Load Tag Cache Op\n");
 519             break;
 520           case 2: warn("Index Store Tag Cache Op\n");
 521             break;
 522           case 4: warn("Hit Invalidate Cache Op\n");
 523             break;
 524           case 5: warn("Fill/Hit Writeback Invalidate Cache Op\n");
 525             break;
 526           case 6: warn("Hit Writeback\n");
 527             break;
 528           case 7: warn("Fetch & Lock Cache Op\n");
 529             break;
 530           default: warn("Unimplemented Cache Op\n");
 531           }
 532       }
 533     return fault;
 534 }*/