2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
31 #include "arch/utility.hh"
32 #include "arch/faults.hh"
33 #include "base/cprintf.hh"
34 #include "base/inifile.hh"
35 #include "base/loader/symtab.hh"
36 #include "base/misc.hh"
37 #include "base/pollevent.hh"
38 #include "base/range.hh"
39 #include "base/stats/events.hh"
40 #include "base/trace.hh"
41 #include "cpu/base.hh"
42 #include "cpu/exetrace.hh"
43 #include "cpu/profile.hh"
44 #include "cpu/simple/base.hh"
45 #include "cpu/simple_thread.hh"
47 #include "cpu/static_inst.hh"
48 #include "cpu/thread_context.hh"
49 #include "mem/packet.hh"
50 #include "sim/byteswap.hh"
51 #include "sim/debug.hh"
52 #include "sim/host.hh"
53 #include "sim/sim_events.hh"
54 #include "sim/sim_object.hh"
55 #include "sim/stats.hh"
56 #include "sim/system.hh"
59 #include "arch/kernel_stats.hh"
60 #include "arch/stacktrace.hh"
61 #include "arch/tlb.hh"
62 #include "arch/vtophys.hh"
63 #include "base/remote_gdb.hh"
65 #include "mem/mem_object.hh"
69 using namespace TheISA
;
71 BaseSimpleCPU::BaseSimpleCPU(Params
*p
)
72 : BaseCPU(p
), traceData(NULL
), thread(NULL
), predecoder(NULL
)
75 thread
= new SimpleThread(this, 0, p
->system
, p
->itb
, p
->dtb
);
77 thread
= new SimpleThread(this, /* thread_num */ 0, p
->process
,
78 p
->itb
, p
->dtb
, /* asid */ 0);
79 #endif // !FULL_SYSTEM
81 thread
->setStatus(ThreadContext::Unallocated
);
92 threadContexts
.push_back(tc
);
99 BaseSimpleCPU::~BaseSimpleCPU()
104 BaseSimpleCPU::deallocateContext(int thread_num
)
106 // for now, these are equivalent
107 suspendContext(thread_num
);
112 BaseSimpleCPU::haltContext(int thread_num
)
114 // for now, these are equivalent
115 suspendContext(thread_num
);
120 BaseSimpleCPU::regStats()
122 using namespace Stats
;
127 .name(name() + ".num_insts")
128 .desc("Number of instructions executed")
132 .name(name() + ".num_refs")
133 .desc("Number of memory references")
137 .name(name() + ".not_idle_fraction")
138 .desc("Percentage of non-idle cycles")
142 .name(name() + ".idle_fraction")
143 .desc("Percentage of idle cycles")
147 .name(name() + ".icache_stall_cycles")
148 .desc("ICache total stall cycles")
149 .prereq(icacheStallCycles
)
153 .name(name() + ".dcache_stall_cycles")
154 .desc("DCache total stall cycles")
155 .prereq(dcacheStallCycles
)
159 .name(name() + ".icache_retry_cycles")
160 .desc("ICache total retry cycles")
161 .prereq(icacheRetryCycles
)
165 .name(name() + ".dcache_retry_cycles")
166 .desc("DCache total retry cycles")
167 .prereq(dcacheRetryCycles
)
170 idleFraction
= constant(1.0) - notIdleFraction
;
174 BaseSimpleCPU::resetStats()
176 // startNumInst = numInst;
177 // notIdleFraction = (_status != Idle);
181 BaseSimpleCPU::serialize(ostream
&os
)
183 BaseCPU::serialize(os
);
184 // SERIALIZE_SCALAR(inst);
185 nameOut(os
, csprintf("%s.xc.0", name()));
186 thread
->serialize(os
);
190 BaseSimpleCPU::unserialize(Checkpoint
*cp
, const string
§ion
)
192 BaseCPU::unserialize(cp
, section
);
193 // UNSERIALIZE_SCALAR(inst);
194 thread
->unserialize(cp
, csprintf("%s.xc.0", section
));
198 change_thread_state(int thread_number
, int activate
, int priority
)
203 BaseSimpleCPU::copySrcTranslate(Addr src
)
206 static bool no_warn
= true;
207 int blk_size
= (dcacheInterface
) ? dcacheInterface
->getBlockSize() : 64;
208 // Only support block sizes of 64 atm.
209 assert(blk_size
== 64);
210 int offset
= src
& (blk_size
- 1);
212 // Make sure block doesn't span page
214 (src
& PageMask
) != ((src
+ blk_size
) & PageMask
) &&
215 (src
>> 40) != 0xfffffc) {
216 warn("Copied block source spans pages %x.", src
);
220 memReq
->reset(src
& ~(blk_size
- 1), blk_size
);
222 // translate to physical address
223 Fault fault
= thread
->translateDataReadReq(req
);
225 if (fault
== NoFault
) {
226 thread
->copySrcAddr
= src
;
227 thread
->copySrcPhysAddr
= memReq
->paddr
+ offset
;
229 assert(!fault
->isAlignmentFault());
231 thread
->copySrcAddr
= 0;
232 thread
->copySrcPhysAddr
= 0;
241 BaseSimpleCPU::copy(Addr dest
)
244 static bool no_warn
= true;
245 int blk_size
= (dcacheInterface
) ? dcacheInterface
->getBlockSize() : 64;
246 // Only support block sizes of 64 atm.
247 assert(blk_size
== 64);
248 uint8_t data
[blk_size
];
249 //assert(thread->copySrcAddr);
250 int offset
= dest
& (blk_size
- 1);
252 // Make sure block doesn't span page
254 (dest
& PageMask
) != ((dest
+ blk_size
) & PageMask
) &&
255 (dest
>> 40) != 0xfffffc) {
257 warn("Copied block destination spans pages %x. ", dest
);
260 memReq
->reset(dest
& ~(blk_size
-1), blk_size
);
261 // translate to physical address
262 Fault fault
= thread
->translateDataWriteReq(req
);
264 if (fault
== NoFault
) {
265 Addr dest_addr
= memReq
->paddr
+ offset
;
266 // Need to read straight from memory since we have more than 8 bytes.
267 memReq
->paddr
= thread
->copySrcPhysAddr
;
268 thread
->mem
->read(memReq
, data
);
269 memReq
->paddr
= dest_addr
;
270 thread
->mem
->write(memReq
, data
);
271 if (dcacheInterface
) {
273 memReq
->completionEvent
= NULL
;
274 memReq
->paddr
= thread
->copySrcPhysAddr
;
275 memReq
->dest
= dest_addr
;
277 memReq
->time
= curTick
;
278 memReq
->flags
&= ~INST_READ
;
279 dcacheInterface
->access(memReq
);
283 assert(!fault
->isAlignmentFault());
287 panic("copy not implemented");
294 BaseSimpleCPU::dbg_vtophys(Addr addr
)
296 return vtophys(tc
, addr
);
298 #endif // FULL_SYSTEM
302 BaseSimpleCPU::post_interrupt(int int_num
, int index
)
304 BaseCPU::post_interrupt(int_num
, index
);
306 if (thread
->status() == ThreadContext::Suspended
) {
307 DPRINTF(Quiesce
,"Suspended Processor awoke\n");
311 #endif // FULL_SYSTEM
314 BaseSimpleCPU::checkForInterrupts()
317 if (check_interrupts(tc
)) {
318 Fault interrupt
= interrupts
.getInterrupt(tc
);
320 if (interrupt
!= NoFault
) {
321 interrupts
.updateIntrInfo(tc
);
322 interrupt
->invoke(tc
);
330 BaseSimpleCPU::setupFetchRequest(Request
*req
)
332 Addr threadPC
= thread
->readPC();
334 // set up memory request for instruction fetch
335 #if ISA_HAS_DELAY_SLOT
336 DPRINTF(Fetch
,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",threadPC
,
337 thread
->readNextPC(),thread
->readNextNPC());
339 DPRINTF(Fetch
,"Fetch: PC:%08p NPC:%08p\n",threadPC
,
340 thread
->readNextPC());
343 Addr fetchPC
= (threadPC
& PCMask
) + fetchOffset
;
344 req
->setVirt(0, fetchPC
, sizeof(MachInst
), 0, threadPC
);
346 Fault fault
= thread
->translateInstReq(req
);
353 BaseSimpleCPU::preExecute()
355 // maintain $r0 semantics
356 thread
->setIntReg(ZeroReg
, 0);
357 #if THE_ISA == ALPHA_ISA
358 thread
->setFloatReg(ZeroReg
, 0.0);
361 // check for instruction-count-based events
362 comInstEventQueue
[0]->serviceEvents(numInst
);
364 // decode the instruction
367 //If we're not in the middle of a macro instruction
368 if (!curMacroStaticInst
) {
370 StaticInstPtr instPtr
= NULL
;
372 //Predecode, ie bundle up an ExtMachInst
373 //This should go away once the constructor can be set up properly
374 predecoder
.setTC(thread
->getTC());
375 //If more fetch data is needed, pass it in.
376 Addr fetchPC
= (thread
->readPC() & PCMask
) + fetchOffset
;
377 //if(predecoder.needMoreBytes())
378 predecoder
.moreBytes(thread
->readPC(), fetchPC
, inst
);
380 // predecoder.process();
382 //If an instruction is ready, decode it. Otherwise, we'll have to
383 //fetch beyond the MachInst at the current pc.
384 if (predecoder
.extMachInstReady()) {
385 #if THE_ISA == X86_ISA
386 thread
->setNextPC(thread
->readPC() + predecoder
.getInstSize());
389 instPtr
= StaticInst::decode(predecoder
.getExtMachInst(),
393 fetchOffset
+= sizeof(MachInst
);
396 //If we decoded an instruction and it's microcoded, start pulling
398 if (instPtr
&& instPtr
->isMacroop()) {
399 curMacroStaticInst
= instPtr
;
400 curStaticInst
= curMacroStaticInst
->
401 fetchMicroop(thread
->readMicroPC());
403 curStaticInst
= instPtr
;
406 //Read the next micro op from the macro op
407 curStaticInst
= curMacroStaticInst
->
408 fetchMicroop(thread
->readMicroPC());
411 //If we decoded an instruction this "tick", record information about it.
415 traceData
= tracer
->getInstRecord(curTick
, tc
, curStaticInst
,
418 DPRINTF(Decode
,"Decode: Decoded %s instruction: 0x%x\n",
419 curStaticInst
->getName(), curStaticInst
->machInst
);
423 thread
->setInst(inst
);
424 #endif // FULL_SYSTEM
429 BaseSimpleCPU::postExecute()
432 if (thread
->profile
&& curStaticInst
) {
433 bool usermode
= TheISA::inUserMode(tc
);
434 thread
->profilePC
= usermode
? 1 : thread
->readPC();
435 ProfileNode
*node
= thread
->profile
->consume(tc
, curStaticInst
);
437 thread
->profileNode
= node
;
441 if (curStaticInst
->isMemRef()) {
445 if (curStaticInst
->isLoad()) {
447 comLoadEventQueue
[0]->serviceEvents(numLoad
);
450 traceFunctions(thread
->readPC());
461 BaseSimpleCPU::advancePC(Fault fault
)
463 //Since we're moving to a new pc, zero out the offset
465 if (fault
!= NoFault
) {
466 curMacroStaticInst
= StaticInst::nullStaticInstPtr
;
468 thread
->setMicroPC(0);
469 thread
->setNextMicroPC(1);
472 //If we're at the last micro op for this instruction
473 if (curStaticInst
&& curStaticInst
->isLastMicroop()) {
474 //We should be working with a macro op
475 assert(curMacroStaticInst
);
476 //Close out this macro op, and clean up the
478 curMacroStaticInst
= StaticInst::nullStaticInstPtr
;
479 thread
->setMicroPC(0);
480 thread
->setNextMicroPC(1);
482 //If we're still in a macro op
483 if (curMacroStaticInst
) {
484 //Advance the micro pc
485 thread
->setMicroPC(thread
->readNextMicroPC());
486 //Advance the "next" micro pc. Note that there are no delay
487 //slots, and micro ops are "word" addressed.
488 thread
->setNextMicroPC(thread
->readNextMicroPC() + 1);
490 // go to the next instruction
491 thread
->setPC(thread
->readNextPC());
492 thread
->setNextPC(thread
->readNextNPC());
493 thread
->setNextNPC(thread
->readNextNPC() + sizeof(MachInst
));
494 assert(thread
->readNextPC() != thread
->readNextNPC());
500 oldpc
= thread
->readPC();
501 system
->pcEventQueue
.service(tc
);
502 } while (oldpc
!= thread
->readPC());
506 BaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr)
508 // translate to physical address
509 Fault fault = NoFault;
510 int CacheID = Op & 0x3; // Lower 3 bits identify Cache
511 int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation
514 warn("CacheOps not implemented for secondary/tertiary caches\n");
519 { // Fill Packet Type
520 case 0: warn("Invalidate Cache Op\n");
522 case 1: warn("Index Load Tag Cache Op\n");
524 case 2: warn("Index Store Tag Cache Op\n");
526 case 4: warn("Hit Invalidate Cache Op\n");
528 case 5: warn("Fill/Hit Writeback Invalidate Cache Op\n");
530 case 6: warn("Hit Writeback\n");
532 case 7: warn("Fetch & Lock Cache Op\n");
534 default: warn("Unimplemented Cache Op\n");