2 * Copyright (c) 2010-2012, 2015, 2017 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
15 * Copyright (c) 2002-2005 The Regents of The University of Michigan
16 * All rights reserved.
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 * Authors: Steve Reinhardt
44 #include "cpu/simple/base.hh"
46 #include "arch/kernel_stats.hh"
47 #include "arch/stacktrace.hh"
48 #include "arch/tlb.hh"
49 #include "arch/utility.hh"
50 #include "arch/vtophys.hh"
51 #include "base/cp_annotate.hh"
52 #include "base/cprintf.hh"
53 #include "base/inifile.hh"
54 #include "base/loader/symtab.hh"
55 #include "base/misc.hh"
56 #include "base/pollevent.hh"
57 #include "base/trace.hh"
58 #include "base/types.hh"
59 #include "config/the_isa.hh"
60 #include "cpu/base.hh"
61 #include "cpu/checker/cpu.hh"
62 #include "cpu/checker/thread_context.hh"
63 #include "cpu/exetrace.hh"
64 #include "cpu/pred/bpred_unit.hh"
65 #include "cpu/profile.hh"
66 #include "cpu/simple/exec_context.hh"
67 #include "cpu/simple_thread.hh"
69 #include "cpu/static_inst.hh"
70 #include "cpu/thread_context.hh"
71 #include "debug/Decode.hh"
72 #include "debug/Fetch.hh"
73 #include "debug/Quiesce.hh"
74 #include "mem/mem_object.hh"
75 #include "mem/packet.hh"
76 #include "mem/request.hh"
77 #include "params/BaseSimpleCPU.hh"
78 #include "sim/byteswap.hh"
79 #include "sim/debug.hh"
80 #include "sim/faults.hh"
81 #include "sim/full_system.hh"
82 #include "sim/sim_events.hh"
83 #include "sim/sim_object.hh"
84 #include "sim/stats.hh"
85 #include "sim/system.hh"
88 using namespace TheISA
;
90 BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams
*p
)
93 branchPred(p
->branchPred
),
100 for (unsigned i
= 0; i
< numThreads
; i
++) {
102 thread
= new SimpleThread(this, i
, p
->system
,
103 p
->itb
, p
->dtb
, p
->isa
[i
]);
105 thread
= new SimpleThread(this, i
, p
->system
, p
->workload
[i
],
106 p
->itb
, p
->dtb
, p
->isa
[i
]);
108 threadInfo
.push_back(new SimpleExecContext(this, thread
));
109 ThreadContext
*tc
= thread
->getTC();
110 threadContexts
.push_back(tc
);
115 fatal("Checker currently does not support SMT");
117 BaseCPU
*temp_checker
= p
->checker
;
118 checker
= dynamic_cast<CheckerCPU
*>(temp_checker
);
119 checker
->setSystem(p
->system
);
120 // Manipulate thread context
121 ThreadContext
*cpu_tc
= threadContexts
[0];
122 threadContexts
[0] = new CheckerThreadContext
<ThreadContext
>(cpu_tc
, this->checker
);
129 BaseSimpleCPU::init()
133 for (auto tc
: threadContexts
) {
134 // Initialise the ThreadContext's memory proxies
135 tc
->initMemProxies(tc
);
137 if (FullSystem
&& !params()->switched_out
) {
138 // initialize CPU, including PC
139 TheISA::initCPU(tc
, tc
->contextId());
145 BaseSimpleCPU::checkPcEventQueue()
147 Addr oldpc
, pc
= threadInfo
[curThread
]->thread
->instAddr();
150 system
->pcEventQueue
.service(threadContexts
[curThread
]);
151 pc
= threadInfo
[curThread
]->thread
->instAddr();
152 } while (oldpc
!= pc
);
156 BaseSimpleCPU::swapActiveThread()
158 if (numThreads
> 1) {
159 if ((!curStaticInst
|| !curStaticInst
->isDelayedCommit()) &&
160 !threadInfo
[curThread
]->stayAtPC
) {
161 // Swap active threads
162 if (!activeThreads
.empty()) {
163 curThread
= activeThreads
.front();
164 activeThreads
.pop_front();
165 activeThreads
.push_back(curThread
);
172 BaseSimpleCPU::countInst()
174 SimpleExecContext
& t_info
= *threadInfo
[curThread
];
176 if (!curStaticInst
->isMicroop() || curStaticInst
->isLastMicroop()) {
183 system
->totalNumInsts
++;
184 t_info
.thread
->funcExeInst
++;
188 BaseSimpleCPU::totalInsts() const
190 Counter total_inst
= 0;
191 for (auto& t_info
: threadInfo
) {
192 total_inst
+= t_info
->numInst
;
199 BaseSimpleCPU::totalOps() const
201 Counter total_op
= 0;
202 for (auto& t_info
: threadInfo
) {
203 total_op
+= t_info
->numOp
;
209 BaseSimpleCPU::~BaseSimpleCPU()
214 BaseSimpleCPU::haltContext(ThreadID thread_num
)
216 // for now, these are equivalent
217 suspendContext(thread_num
);
218 updateCycleCounters(BaseCPU::CPU_STATE_SLEEP
);
223 BaseSimpleCPU::regStats()
225 using namespace Stats
;
229 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
230 SimpleExecContext
& t_info
= *threadInfo
[tid
];
232 std::string thread_str
= name();
234 thread_str
+= ".thread" + std::to_string(tid
);
237 .name(thread_str
+ ".committedInsts")
238 .desc("Number of instructions committed")
242 .name(thread_str
+ ".committedOps")
243 .desc("Number of ops (including micro ops) committed")
246 t_info
.numIntAluAccesses
247 .name(thread_str
+ ".num_int_alu_accesses")
248 .desc("Number of integer alu accesses")
251 t_info
.numFpAluAccesses
252 .name(thread_str
+ ".num_fp_alu_accesses")
253 .desc("Number of float alu accesses")
256 t_info
.numVecAluAccesses
257 .name(thread_str
+ ".num_vec_alu_accesses")
258 .desc("Number of vector alu accesses")
261 t_info
.numCallsReturns
262 .name(thread_str
+ ".num_func_calls")
263 .desc("number of times a function call or return occured")
266 t_info
.numCondCtrlInsts
267 .name(thread_str
+ ".num_conditional_control_insts")
268 .desc("number of instructions that are conditional controls")
272 .name(thread_str
+ ".num_int_insts")
273 .desc("number of integer instructions")
277 .name(thread_str
+ ".num_fp_insts")
278 .desc("number of float instructions")
282 .name(thread_str
+ ".num_vec_insts")
283 .desc("number of vector instructions")
286 t_info
.numIntRegReads
287 .name(thread_str
+ ".num_int_register_reads")
288 .desc("number of times the integer registers were read")
291 t_info
.numIntRegWrites
292 .name(thread_str
+ ".num_int_register_writes")
293 .desc("number of times the integer registers were written")
297 .name(thread_str
+ ".num_fp_register_reads")
298 .desc("number of times the floating registers were read")
301 t_info
.numFpRegWrites
302 .name(thread_str
+ ".num_fp_register_writes")
303 .desc("number of times the floating registers were written")
306 t_info
.numVecRegReads
307 .name(thread_str
+ ".num_vec_register_reads")
308 .desc("number of times the vector registers were read")
311 t_info
.numVecRegWrites
312 .name(thread_str
+ ".num_vec_register_writes")
313 .desc("number of times the vector registers were written")
317 .name(thread_str
+ ".num_cc_register_reads")
318 .desc("number of times the CC registers were read")
322 t_info
.numCCRegWrites
323 .name(thread_str
+ ".num_cc_register_writes")
324 .desc("number of times the CC registers were written")
329 .name(thread_str
+ ".num_mem_refs")
330 .desc("number of memory refs")
334 .name(thread_str
+ ".num_store_insts")
335 .desc("Number of store instructions")
339 .name(thread_str
+ ".num_load_insts")
340 .desc("Number of load instructions")
343 t_info
.notIdleFraction
344 .name(thread_str
+ ".not_idle_fraction")
345 .desc("Percentage of non-idle cycles")
349 .name(thread_str
+ ".idle_fraction")
350 .desc("Percentage of idle cycles")
354 .name(thread_str
+ ".num_busy_cycles")
355 .desc("Number of busy cycles")
359 .name(thread_str
+ ".num_idle_cycles")
360 .desc("Number of idle cycles")
363 t_info
.icacheStallCycles
364 .name(thread_str
+ ".icache_stall_cycles")
365 .desc("ICache total stall cycles")
366 .prereq(t_info
.icacheStallCycles
)
369 t_info
.dcacheStallCycles
370 .name(thread_str
+ ".dcache_stall_cycles")
371 .desc("DCache total stall cycles")
372 .prereq(t_info
.dcacheStallCycles
)
375 t_info
.statExecutedInstType
376 .init(Enums::Num_OpClass
)
377 .name(thread_str
+ ".op_class")
378 .desc("Class of executed instruction")
379 .flags(total
| pdf
| dist
)
382 for (unsigned i
= 0; i
< Num_OpClasses
; ++i
) {
383 t_info
.statExecutedInstType
.subname(i
, Enums::OpClassStrings
[i
]);
386 t_info
.idleFraction
= constant(1.0) - t_info
.notIdleFraction
;
387 t_info
.numIdleCycles
= t_info
.idleFraction
* numCycles
;
388 t_info
.numBusyCycles
= t_info
.notIdleFraction
* numCycles
;
391 .name(thread_str
+ ".Branches")
392 .desc("Number of branches fetched")
393 .prereq(t_info
.numBranches
);
395 t_info
.numPredictedBranches
396 .name(thread_str
+ ".predictedBranches")
397 .desc("Number of branches predicted as taken")
398 .prereq(t_info
.numPredictedBranches
);
400 t_info
.numBranchMispred
401 .name(thread_str
+ ".BranchMispred")
402 .desc("Number of branch mispredictions")
403 .prereq(t_info
.numBranchMispred
);
408 BaseSimpleCPU::resetStats()
410 for (auto &thread_info
: threadInfo
) {
411 thread_info
->notIdleFraction
= (_status
!= Idle
);
416 BaseSimpleCPU::serializeThread(CheckpointOut
&cp
, ThreadID tid
) const
418 assert(_status
== Idle
|| _status
== Running
);
420 threadInfo
[tid
]->thread
->serialize(cp
);
424 BaseSimpleCPU::unserializeThread(CheckpointIn
&cp
, ThreadID tid
)
426 threadInfo
[tid
]->thread
->unserialize(cp
);
430 change_thread_state(ThreadID tid
, int activate
, int priority
)
435 BaseSimpleCPU::dbg_vtophys(Addr addr
)
437 return vtophys(threadContexts
[curThread
], addr
);
441 BaseSimpleCPU::wakeup(ThreadID tid
)
443 getCpuAddrMonitor(tid
)->gotWakeup
= true;
445 if (threadInfo
[tid
]->thread
->status() == ThreadContext::Suspended
) {
446 DPRINTF(Quiesce
,"[tid:%d] Suspended Processor awoke\n", tid
);
447 threadInfo
[tid
]->thread
->activate();
452 BaseSimpleCPU::checkForInterrupts()
454 SimpleExecContext
&t_info
= *threadInfo
[curThread
];
455 SimpleThread
* thread
= t_info
.thread
;
456 ThreadContext
* tc
= thread
->getTC();
458 if (checkInterrupts(tc
)) {
459 Fault interrupt
= interrupts
[curThread
]->getInterrupt(tc
);
461 if (interrupt
!= NoFault
) {
462 t_info
.fetchOffset
= 0;
463 interrupts
[curThread
]->updateIntrInfo(tc
);
464 interrupt
->invoke(tc
);
465 thread
->decoder
.reset();
472 BaseSimpleCPU::setupFetchRequest(Request
*req
)
474 SimpleExecContext
&t_info
= *threadInfo
[curThread
];
475 SimpleThread
* thread
= t_info
.thread
;
477 Addr instAddr
= thread
->instAddr();
479 // set up memory request for instruction fetch
480 DPRINTF(Fetch
, "Fetch: PC:%08p\n", instAddr
);
482 Addr fetchPC
= (instAddr
& PCMask
) + t_info
.fetchOffset
;
483 req
->setVirt(0, fetchPC
, sizeof(MachInst
), Request::INST_FETCH
, instMasterId(),
489 BaseSimpleCPU::preExecute()
491 SimpleExecContext
&t_info
= *threadInfo
[curThread
];
492 SimpleThread
* thread
= t_info
.thread
;
494 // maintain $r0 semantics
495 thread
->setIntReg(ZeroReg
, 0);
496 #if THE_ISA == ALPHA_ISA
497 thread
->setFloatReg(ZeroReg
, 0.0);
500 // check for instruction-count-based events
501 comInstEventQueue
[curThread
]->serviceEvents(t_info
.numInst
);
502 system
->instEventQueue
.serviceEvents(system
->totalNumInsts
);
504 // decode the instruction
507 TheISA::PCState pcState
= thread
->pcState();
509 if (isRomMicroPC(pcState
.microPC())) {
510 t_info
.stayAtPC
= false;
511 curStaticInst
= microcodeRom
.fetchMicroop(pcState
.microPC(),
513 } else if (!curMacroStaticInst
) {
514 //We're not in the middle of a macro instruction
515 StaticInstPtr instPtr
= NULL
;
517 TheISA::Decoder
*decoder
= &(thread
->decoder
);
519 //Predecode, ie bundle up an ExtMachInst
520 //If more fetch data is needed, pass it in.
521 Addr fetchPC
= (pcState
.instAddr() & PCMask
) + t_info
.fetchOffset
;
522 //if (decoder->needMoreBytes())
523 decoder
->moreBytes(pcState
, fetchPC
, inst
);
525 // decoder->process();
527 //Decode an instruction if one is ready. Otherwise, we'll have to
528 //fetch beyond the MachInst at the current pc.
529 instPtr
= decoder
->decode(pcState
);
531 t_info
.stayAtPC
= false;
532 thread
->pcState(pcState
);
534 t_info
.stayAtPC
= true;
535 t_info
.fetchOffset
+= sizeof(MachInst
);
538 //If we decoded an instruction and it's microcoded, start pulling
540 if (instPtr
&& instPtr
->isMacroop()) {
541 curMacroStaticInst
= instPtr
;
543 curMacroStaticInst
->fetchMicroop(pcState
.microPC());
545 curStaticInst
= instPtr
;
548 //Read the next micro op from the macro op
549 curStaticInst
= curMacroStaticInst
->fetchMicroop(pcState
.microPC());
552 //If we decoded an instruction this "tick", record information about it.
555 traceData
= tracer
->getInstRecord(curTick(), thread
->getTC(),
556 curStaticInst
, thread
->pcState(), curMacroStaticInst
);
558 DPRINTF(Decode
,"Decode: Decoded %s instruction: %#x\n",
559 curStaticInst
->getName(), curStaticInst
->machInst
);
563 if (branchPred
&& curStaticInst
&&
564 curStaticInst
->isControl()) {
565 // Use a fake sequence number since we only have one
566 // instruction in flight at the same time.
567 const InstSeqNum
cur_sn(0);
568 t_info
.predPC
= thread
->pcState();
569 const bool predict_taken(
570 branchPred
->predict(curStaticInst
, cur_sn
, t_info
.predPC
,
574 ++t_info
.numPredictedBranches
;
579 BaseSimpleCPU::postExecute()
581 SimpleExecContext
&t_info
= *threadInfo
[curThread
];
582 SimpleThread
* thread
= t_info
.thread
;
584 assert(curStaticInst
);
586 TheISA::PCState pc
= threadContexts
[curThread
]->pcState();
587 Addr instAddr
= pc
.instAddr();
588 if (FullSystem
&& thread
->profile
) {
589 bool usermode
= TheISA::inUserMode(threadContexts
[curThread
]);
590 thread
->profilePC
= usermode
? 1 : instAddr
;
591 ProfileNode
*node
= thread
->profile
->consume(threadContexts
[curThread
],
594 thread
->profileNode
= node
;
597 if (curStaticInst
->isMemRef()) {
601 if (curStaticInst
->isLoad()) {
603 comLoadEventQueue
[curThread
]->serviceEvents(t_info
.numLoad
);
606 if (CPA::available()) {
607 CPA::cpa()->swAutoBegin(threadContexts
[curThread
], pc
.nextInstAddr());
610 if (curStaticInst
->isControl()) {
611 ++t_info
.numBranches
;
614 /* Power model statistics */
615 //integer alu accesses
616 if (curStaticInst
->isInteger()){
617 t_info
.numIntAluAccesses
++;
618 t_info
.numIntInsts
++;
622 if (curStaticInst
->isFloating()){
623 t_info
.numFpAluAccesses
++;
627 //vector alu accesses
628 if (curStaticInst
->isVector()){
629 t_info
.numVecAluAccesses
++;
630 t_info
.numVecInsts
++;
633 //number of function calls/returns to get window accesses
634 if (curStaticInst
->isCall() || curStaticInst
->isReturn()){
635 t_info
.numCallsReturns
++;
638 //the number of branch predictions that will be made
639 if (curStaticInst
->isCondCtrl()){
640 t_info
.numCondCtrlInsts
++;
644 if (curStaticInst
->isLoad()){
645 t_info
.numLoadInsts
++;
648 if (curStaticInst
->isStore()){
649 t_info
.numStoreInsts
++;
651 /* End power model statistics */
653 t_info
.statExecutedInstType
[curStaticInst
->opClass()]++;
656 traceFunctions(instAddr
);
664 // Call CPU instruction commit probes
665 probeInstCommit(curStaticInst
);
669 BaseSimpleCPU::advancePC(const Fault
&fault
)
671 SimpleExecContext
&t_info
= *threadInfo
[curThread
];
672 SimpleThread
* thread
= t_info
.thread
;
674 const bool branching(thread
->pcState().branching());
676 //Since we're moving to a new pc, zero out the offset
677 t_info
.fetchOffset
= 0;
678 if (fault
!= NoFault
) {
679 curMacroStaticInst
= StaticInst::nullStaticInstPtr
;
680 fault
->invoke(threadContexts
[curThread
], curStaticInst
);
681 thread
->decoder
.reset();
684 if (curStaticInst
->isLastMicroop())
685 curMacroStaticInst
= StaticInst::nullStaticInstPtr
;
686 TheISA::PCState pcState
= thread
->pcState();
687 TheISA::advancePC(pcState
, curStaticInst
);
688 thread
->pcState(pcState
);
692 if (branchPred
&& curStaticInst
&& curStaticInst
->isControl()) {
693 // Use a fake sequence number since we only have one
694 // instruction in flight at the same time.
695 const InstSeqNum
cur_sn(0);
697 if (t_info
.predPC
== thread
->pcState()) {
698 // Correctly predicted branch
699 branchPred
->update(cur_sn
, curThread
);
701 // Mis-predicted branch
702 branchPred
->squash(cur_sn
, thread
->pcState(), branching
, curThread
);
703 ++t_info
.numBranchMispred
;
709 BaseSimpleCPU::startup()
712 for (auto& t_info
: threadInfo
)
713 t_info
->thread
->startup();