src/cpu/simple/base.cc

   1 /*
   2  * Copyright (c) 2010 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Steve Reinhardt
  41  */
  42
  43 #include "arch/faults.hh"
  44 #include "arch/utility.hh"
  45 #include "base/cp_annotate.hh"
  46 #include "base/cprintf.hh"
  47 #include "base/inifile.hh"
  48 #include "base/loader/symtab.hh"
  49 #include "base/misc.hh"
  50 #include "base/pollevent.hh"
  51 #include "base/range.hh"
  52 #include "base/trace.hh"
  53 #include "base/types.hh"
  54 #include "config/the_isa.hh"
  55 #include "cpu/base.hh"
  56 #include "cpu/exetrace.hh"
  57 #include "cpu/profile.hh"
  58 #include "cpu/simple/base.hh"
  59 #include "cpu/simple_thread.hh"
  60 #include "cpu/smt.hh"
  61 #include "cpu/static_inst.hh"
  62 #include "cpu/thread_context.hh"
  63 #include "mem/packet.hh"
  64 #include "mem/request.hh"
  65 #include "params/BaseSimpleCPU.hh"
  66 #include "sim/byteswap.hh"
  67 #include "sim/debug.hh"
  68 #include "sim/sim_events.hh"
  69 #include "sim/sim_object.hh"
  70 #include "sim/stats.hh"
  71 #include "sim/system.hh"
  72
  73 #if FULL_SYSTEM
  74 #include "arch/kernel_stats.hh"
  75 #include "arch/stacktrace.hh"
  76 #include "arch/tlb.hh"
  77 #include "arch/vtophys.hh"
  78 #else // !FULL_SYSTEM
  79 #include "mem/mem_object.hh"
  80 #endif // FULL_SYSTEM
  81
  82 using namespace std;
  83 using namespace TheISA;
  84
  85 BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
  86     : BaseCPU(p), traceData(NULL), thread(NULL), predecoder(NULL)
  87 {
  88 #if FULL_SYSTEM
  89     thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
  90 #else
  91     thread = new SimpleThread(this, /* thread_num */ 0, p->workload[0],
  92             p->itb, p->dtb);
  93 #endif // !FULL_SYSTEM
  94
  95     thread->setStatus(ThreadContext::Halted);
  96
  97     tc = thread->getTC();
  98
  99     numInst = 0;
 100     startNumInst = 0;
 101     numLoad = 0;
 102     startNumLoad = 0;
 103     lastIcacheStall = 0;
 104     lastDcacheStall = 0;
 105
 106     threadContexts.push_back(tc);
 107
 108
 109     fetchOffset = 0;
 110     stayAtPC = false;
 111 }
 112
 113 BaseSimpleCPU::~BaseSimpleCPU()
 114 {
 115 }
 116
 117 void
 118 BaseSimpleCPU::deallocateContext(int thread_num)
 119 {
 120     // for now, these are equivalent
 121     suspendContext(thread_num);
 122 }
 123
 124
 125 void
 126 BaseSimpleCPU::haltContext(int thread_num)
 127 {
 128     // for now, these are equivalent
 129     suspendContext(thread_num);
 130 }
 131
 132
 133 void
 134 BaseSimpleCPU::regStats()
 135 {
 136     using namespace Stats;
 137
 138     BaseCPU::regStats();
 139
 140     numInsts
 141         .name(name() + ".num_insts")
 142         .desc("Number of instructions executed")
 143         ;
 144
 145     numMemRefs
 146         .name(name() + ".num_refs")
 147         .desc("Number of memory references")
 148         ;
 149
 150     notIdleFraction
 151         .name(name() + ".not_idle_fraction")
 152         .desc("Percentage of non-idle cycles")
 153         ;
 154
 155     idleFraction
 156         .name(name() + ".idle_fraction")
 157         .desc("Percentage of idle cycles")
 158         ;
 159
 160     icacheStallCycles
 161         .name(name() + ".icache_stall_cycles")
 162         .desc("ICache total stall cycles")
 163         .prereq(icacheStallCycles)
 164         ;
 165
 166     dcacheStallCycles
 167         .name(name() + ".dcache_stall_cycles")
 168         .desc("DCache total stall cycles")
 169         .prereq(dcacheStallCycles)
 170         ;
 171
 172     icacheRetryCycles
 173         .name(name() + ".icache_retry_cycles")
 174         .desc("ICache total retry cycles")
 175         .prereq(icacheRetryCycles)
 176         ;
 177
 178     dcacheRetryCycles
 179         .name(name() + ".dcache_retry_cycles")
 180         .desc("DCache total retry cycles")
 181         .prereq(dcacheRetryCycles)
 182         ;
 183
 184     idleFraction = constant(1.0) - notIdleFraction;
 185 }
 186
 187 void
 188 BaseSimpleCPU::resetStats()
 189 {
 190 //    startNumInst = numInst;
 191      notIdleFraction = (_status != Idle);
 192 }
 193
 194 void
 195 BaseSimpleCPU::serialize(ostream &os)
 196 {
 197     SERIALIZE_ENUM(_status);
 198     BaseCPU::serialize(os);
 199 //    SERIALIZE_SCALAR(inst);
 200     nameOut(os, csprintf("%s.xc.0", name()));
 201     thread->serialize(os);
 202 }
 203
 204 void
 205 BaseSimpleCPU::unserialize(Checkpoint *cp, const string &section)
 206 {
 207     UNSERIALIZE_ENUM(_status);
 208     BaseCPU::unserialize(cp, section);
 209 //    UNSERIALIZE_SCALAR(inst);
 210     thread->unserialize(cp, csprintf("%s.xc.0", section));
 211 }
 212
 213 void
 214 change_thread_state(ThreadID tid, int activate, int priority)
 215 {
 216 }
 217
 218 void
 219 BaseSimpleCPU::prefetch(Addr addr, unsigned flags)
 220 {
 221     if (traceData) {
 222         traceData->setAddr(addr);
 223     }
 224
 225     // need to do this...
 226 }
 227
 228 void
 229 BaseSimpleCPU::writeHint(Addr addr, int size, unsigned flags)
 230 {
 231     if (traceData) {
 232         traceData->setAddr(addr);
 233     }
 234
 235     // need to do this...
 236 }
 237
 238
 239 Fault
 240 BaseSimpleCPU::copySrcTranslate(Addr src)
 241 {
 242 #if 0
 243     static bool no_warn = true;
 244     unsigned blk_size =
 245         (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
 246     // Only support block sizes of 64 atm.
 247     assert(blk_size == 64);
 248     int offset = src & (blk_size - 1);
 249
 250     // Make sure block doesn't span page
 251     if (no_warn &&
 252         (src & PageMask) != ((src + blk_size) & PageMask) &&
 253         (src >> 40) != 0xfffffc) {
 254         warn("Copied block source spans pages %x.", src);
 255         no_warn = false;
 256     }
 257
 258     memReq->reset(src & ~(blk_size - 1), blk_size);
 259
 260     // translate to physical address
 261     Fault fault = thread->translateDataReadReq(req);
 262
 263     if (fault == NoFault) {
 264         thread->copySrcAddr = src;
 265         thread->copySrcPhysAddr = memReq->paddr + offset;
 266     } else {
 267         assert(!fault->isAlignmentFault());
 268
 269         thread->copySrcAddr = 0;
 270         thread->copySrcPhysAddr = 0;
 271     }
 272     return fault;
 273 #else
 274     return NoFault;
 275 #endif
 276 }
 277
 278 Fault
 279 BaseSimpleCPU::copy(Addr dest)
 280 {
 281 #if 0
 282     static bool no_warn = true;
 283     unsigned blk_size =
 284         (dcacheInterface) ? dcacheInterface->getBlockSize() : 64;
 285     // Only support block sizes of 64 atm.
 286     assert(blk_size == 64);
 287     uint8_t data[blk_size];
 288     //assert(thread->copySrcAddr);
 289     int offset = dest & (blk_size - 1);
 290
 291     // Make sure block doesn't span page
 292     if (no_warn &&
 293         (dest & PageMask) != ((dest + blk_size) & PageMask) &&
 294         (dest >> 40) != 0xfffffc) {
 295         no_warn = false;
 296         warn("Copied block destination spans pages %x. ", dest);
 297     }
 298
 299     memReq->reset(dest & ~(blk_size -1), blk_size);
 300     // translate to physical address
 301     Fault fault = thread->translateDataWriteReq(req);
 302
 303     if (fault == NoFault) {
 304         Addr dest_addr = memReq->paddr + offset;
 305         // Need to read straight from memory since we have more than 8 bytes.
 306         memReq->paddr = thread->copySrcPhysAddr;
 307         thread->mem->read(memReq, data);
 308         memReq->paddr = dest_addr;
 309         thread->mem->write(memReq, data);
 310         if (dcacheInterface) {
 311             memReq->cmd = Copy;
 312             memReq->completionEvent = NULL;
 313             memReq->paddr = thread->copySrcPhysAddr;
 314             memReq->dest = dest_addr;
 315             memReq->size = 64;
 316             memReq->time = curTick;
 317             dcacheInterface->access(memReq);
 318         }
 319     }
 320     else
 321         assert(!fault->isAlignmentFault());
 322
 323     return fault;
 324 #else
 325     panic("copy not implemented");
 326     return NoFault;
 327 #endif
 328 }
 329
 330 #if FULL_SYSTEM
 331 Addr
 332 BaseSimpleCPU::dbg_vtophys(Addr addr)
 333 {
 334     return vtophys(tc, addr);
 335 }
 336 #endif // FULL_SYSTEM
 337
 338 #if FULL_SYSTEM
 339 void
 340 BaseSimpleCPU::wakeup()
 341 {
 342     if (thread->status() != ThreadContext::Suspended)
 343         return;
 344
 345     DPRINTF(Quiesce,"Suspended Processor awoke\n");
 346     thread->activate();
 347 }
 348 #endif // FULL_SYSTEM
 349
 350 void
 351 BaseSimpleCPU::checkForInterrupts()
 352 {
 353 #if FULL_SYSTEM
 354     if (checkInterrupts(tc)) {
 355         Fault interrupt = interrupts->getInterrupt(tc);
 356
 357         if (interrupt != NoFault) {
 358             fetchOffset = 0;
 359             interrupts->updateIntrInfo(tc);
 360             interrupt->invoke(tc);
 361             predecoder.reset();
 362         }
 363     }
 364 #endif
 365 }
 366
 367
 368 void
 369 BaseSimpleCPU::setupFetchRequest(Request *req)
 370 {
 371     Addr threadPC = thread->readPC();
 372
 373     // set up memory request for instruction fetch
 374 #if ISA_HAS_DELAY_SLOT
 375     DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",threadPC,
 376             thread->readNextPC(),thread->readNextNPC());
 377 #else
 378     DPRINTF(Fetch,"Fetch: PC:%08p NPC:%08p\n",threadPC,
 379             thread->readNextPC());
 380 #endif
 381
 382     Addr fetchPC = (threadPC & PCMask) + fetchOffset;
 383     req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, threadPC);
 384 }
 385
 386
 387 void
 388 BaseSimpleCPU::preExecute()
 389 {
 390     // maintain $r0 semantics
 391     thread->setIntReg(ZeroReg, 0);
 392 #if THE_ISA == ALPHA_ISA
 393     thread->setFloatReg(ZeroReg, 0.0);
 394 #endif // ALPHA_ISA
 395
 396     // check for instruction-count-based events
 397     comInstEventQueue[0]->serviceEvents(numInst);
 398
 399     // decode the instruction
 400     inst = gtoh(inst);
 401
 402     MicroPC upc = thread->readMicroPC();
 403
 404     if (isRomMicroPC(upc)) {
 405         stayAtPC = false;
 406         curStaticInst = microcodeRom.fetchMicroop(upc, curMacroStaticInst);
 407     } else if (!curMacroStaticInst) {
 408         //We're not in the middle of a macro instruction
 409         StaticInstPtr instPtr = NULL;
 410
 411         //Predecode, ie bundle up an ExtMachInst
 412         //This should go away once the constructor can be set up properly
 413         predecoder.setTC(thread->getTC());
 414         //If more fetch data is needed, pass it in.
 415         Addr fetchPC = (thread->readPC() & PCMask) + fetchOffset;
 416         //if(predecoder.needMoreBytes())
 417             predecoder.moreBytes(thread->readPC(), fetchPC, inst);
 418         //else
 419         //    predecoder.process();
 420
 421         //If an instruction is ready, decode it. Otherwise, we'll have to
 422         //fetch beyond the MachInst at the current pc.
 423         if (predecoder.extMachInstReady()) {
 424 #if THE_ISA == X86_ISA || THE_ISA == ARM_ISA
 425             thread->setNextPC(thread->readPC() + predecoder.getInstSize());
 426 #endif // X86_ISA
 427             stayAtPC = false;
 428             instPtr = StaticInst::decode(predecoder.getExtMachInst(),
 429                                          thread->readPC());
 430         } else {
 431             stayAtPC = true;
 432             fetchOffset += sizeof(MachInst);
 433         }
 434
 435         //If we decoded an instruction and it's microcoded, start pulling
 436         //out micro ops
 437         if (instPtr && instPtr->isMacroop()) {
 438             curMacroStaticInst = instPtr;
 439             curStaticInst = curMacroStaticInst->fetchMicroop(upc);
 440         } else {
 441             curStaticInst = instPtr;
 442         }
 443     } else {
 444         //Read the next micro op from the macro op
 445         curStaticInst = curMacroStaticInst->fetchMicroop(upc);
 446     }
 447
 448     //If we decoded an instruction this "tick", record information about it.
 449     if(curStaticInst)
 450     {
 451 #if TRACING_ON
 452         traceData = tracer->getInstRecord(curTick, tc,
 453                 curStaticInst, thread->readPC(),
 454                 curMacroStaticInst, thread->readMicroPC());
 455
 456         DPRINTF(Decode,"Decode: Decoded %s instruction: 0x%x\n",
 457                 curStaticInst->getName(), curStaticInst->machInst);
 458 #endif // TRACING_ON
 459     }
 460 }
 461
 462 void
 463 BaseSimpleCPU::postExecute()
 464 {
 465 #if FULL_SYSTEM
 466     if (thread->profile && curStaticInst) {
 467         bool usermode = TheISA::inUserMode(tc);
 468         thread->profilePC = usermode ? 1 : thread->readPC();
 469         ProfileNode *node = thread->profile->consume(tc, curStaticInst);
 470         if (node)
 471             thread->profileNode = node;
 472     }
 473 #endif
 474
 475     if (curStaticInst->isMemRef()) {
 476         numMemRefs++;
 477     }
 478
 479     if (curStaticInst->isLoad()) {
 480         ++numLoad;
 481         comLoadEventQueue[0]->serviceEvents(numLoad);
 482     }
 483
 484     if (CPA::available()) {
 485         CPA::cpa()->swAutoBegin(tc, thread->readNextPC());
 486     }
 487
 488     traceFunctions(thread->readPC());
 489
 490     if (traceData) {
 491         traceData->dump();
 492         delete traceData;
 493         traceData = NULL;
 494     }
 495 }
 496
 497
 498 void
 499 BaseSimpleCPU::advancePC(Fault fault)
 500 {
 501     //Since we're moving to a new pc, zero out the offset
 502     fetchOffset = 0;
 503     if (fault != NoFault) {
 504         curMacroStaticInst = StaticInst::nullStaticInstPtr;
 505         fault->invoke(tc, curStaticInst);
 506         predecoder.reset();
 507     } else {
 508         //If we're at the last micro op for this instruction
 509         if (curStaticInst && curStaticInst->isLastMicroop()) {
 510             //We should be working with a macro op or be in the ROM
 511             assert(curMacroStaticInst ||
 512                     isRomMicroPC(thread->readMicroPC()));
 513             //Close out this macro op, and clean up the
 514             //microcode state
 515             curMacroStaticInst = StaticInst::nullStaticInstPtr;
 516             thread->setMicroPC(normalMicroPC(0));
 517             thread->setNextMicroPC(normalMicroPC(1));
 518         }
 519         //If we're still in a macro op
 520         if (curMacroStaticInst || isRomMicroPC(thread->readMicroPC())) {
 521             //Advance the micro pc
 522             thread->setMicroPC(thread->readNextMicroPC());
 523             //Advance the "next" micro pc. Note that there are no delay
 524             //slots, and micro ops are "word" addressed.
 525             thread->setNextMicroPC(thread->readNextMicroPC() + 1);
 526         } else {
 527             // go to the next instruction
 528             thread->setPC(thread->readNextPC());
 529             thread->setNextPC(thread->readNextNPC());
 530             thread->setNextNPC(thread->readNextNPC() + sizeof(MachInst));
 531             assert(thread->readNextPC() != thread->readNextNPC());
 532         }
 533     }
 534 }
 535
 536 /*Fault
 537 BaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr)
 538 {
 539     // translate to physical address
 540     Fault fault = NoFault;
 541     int CacheID = Op & 0x3; // Lower 3 bits identify Cache
 542     int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation
 543     if(CacheID > 1)
 544       {
 545         warn("CacheOps not implemented for secondary/tertiary caches\n");
 546       }
 547     else
 548       {
 549         switch(CacheOP)
 550           { // Fill Packet Type
 551           case 0: warn("Invalidate Cache Op\n");
 552             break;
 553           case 1: warn("Index Load Tag Cache Op\n");
 554             break;
 555           case 2: warn("Index Store Tag Cache Op\n");
 556             break;
 557           case 4: warn("Hit Invalidate Cache Op\n");
 558             break;
 559           case 5: warn("Fill/Hit Writeback Invalidate Cache Op\n");
 560             break;
 561           case 6: warn("Hit Writeback\n");
 562             break;
 563           case 7: warn("Fetch & Lock Cache Op\n");
 564             break;
 565           default: warn("Unimplemented Cache Op\n");
 566           }
 567       }
 568     return fault;
 569 }*/