2 * Copyright (c) 2010 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Steve Reinhardt
43 #include "arch/faults.hh"
44 #include "arch/kernel_stats.hh"
45 #include "arch/stacktrace.hh"
46 #include "arch/tlb.hh"
47 #include "arch/utility.hh"
48 #include "arch/vtophys.hh"
49 #include "base/loader/symtab.hh"
50 #include "base/cp_annotate.hh"
51 #include "base/cprintf.hh"
52 #include "base/inifile.hh"
53 #include "base/misc.hh"
54 #include "base/pollevent.hh"
55 #include "base/range.hh"
56 #include "base/trace.hh"
57 #include "base/types.hh"
58 #include "config/the_isa.hh"
59 #include "cpu/simple/base.hh"
60 #include "cpu/base.hh"
61 #include "cpu/exetrace.hh"
62 #include "cpu/profile.hh"
63 #include "cpu/simple_thread.hh"
65 #include "cpu/static_inst.hh"
66 #include "cpu/thread_context.hh"
67 #include "debug/Decode.hh"
68 #include "debug/Fetch.hh"
69 #include "debug/Quiesce.hh"
70 #include "mem/mem_object.hh"
71 #include "mem/packet.hh"
72 #include "mem/request.hh"
73 #include "params/BaseSimpleCPU.hh"
74 #include "sim/byteswap.hh"
75 #include "sim/debug.hh"
76 #include "sim/sim_events.hh"
77 #include "sim/sim_object.hh"
78 #include "sim/stats.hh"
79 #include "sim/system.hh"
82 using namespace TheISA
;
84 BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams
*p
)
85 : BaseCPU(p
), traceData(NULL
), thread(NULL
), predecoder(NULL
)
88 thread
= new SimpleThread(this, 0, p
->system
, p
->itb
, p
->dtb
);
90 thread
= new SimpleThread(this, /* thread_num */ 0, p
->workload
[0],
92 #endif // !FULL_SYSTEM
94 thread
->setStatus(ThreadContext::Halted
);
105 threadContexts
.push_back(tc
);
112 BaseSimpleCPU::~BaseSimpleCPU()
117 BaseSimpleCPU::deallocateContext(int thread_num
)
119 // for now, these are equivalent
120 suspendContext(thread_num
);
125 BaseSimpleCPU::haltContext(int thread_num
)
127 // for now, these are equivalent
128 suspendContext(thread_num
);
133 BaseSimpleCPU::regStats()
135 using namespace Stats
;
140 .name(name() + ".num_insts")
141 .desc("Number of instructions executed")
145 .name(name() + ".num_int_alu_accesses")
146 .desc("Number of integer alu accesses")
150 .name(name() + ".num_fp_alu_accesses")
151 .desc("Number of float alu accesses")
155 .name(name() + ".num_func_calls")
156 .desc("number of times a function call or return occured")
160 .name(name() + ".num_conditional_control_insts")
161 .desc("number of instructions that are conditional controls")
165 .name(name() + ".num_int_insts")
166 .desc("number of integer instructions")
170 .name(name() + ".num_fp_insts")
171 .desc("number of float instructions")
175 .name(name() + ".num_int_register_reads")
176 .desc("number of times the integer registers were read")
180 .name(name() + ".num_int_register_writes")
181 .desc("number of times the integer registers were written")
185 .name(name() + ".num_fp_register_reads")
186 .desc("number of times the floating registers were read")
190 .name(name() + ".num_fp_register_writes")
191 .desc("number of times the floating registers were written")
195 .name(name()+".num_mem_refs")
196 .desc("number of memory refs")
200 .name(name() + ".num_store_insts")
201 .desc("Number of store instructions")
205 .name(name() + ".num_load_insts")
206 .desc("Number of load instructions")
210 .name(name() + ".not_idle_fraction")
211 .desc("Percentage of non-idle cycles")
215 .name(name() + ".idle_fraction")
216 .desc("Percentage of idle cycles")
220 .name(name() + ".num_busy_cycles")
221 .desc("Number of busy cycles")
225 .name(name()+".num_idle_cycles")
226 .desc("Number of idle cycles")
230 .name(name() + ".icache_stall_cycles")
231 .desc("ICache total stall cycles")
232 .prereq(icacheStallCycles
)
236 .name(name() + ".dcache_stall_cycles")
237 .desc("DCache total stall cycles")
238 .prereq(dcacheStallCycles
)
242 .name(name() + ".icache_retry_cycles")
243 .desc("ICache total retry cycles")
244 .prereq(icacheRetryCycles
)
248 .name(name() + ".dcache_retry_cycles")
249 .desc("DCache total retry cycles")
250 .prereq(dcacheRetryCycles
)
253 idleFraction
= constant(1.0) - notIdleFraction
;
254 numIdleCycles
= idleFraction
* numCycles
;
255 numBusyCycles
= (notIdleFraction
)*numCycles
;
259 BaseSimpleCPU::resetStats()
261 // startNumInst = numInst;
262 notIdleFraction
= (_status
!= Idle
);
266 BaseSimpleCPU::serialize(ostream
&os
)
268 SERIALIZE_ENUM(_status
);
269 BaseCPU::serialize(os
);
270 // SERIALIZE_SCALAR(inst);
271 nameOut(os
, csprintf("%s.xc.0", name()));
272 thread
->serialize(os
);
276 BaseSimpleCPU::unserialize(Checkpoint
*cp
, const string
§ion
)
278 UNSERIALIZE_ENUM(_status
);
279 BaseCPU::unserialize(cp
, section
);
280 // UNSERIALIZE_SCALAR(inst);
281 thread
->unserialize(cp
, csprintf("%s.xc.0", section
));
285 change_thread_state(ThreadID tid
, int activate
, int priority
)
290 BaseSimpleCPU::dbg_vtophys(Addr addr
)
292 return vtophys(tc
, addr
);
296 BaseSimpleCPU::wakeup()
298 if (thread
->status() != ThreadContext::Suspended
)
301 DPRINTF(Quiesce
,"Suspended Processor awoke\n");
306 BaseSimpleCPU::checkForInterrupts()
308 if (checkInterrupts(tc
)) {
309 Fault interrupt
= interrupts
->getInterrupt(tc
);
311 if (interrupt
!= NoFault
) {
313 interrupts
->updateIntrInfo(tc
);
314 interrupt
->invoke(tc
);
322 BaseSimpleCPU::setupFetchRequest(Request
*req
)
324 Addr instAddr
= thread
->instAddr();
326 // set up memory request for instruction fetch
327 DPRINTF(Fetch
, "Fetch: PC:%08p\n", instAddr
);
329 Addr fetchPC
= (instAddr
& PCMask
) + fetchOffset
;
330 req
->setVirt(0, fetchPC
, sizeof(MachInst
), Request::INST_FETCH
, instAddr
);
335 BaseSimpleCPU::preExecute()
337 // maintain $r0 semantics
338 thread
->setIntReg(ZeroReg
, 0);
339 #if THE_ISA == ALPHA_ISA
340 thread
->setFloatReg(ZeroReg
, 0.0);
343 // check for instruction-count-based events
344 comInstEventQueue
[0]->serviceEvents(numInst
);
345 system
->instEventQueue
.serviceEvents(system
->totalNumInsts
);
347 // decode the instruction
350 TheISA::PCState pcState
= thread
->pcState();
352 if (isRomMicroPC(pcState
.microPC())) {
354 curStaticInst
= microcodeRom
.fetchMicroop(pcState
.microPC(),
356 } else if (!curMacroStaticInst
) {
357 //We're not in the middle of a macro instruction
358 StaticInstPtr instPtr
= NULL
;
360 //Predecode, ie bundle up an ExtMachInst
361 //This should go away once the constructor can be set up properly
362 predecoder
.setTC(thread
->getTC());
363 //If more fetch data is needed, pass it in.
364 Addr fetchPC
= (pcState
.instAddr() & PCMask
) + fetchOffset
;
365 //if(predecoder.needMoreBytes())
366 predecoder
.moreBytes(pcState
, fetchPC
, inst
);
368 // predecoder.process();
370 //If an instruction is ready, decode it. Otherwise, we'll have to
371 //fetch beyond the MachInst at the current pc.
372 if (predecoder
.extMachInstReady()) {
374 ExtMachInst machInst
= predecoder
.getExtMachInst(pcState
);
375 thread
->pcState(pcState
);
376 instPtr
= thread
->decoder
.decode(machInst
, pcState
.instAddr());
379 fetchOffset
+= sizeof(MachInst
);
382 //If we decoded an instruction and it's microcoded, start pulling
384 if (instPtr
&& instPtr
->isMacroop()) {
385 curMacroStaticInst
= instPtr
;
386 curStaticInst
= curMacroStaticInst
->fetchMicroop(pcState
.microPC());
388 curStaticInst
= instPtr
;
391 //Read the next micro op from the macro op
392 curStaticInst
= curMacroStaticInst
->fetchMicroop(pcState
.microPC());
395 //If we decoded an instruction this "tick", record information about it.
399 traceData
= tracer
->getInstRecord(curTick(), tc
,
400 curStaticInst
, thread
->pcState(), curMacroStaticInst
);
402 DPRINTF(Decode
,"Decode: Decoded %s instruction: 0x%x\n",
403 curStaticInst
->getName(), curStaticInst
->machInst
);
409 BaseSimpleCPU::postExecute()
411 assert(curStaticInst
);
413 TheISA::PCState pc
= tc
->pcState();
414 Addr instAddr
= pc
.instAddr();
415 if (FullSystem
&& thread
->profile
) {
416 bool usermode
= TheISA::inUserMode(tc
);
417 thread
->profilePC
= usermode
? 1 : instAddr
;
418 ProfileNode
*node
= thread
->profile
->consume(tc
, curStaticInst
);
420 thread
->profileNode
= node
;
423 if (curStaticInst
->isMemRef()) {
427 if (curStaticInst
->isLoad()) {
429 comLoadEventQueue
[0]->serviceEvents(numLoad
);
432 if (CPA::available()) {
433 CPA::cpa()->swAutoBegin(tc
, pc
.nextInstAddr());
436 /* Power model statistics */
437 //integer alu accesses
438 if (curStaticInst
->isInteger()){
444 if (curStaticInst
->isFloating()){
449 //number of function calls/returns to get window accesses
450 if (curStaticInst
->isCall() || curStaticInst
->isReturn()){
454 //the number of branch predictions that will be made
455 if (curStaticInst
->isCondCtrl()){
460 if (curStaticInst
->isLoad()){
464 if (curStaticInst
->isStore()){
467 /* End power model statistics */
470 traceFunctions(instAddr
);
481 BaseSimpleCPU::advancePC(Fault fault
)
483 //Since we're moving to a new pc, zero out the offset
485 if (fault
!= NoFault
) {
486 curMacroStaticInst
= StaticInst::nullStaticInstPtr
;
487 fault
->invoke(tc
, curStaticInst
);
491 if (curStaticInst
->isLastMicroop())
492 curMacroStaticInst
= StaticInst::nullStaticInstPtr
;
493 TheISA::PCState pcState
= thread
->pcState();
494 TheISA::advancePC(pcState
, curStaticInst
);
495 thread
->pcState(pcState
);
501 BaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr)
503 // translate to physical address
504 Fault fault = NoFault;
505 int CacheID = Op & 0x3; // Lower 3 bits identify Cache
506 int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation
509 warn("CacheOps not implemented for secondary/tertiary caches\n");
514 { // Fill Packet Type
515 case 0: warn("Invalidate Cache Op\n");
517 case 1: warn("Index Load Tag Cache Op\n");
519 case 2: warn("Index Store Tag Cache Op\n");
521 case 4: warn("Hit Invalidate Cache Op\n");
523 case 5: warn("Fill/Hit Writeback Invalidate Cache Op\n");
525 case 6: warn("Hit Writeback\n");
527 case 7: warn("Fetch & Lock Cache Op\n");
529 default: warn("Unimplemented Cache Op\n");