2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
31 #include "arch/utility.hh"
32 #include "arch/faults.hh"
33 #include "base/cprintf.hh"
34 #include "base/inifile.hh"
35 #include "base/loader/symtab.hh"
36 #include "base/misc.hh"
37 #include "base/pollevent.hh"
38 #include "base/range.hh"
39 #include "base/stats/events.hh"
40 #include "base/trace.hh"
41 #include "cpu/base.hh"
42 #include "cpu/exetrace.hh"
43 #include "cpu/profile.hh"
44 #include "cpu/simple/base.hh"
45 #include "cpu/simple_thread.hh"
47 #include "cpu/static_inst.hh"
48 #include "cpu/thread_context.hh"
49 #include "mem/packet.hh"
50 #include "sim/byteswap.hh"
51 #include "sim/debug.hh"
52 #include "sim/host.hh"
53 #include "sim/sim_events.hh"
54 #include "sim/sim_object.hh"
55 #include "sim/stats.hh"
56 #include "sim/system.hh"
59 #include "arch/kernel_stats.hh"
60 #include "arch/stacktrace.hh"
61 #include "arch/tlb.hh"
62 #include "arch/vtophys.hh"
63 #include "base/remote_gdb.hh"
65 #include "mem/mem_object.hh"
68 #include "params/BaseSimpleCPU.hh"
71 using namespace TheISA
;
73 BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams
*p
)
74 : BaseCPU(p
), traceData(NULL
), thread(NULL
), predecoder(NULL
)
77 thread
= new SimpleThread(this, 0, p
->system
, p
->itb
, p
->dtb
);
79 thread
= new SimpleThread(this, /* thread_num */ 0, p
->workload
[0],
80 p
->itb
, p
->dtb
, /* asid */ 0);
81 #endif // !FULL_SYSTEM
83 thread
->setStatus(ThreadContext::Unallocated
);
94 threadContexts
.push_back(tc
);
101 BaseSimpleCPU::~BaseSimpleCPU()
106 BaseSimpleCPU::deallocateContext(int thread_num
)
108 // for now, these are equivalent
109 suspendContext(thread_num
);
114 BaseSimpleCPU::haltContext(int thread_num
)
116 // for now, these are equivalent
117 suspendContext(thread_num
);
122 BaseSimpleCPU::regStats()
124 using namespace Stats
;
129 .name(name() + ".num_insts")
130 .desc("Number of instructions executed")
134 .name(name() + ".num_refs")
135 .desc("Number of memory references")
139 .name(name() + ".not_idle_fraction")
140 .desc("Percentage of non-idle cycles")
144 .name(name() + ".idle_fraction")
145 .desc("Percentage of idle cycles")
149 .name(name() + ".icache_stall_cycles")
150 .desc("ICache total stall cycles")
151 .prereq(icacheStallCycles
)
155 .name(name() + ".dcache_stall_cycles")
156 .desc("DCache total stall cycles")
157 .prereq(dcacheStallCycles
)
161 .name(name() + ".icache_retry_cycles")
162 .desc("ICache total retry cycles")
163 .prereq(icacheRetryCycles
)
167 .name(name() + ".dcache_retry_cycles")
168 .desc("DCache total retry cycles")
169 .prereq(dcacheRetryCycles
)
172 idleFraction
= constant(1.0) - notIdleFraction
;
176 BaseSimpleCPU::resetStats()
178 // startNumInst = numInst;
179 notIdleFraction
= (_status
!= Idle
);
183 BaseSimpleCPU::serialize(ostream
&os
)
185 SERIALIZE_ENUM(_status
);
186 BaseCPU::serialize(os
);
187 // SERIALIZE_SCALAR(inst);
188 nameOut(os
, csprintf("%s.xc.0", name()));
189 thread
->serialize(os
);
193 BaseSimpleCPU::unserialize(Checkpoint
*cp
, const string
§ion
)
195 UNSERIALIZE_ENUM(_status
);
196 BaseCPU::unserialize(cp
, section
);
197 // UNSERIALIZE_SCALAR(inst);
198 thread
->unserialize(cp
, csprintf("%s.xc.0", section
));
202 change_thread_state(int thread_number
, int activate
, int priority
)
207 BaseSimpleCPU::copySrcTranslate(Addr src
)
210 static bool no_warn
= true;
211 int blk_size
= (dcacheInterface
) ? dcacheInterface
->getBlockSize() : 64;
212 // Only support block sizes of 64 atm.
213 assert(blk_size
== 64);
214 int offset
= src
& (blk_size
- 1);
216 // Make sure block doesn't span page
218 (src
& PageMask
) != ((src
+ blk_size
) & PageMask
) &&
219 (src
>> 40) != 0xfffffc) {
220 warn("Copied block source spans pages %x.", src
);
224 memReq
->reset(src
& ~(blk_size
- 1), blk_size
);
226 // translate to physical address
227 Fault fault
= thread
->translateDataReadReq(req
);
229 if (fault
== NoFault
) {
230 thread
->copySrcAddr
= src
;
231 thread
->copySrcPhysAddr
= memReq
->paddr
+ offset
;
233 assert(!fault
->isAlignmentFault());
235 thread
->copySrcAddr
= 0;
236 thread
->copySrcPhysAddr
= 0;
245 BaseSimpleCPU::copy(Addr dest
)
248 static bool no_warn
= true;
249 int blk_size
= (dcacheInterface
) ? dcacheInterface
->getBlockSize() : 64;
250 // Only support block sizes of 64 atm.
251 assert(blk_size
== 64);
252 uint8_t data
[blk_size
];
253 //assert(thread->copySrcAddr);
254 int offset
= dest
& (blk_size
- 1);
256 // Make sure block doesn't span page
258 (dest
& PageMask
) != ((dest
+ blk_size
) & PageMask
) &&
259 (dest
>> 40) != 0xfffffc) {
261 warn("Copied block destination spans pages %x. ", dest
);
264 memReq
->reset(dest
& ~(blk_size
-1), blk_size
);
265 // translate to physical address
266 Fault fault
= thread
->translateDataWriteReq(req
);
268 if (fault
== NoFault
) {
269 Addr dest_addr
= memReq
->paddr
+ offset
;
270 // Need to read straight from memory since we have more than 8 bytes.
271 memReq
->paddr
= thread
->copySrcPhysAddr
;
272 thread
->mem
->read(memReq
, data
);
273 memReq
->paddr
= dest_addr
;
274 thread
->mem
->write(memReq
, data
);
275 if (dcacheInterface
) {
277 memReq
->completionEvent
= NULL
;
278 memReq
->paddr
= thread
->copySrcPhysAddr
;
279 memReq
->dest
= dest_addr
;
281 memReq
->time
= curTick
;
282 memReq
->flags
&= ~INST_READ
;
283 dcacheInterface
->access(memReq
);
287 assert(!fault
->isAlignmentFault());
291 panic("copy not implemented");
298 BaseSimpleCPU::dbg_vtophys(Addr addr
)
300 return vtophys(tc
, addr
);
302 #endif // FULL_SYSTEM
306 BaseSimpleCPU::post_interrupt(int int_num
, int index
)
308 BaseCPU::post_interrupt(int_num
, index
);
310 if (thread
->status() == ThreadContext::Suspended
) {
311 DPRINTF(Quiesce
,"Suspended Processor awoke\n");
315 #endif // FULL_SYSTEM
318 BaseSimpleCPU::checkForInterrupts()
321 if (check_interrupts(tc
)) {
322 Fault interrupt
= interrupts
->getInterrupt(tc
);
324 if (interrupt
!= NoFault
) {
325 interrupts
->updateIntrInfo(tc
);
326 interrupt
->invoke(tc
);
334 BaseSimpleCPU::setupFetchRequest(Request
*req
)
336 Addr threadPC
= thread
->readPC();
338 // set up memory request for instruction fetch
339 #if ISA_HAS_DELAY_SLOT
340 DPRINTF(Fetch
,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",threadPC
,
341 thread
->readNextPC(),thread
->readNextNPC());
343 DPRINTF(Fetch
,"Fetch: PC:%08p NPC:%08p\n",threadPC
,
344 thread
->readNextPC());
347 Addr fetchPC
= (threadPC
& PCMask
) + fetchOffset
;
348 req
->setVirt(0, fetchPC
, sizeof(MachInst
), 0, threadPC
);
350 Fault fault
= thread
->translateInstReq(req
);
357 BaseSimpleCPU::preExecute()
359 // maintain $r0 semantics
360 thread
->setIntReg(ZeroReg
, 0);
361 #if THE_ISA == ALPHA_ISA
362 thread
->setFloatReg(ZeroReg
, 0.0);
365 // check for instruction-count-based events
366 comInstEventQueue
[0]->serviceEvents(numInst
);
368 // decode the instruction
371 MicroPC upc
= thread
->readMicroPC();
373 if (isRomMicroPC(upc
)) {
375 curStaticInst
= microcodeRom
.fetchMicroop(upc
, curMacroStaticInst
);
376 } else if (!curMacroStaticInst
) {
377 //We're not in the middle of a macro instruction
378 StaticInstPtr instPtr
= NULL
;
380 //Predecode, ie bundle up an ExtMachInst
381 //This should go away once the constructor can be set up properly
382 predecoder
.setTC(thread
->getTC());
383 //If more fetch data is needed, pass it in.
384 Addr fetchPC
= (thread
->readPC() & PCMask
) + fetchOffset
;
385 //if(predecoder.needMoreBytes())
386 predecoder
.moreBytes(thread
->readPC(), fetchPC
, inst
);
388 // predecoder.process();
390 //If an instruction is ready, decode it. Otherwise, we'll have to
391 //fetch beyond the MachInst at the current pc.
392 if (predecoder
.extMachInstReady()) {
393 #if THE_ISA == X86_ISA
394 thread
->setNextPC(thread
->readPC() + predecoder
.getInstSize());
397 instPtr
= StaticInst::decode(predecoder
.getExtMachInst(),
401 fetchOffset
+= sizeof(MachInst
);
404 //If we decoded an instruction and it's microcoded, start pulling
406 if (instPtr
&& instPtr
->isMacroop()) {
407 curMacroStaticInst
= instPtr
;
408 curStaticInst
= curMacroStaticInst
->fetchMicroop(upc
);
410 curStaticInst
= instPtr
;
413 //Read the next micro op from the macro op
414 curStaticInst
= curMacroStaticInst
->fetchMicroop(upc
);
417 //If we decoded an instruction this "tick", record information about it.
421 traceData
= tracer
->getInstRecord(curTick
, tc
, curStaticInst
,
424 DPRINTF(Decode
,"Decode: Decoded %s instruction: 0x%x\n",
425 curStaticInst
->getName(), curStaticInst
->machInst
);
429 thread
->setInst(inst
);
430 #endif // FULL_SYSTEM
435 BaseSimpleCPU::postExecute()
438 if (thread
->profile
&& curStaticInst
) {
439 bool usermode
= TheISA::inUserMode(tc
);
440 thread
->profilePC
= usermode
? 1 : thread
->readPC();
441 ProfileNode
*node
= thread
->profile
->consume(tc
, curStaticInst
);
443 thread
->profileNode
= node
;
447 if (curStaticInst
->isMemRef()) {
451 if (curStaticInst
->isLoad()) {
453 comLoadEventQueue
[0]->serviceEvents(numLoad
);
456 traceFunctions(thread
->readPC());
467 BaseSimpleCPU::advancePC(Fault fault
)
469 //Since we're moving to a new pc, zero out the offset
471 if (fault
!= NoFault
) {
472 curMacroStaticInst
= StaticInst::nullStaticInstPtr
;
474 thread
->setMicroPC(normalMicroPC(0));
475 thread
->setNextMicroPC(normalMicroPC(1));
478 //If we're at the last micro op for this instruction
479 if (curStaticInst
&& curStaticInst
->isLastMicroop()) {
480 //We should be working with a macro op or be in the ROM
481 assert(curMacroStaticInst
||
482 isRomMicroPC(thread
->readMicroPC()));
483 //Close out this macro op, and clean up the
485 curMacroStaticInst
= StaticInst::nullStaticInstPtr
;
486 thread
->setMicroPC(normalMicroPC(0));
487 thread
->setNextMicroPC(normalMicroPC(1));
489 //If we're still in a macro op
490 if (curMacroStaticInst
|| isRomMicroPC(thread
->readMicroPC())) {
491 //Advance the micro pc
492 thread
->setMicroPC(thread
->readNextMicroPC());
493 //Advance the "next" micro pc. Note that there are no delay
494 //slots, and micro ops are "word" addressed.
495 thread
->setNextMicroPC(thread
->readNextMicroPC() + 1);
497 // go to the next instruction
498 thread
->setPC(thread
->readNextPC());
499 thread
->setNextPC(thread
->readNextNPC());
500 thread
->setNextNPC(thread
->readNextNPC() + sizeof(MachInst
));
501 assert(thread
->readNextPC() != thread
->readNextNPC());
507 BaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr)
509 // translate to physical address
510 Fault fault = NoFault;
511 int CacheID = Op & 0x3; // Lower 3 bits identify Cache
512 int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation
515 warn("CacheOps not implemented for secondary/tertiary caches\n");
520 { // Fill Packet Type
521 case 0: warn("Invalidate Cache Op\n");
523 case 1: warn("Index Load Tag Cache Op\n");
525 case 2: warn("Index Store Tag Cache Op\n");
527 case 4: warn("Hit Invalidate Cache Op\n");
529 case 5: warn("Fill/Hit Writeback Invalidate Cache Op\n");
531 case 6: warn("Hit Writeback\n");
533 case 7: warn("Fetch & Lock Cache Op\n");
535 default: warn("Unimplemented Cache Op\n");