2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
31 #include "arch/faults.hh"
32 #include "arch/utility.hh"
33 #include "base/cp_annotate.hh"
34 #include "base/cprintf.hh"
35 #include "base/inifile.hh"
36 #include "base/loader/symtab.hh"
37 #include "base/misc.hh"
38 #include "base/pollevent.hh"
39 #include "base/range.hh"
40 #include "base/stats/events.hh"
41 #include "base/trace.hh"
42 #include "base/types.hh"
43 #include "config/the_isa.hh"
44 #include "cpu/base.hh"
45 #include "cpu/exetrace.hh"
46 #include "cpu/profile.hh"
47 #include "cpu/simple/base.hh"
48 #include "cpu/simple_thread.hh"
50 #include "cpu/static_inst.hh"
51 #include "cpu/thread_context.hh"
52 #include "mem/packet.hh"
53 #include "mem/request.hh"
54 #include "params/BaseSimpleCPU.hh"
55 #include "sim/byteswap.hh"
56 #include "sim/debug.hh"
57 #include "sim/sim_events.hh"
58 #include "sim/sim_object.hh"
59 #include "sim/stats.hh"
60 #include "sim/system.hh"
63 #include "arch/kernel_stats.hh"
64 #include "arch/stacktrace.hh"
65 #include "arch/tlb.hh"
66 #include "arch/vtophys.hh"
67 #include "base/remote_gdb.hh"
69 #include "mem/mem_object.hh"
73 using namespace TheISA
;
75 BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams
*p
)
76 : BaseCPU(p
), traceData(NULL
), thread(NULL
), predecoder(NULL
)
79 thread
= new SimpleThread(this, 0, p
->system
, p
->itb
, p
->dtb
);
81 thread
= new SimpleThread(this, /* thread_num */ 0, p
->workload
[0],
83 #endif // !FULL_SYSTEM
85 thread
->setStatus(ThreadContext::Halted
);
96 threadContexts
.push_back(tc
);
103 BaseSimpleCPU::~BaseSimpleCPU()
108 BaseSimpleCPU::deallocateContext(int thread_num
)
110 // for now, these are equivalent
111 suspendContext(thread_num
);
116 BaseSimpleCPU::haltContext(int thread_num
)
118 // for now, these are equivalent
119 suspendContext(thread_num
);
124 BaseSimpleCPU::regStats()
126 using namespace Stats
;
131 .name(name() + ".num_insts")
132 .desc("Number of instructions executed")
136 .name(name() + ".num_refs")
137 .desc("Number of memory references")
141 .name(name() + ".not_idle_fraction")
142 .desc("Percentage of non-idle cycles")
146 .name(name() + ".idle_fraction")
147 .desc("Percentage of idle cycles")
151 .name(name() + ".icache_stall_cycles")
152 .desc("ICache total stall cycles")
153 .prereq(icacheStallCycles
)
157 .name(name() + ".dcache_stall_cycles")
158 .desc("DCache total stall cycles")
159 .prereq(dcacheStallCycles
)
163 .name(name() + ".icache_retry_cycles")
164 .desc("ICache total retry cycles")
165 .prereq(icacheRetryCycles
)
169 .name(name() + ".dcache_retry_cycles")
170 .desc("DCache total retry cycles")
171 .prereq(dcacheRetryCycles
)
174 idleFraction
= constant(1.0) - notIdleFraction
;
178 BaseSimpleCPU::resetStats()
180 // startNumInst = numInst;
181 notIdleFraction
= (_status
!= Idle
);
185 BaseSimpleCPU::serialize(ostream
&os
)
187 SERIALIZE_ENUM(_status
);
188 BaseCPU::serialize(os
);
189 // SERIALIZE_SCALAR(inst);
190 nameOut(os
, csprintf("%s.xc.0", name()));
191 thread
->serialize(os
);
195 BaseSimpleCPU::unserialize(Checkpoint
*cp
, const string
§ion
)
197 UNSERIALIZE_ENUM(_status
);
198 BaseCPU::unserialize(cp
, section
);
199 // UNSERIALIZE_SCALAR(inst);
200 thread
->unserialize(cp
, csprintf("%s.xc.0", section
));
204 change_thread_state(ThreadID tid
, int activate
, int priority
)
209 BaseSimpleCPU::copySrcTranslate(Addr src
)
212 static bool no_warn
= true;
214 (dcacheInterface
) ? dcacheInterface
->getBlockSize() : 64;
215 // Only support block sizes of 64 atm.
216 assert(blk_size
== 64);
217 int offset
= src
& (blk_size
- 1);
219 // Make sure block doesn't span page
221 (src
& PageMask
) != ((src
+ blk_size
) & PageMask
) &&
222 (src
>> 40) != 0xfffffc) {
223 warn("Copied block source spans pages %x.", src
);
227 memReq
->reset(src
& ~(blk_size
- 1), blk_size
);
229 // translate to physical address
230 Fault fault
= thread
->translateDataReadReq(req
);
232 if (fault
== NoFault
) {
233 thread
->copySrcAddr
= src
;
234 thread
->copySrcPhysAddr
= memReq
->paddr
+ offset
;
236 assert(!fault
->isAlignmentFault());
238 thread
->copySrcAddr
= 0;
239 thread
->copySrcPhysAddr
= 0;
248 BaseSimpleCPU::copy(Addr dest
)
251 static bool no_warn
= true;
253 (dcacheInterface
) ? dcacheInterface
->getBlockSize() : 64;
254 // Only support block sizes of 64 atm.
255 assert(blk_size
== 64);
256 uint8_t data
[blk_size
];
257 //assert(thread->copySrcAddr);
258 int offset
= dest
& (blk_size
- 1);
260 // Make sure block doesn't span page
262 (dest
& PageMask
) != ((dest
+ blk_size
) & PageMask
) &&
263 (dest
>> 40) != 0xfffffc) {
265 warn("Copied block destination spans pages %x. ", dest
);
268 memReq
->reset(dest
& ~(blk_size
-1), blk_size
);
269 // translate to physical address
270 Fault fault
= thread
->translateDataWriteReq(req
);
272 if (fault
== NoFault
) {
273 Addr dest_addr
= memReq
->paddr
+ offset
;
274 // Need to read straight from memory since we have more than 8 bytes.
275 memReq
->paddr
= thread
->copySrcPhysAddr
;
276 thread
->mem
->read(memReq
, data
);
277 memReq
->paddr
= dest_addr
;
278 thread
->mem
->write(memReq
, data
);
279 if (dcacheInterface
) {
281 memReq
->completionEvent
= NULL
;
282 memReq
->paddr
= thread
->copySrcPhysAddr
;
283 memReq
->dest
= dest_addr
;
285 memReq
->time
= curTick
;
286 dcacheInterface
->access(memReq
);
290 assert(!fault
->isAlignmentFault());
294 panic("copy not implemented");
301 BaseSimpleCPU::dbg_vtophys(Addr addr
)
303 return vtophys(tc
, addr
);
305 #endif // FULL_SYSTEM
309 BaseSimpleCPU::wakeup()
311 if (thread
->status() != ThreadContext::Suspended
)
314 DPRINTF(Quiesce
,"Suspended Processor awoke\n");
317 #endif // FULL_SYSTEM
320 BaseSimpleCPU::checkForInterrupts()
323 if (checkInterrupts(tc
)) {
324 Fault interrupt
= interrupts
->getInterrupt(tc
);
326 if (interrupt
!= NoFault
) {
328 interrupts
->updateIntrInfo(tc
);
329 interrupt
->invoke(tc
);
337 BaseSimpleCPU::setupFetchRequest(Request
*req
)
339 Addr threadPC
= thread
->readPC();
341 // set up memory request for instruction fetch
342 #if ISA_HAS_DELAY_SLOT
343 DPRINTF(Fetch
,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",threadPC
,
344 thread
->readNextPC(),thread
->readNextNPC());
346 DPRINTF(Fetch
,"Fetch: PC:%08p NPC:%08p\n",threadPC
,
347 thread
->readNextPC());
350 Addr fetchPC
= (threadPC
& PCMask
) + fetchOffset
;
351 req
->setVirt(0, fetchPC
, sizeof(MachInst
), Request::INST_FETCH
, threadPC
);
356 BaseSimpleCPU::preExecute()
358 // maintain $r0 semantics
359 thread
->setIntReg(ZeroReg
, 0);
360 #if THE_ISA == ALPHA_ISA
361 thread
->setFloatReg(ZeroReg
, 0.0);
364 // check for instruction-count-based events
365 comInstEventQueue
[0]->serviceEvents(numInst
);
367 // decode the instruction
370 MicroPC upc
= thread
->readMicroPC();
372 if (isRomMicroPC(upc
)) {
374 curStaticInst
= microcodeRom
.fetchMicroop(upc
, curMacroStaticInst
);
375 } else if (!curMacroStaticInst
) {
376 //We're not in the middle of a macro instruction
377 StaticInstPtr instPtr
= NULL
;
379 //Predecode, ie bundle up an ExtMachInst
380 //This should go away once the constructor can be set up properly
381 predecoder
.setTC(thread
->getTC());
382 //If more fetch data is needed, pass it in.
383 Addr fetchPC
= (thread
->readPC() & PCMask
) + fetchOffset
;
384 //if(predecoder.needMoreBytes())
385 predecoder
.moreBytes(thread
->readPC(), fetchPC
, inst
);
387 // predecoder.process();
389 //If an instruction is ready, decode it. Otherwise, we'll have to
390 //fetch beyond the MachInst at the current pc.
391 if (predecoder
.extMachInstReady()) {
392 #if THE_ISA == X86_ISA
393 thread
->setNextPC(thread
->readPC() + predecoder
.getInstSize());
396 instPtr
= StaticInst::decode(predecoder
.getExtMachInst(),
400 fetchOffset
+= sizeof(MachInst
);
403 //If we decoded an instruction and it's microcoded, start pulling
405 if (instPtr
&& instPtr
->isMacroop()) {
406 curMacroStaticInst
= instPtr
;
407 curStaticInst
= curMacroStaticInst
->fetchMicroop(upc
);
409 curStaticInst
= instPtr
;
412 //Read the next micro op from the macro op
413 curStaticInst
= curMacroStaticInst
->fetchMicroop(upc
);
416 //If we decoded an instruction this "tick", record information about it.
420 traceData
= tracer
->getInstRecord(curTick
, tc
,
421 curStaticInst
, thread
->readPC(),
422 curMacroStaticInst
, thread
->readMicroPC());
424 DPRINTF(Decode
,"Decode: Decoded %s instruction: 0x%x\n",
425 curStaticInst
->getName(), curStaticInst
->machInst
);
429 thread
->setInst(inst
);
430 #endif // FULL_SYSTEM
435 BaseSimpleCPU::postExecute()
438 if (thread
->profile
&& curStaticInst
) {
439 bool usermode
= TheISA::inUserMode(tc
);
440 thread
->profilePC
= usermode
? 1 : thread
->readPC();
441 ProfileNode
*node
= thread
->profile
->consume(tc
, curStaticInst
);
443 thread
->profileNode
= node
;
447 if (curStaticInst
->isMemRef()) {
451 if (curStaticInst
->isLoad()) {
453 comLoadEventQueue
[0]->serviceEvents(numLoad
);
456 if (CPA::available()) {
457 CPA::cpa()->swAutoBegin(tc
, thread
->readNextPC());
460 traceFunctions(thread
->readPC());
471 BaseSimpleCPU::advancePC(Fault fault
)
473 //Since we're moving to a new pc, zero out the offset
475 if (fault
!= NoFault
) {
476 curMacroStaticInst
= StaticInst::nullStaticInstPtr
;
480 //If we're at the last micro op for this instruction
481 if (curStaticInst
&& curStaticInst
->isLastMicroop()) {
482 //We should be working with a macro op or be in the ROM
483 assert(curMacroStaticInst
||
484 isRomMicroPC(thread
->readMicroPC()));
485 //Close out this macro op, and clean up the
487 curMacroStaticInst
= StaticInst::nullStaticInstPtr
;
488 thread
->setMicroPC(normalMicroPC(0));
489 thread
->setNextMicroPC(normalMicroPC(1));
491 //If we're still in a macro op
492 if (curMacroStaticInst
|| isRomMicroPC(thread
->readMicroPC())) {
493 //Advance the micro pc
494 thread
->setMicroPC(thread
->readNextMicroPC());
495 //Advance the "next" micro pc. Note that there are no delay
496 //slots, and micro ops are "word" addressed.
497 thread
->setNextMicroPC(thread
->readNextMicroPC() + 1);
499 // go to the next instruction
500 thread
->setPC(thread
->readNextPC());
501 thread
->setNextPC(thread
->readNextNPC());
502 thread
->setNextNPC(thread
->readNextNPC() + sizeof(MachInst
));
503 assert(thread
->readNextPC() != thread
->readNextNPC());
509 BaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr)
511 // translate to physical address
512 Fault fault = NoFault;
513 int CacheID = Op & 0x3; // Lower 3 bits identify Cache
514 int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation
517 warn("CacheOps not implemented for secondary/tertiary caches\n");
522 { // Fill Packet Type
523 case 0: warn("Invalidate Cache Op\n");
525 case 1: warn("Index Load Tag Cache Op\n");
527 case 2: warn("Index Store Tag Cache Op\n");
529 case 4: warn("Hit Invalidate Cache Op\n");
531 case 5: warn("Fill/Hit Writeback Invalidate Cache Op\n");
533 case 6: warn("Hit Writeback\n");
535 case 7: warn("Fetch & Lock Cache Op\n");
537 default: warn("Unimplemented Cache Op\n");