2 * Copyright (c) 2010-2011 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Steve Reinhardt
43 #include "arch/kernel_stats.hh"
44 #include "arch/stacktrace.hh"
45 #include "arch/tlb.hh"
46 #include "arch/utility.hh"
47 #include "arch/vtophys.hh"
48 #include "base/loader/symtab.hh"
49 #include "base/cp_annotate.hh"
50 #include "base/cprintf.hh"
51 #include "base/inifile.hh"
52 #include "base/misc.hh"
53 #include "base/pollevent.hh"
54 #include "base/trace.hh"
55 #include "base/types.hh"
56 #include "config/the_isa.hh"
57 #include "cpu/simple/base.hh"
58 #include "cpu/base.hh"
59 #include "cpu/checker/cpu.hh"
60 #include "cpu/checker/thread_context.hh"
61 #include "cpu/exetrace.hh"
62 #include "cpu/profile.hh"
63 #include "cpu/simple_thread.hh"
65 #include "cpu/static_inst.hh"
66 #include "cpu/thread_context.hh"
67 #include "debug/Decode.hh"
68 #include "debug/Fetch.hh"
69 #include "debug/Quiesce.hh"
70 #include "mem/mem_object.hh"
71 #include "mem/packet.hh"
72 #include "mem/request.hh"
73 #include "params/BaseSimpleCPU.hh"
74 #include "sim/byteswap.hh"
75 #include "sim/debug.hh"
76 #include "sim/faults.hh"
77 #include "sim/full_system.hh"
78 #include "sim/sim_events.hh"
79 #include "sim/sim_object.hh"
80 #include "sim/stats.hh"
81 #include "sim/system.hh"
84 using namespace TheISA
;
86 BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams
*p
)
87 : BaseCPU(p
), traceData(NULL
), thread(NULL
)
90 thread
= new SimpleThread(this, 0, p
->system
, p
->itb
, p
->dtb
);
92 thread
= new SimpleThread(this, /* thread_num */ 0, p
->system
,
93 p
->workload
[0], p
->itb
, p
->dtb
);
95 thread
->setStatus(ThreadContext::Halted
);
100 BaseCPU
*temp_checker
= p
->checker
;
101 checker
= dynamic_cast<CheckerCPU
*>(temp_checker
);
102 checker
->setSystem(p
->system
);
103 // Manipulate thread context
104 ThreadContext
*cpu_tc
= tc
;
105 tc
= new CheckerThreadContext
<ThreadContext
>(cpu_tc
, this->checker
);
119 threadContexts
.push_back(tc
);
126 BaseSimpleCPU::~BaseSimpleCPU()
131 BaseSimpleCPU::deallocateContext(ThreadID thread_num
)
133 // for now, these are equivalent
134 suspendContext(thread_num
);
139 BaseSimpleCPU::haltContext(ThreadID thread_num
)
141 // for now, these are equivalent
142 suspendContext(thread_num
);
147 BaseSimpleCPU::regStats()
149 using namespace Stats
;
154 .name(name() + ".committedInsts")
155 .desc("Number of instructions committed")
159 .name(name() + ".committedOps")
160 .desc("Number of ops (including micro ops) committed")
164 .name(name() + ".num_int_alu_accesses")
165 .desc("Number of integer alu accesses")
169 .name(name() + ".num_fp_alu_accesses")
170 .desc("Number of float alu accesses")
174 .name(name() + ".num_func_calls")
175 .desc("number of times a function call or return occured")
179 .name(name() + ".num_conditional_control_insts")
180 .desc("number of instructions that are conditional controls")
184 .name(name() + ".num_int_insts")
185 .desc("number of integer instructions")
189 .name(name() + ".num_fp_insts")
190 .desc("number of float instructions")
194 .name(name() + ".num_int_register_reads")
195 .desc("number of times the integer registers were read")
199 .name(name() + ".num_int_register_writes")
200 .desc("number of times the integer registers were written")
204 .name(name() + ".num_fp_register_reads")
205 .desc("number of times the floating registers were read")
209 .name(name() + ".num_fp_register_writes")
210 .desc("number of times the floating registers were written")
214 .name(name()+".num_mem_refs")
215 .desc("number of memory refs")
219 .name(name() + ".num_store_insts")
220 .desc("Number of store instructions")
224 .name(name() + ".num_load_insts")
225 .desc("Number of load instructions")
229 .name(name() + ".not_idle_fraction")
230 .desc("Percentage of non-idle cycles")
234 .name(name() + ".idle_fraction")
235 .desc("Percentage of idle cycles")
239 .name(name() + ".num_busy_cycles")
240 .desc("Number of busy cycles")
244 .name(name()+".num_idle_cycles")
245 .desc("Number of idle cycles")
249 .name(name() + ".icache_stall_cycles")
250 .desc("ICache total stall cycles")
251 .prereq(icacheStallCycles
)
255 .name(name() + ".dcache_stall_cycles")
256 .desc("DCache total stall cycles")
257 .prereq(dcacheStallCycles
)
261 .name(name() + ".icache_retry_cycles")
262 .desc("ICache total retry cycles")
263 .prereq(icacheRetryCycles
)
267 .name(name() + ".dcache_retry_cycles")
268 .desc("DCache total retry cycles")
269 .prereq(dcacheRetryCycles
)
272 idleFraction
= constant(1.0) - notIdleFraction
;
273 numIdleCycles
= idleFraction
* numCycles
;
274 numBusyCycles
= (notIdleFraction
)*numCycles
;
278 BaseSimpleCPU::resetStats()
280 // startNumInst = numInst;
281 notIdleFraction
= (_status
!= Idle
);
285 BaseSimpleCPU::serialize(ostream
&os
)
287 SERIALIZE_ENUM(_status
);
288 BaseCPU::serialize(os
);
289 // SERIALIZE_SCALAR(inst);
290 nameOut(os
, csprintf("%s.xc.0", name()));
291 thread
->serialize(os
);
295 BaseSimpleCPU::unserialize(Checkpoint
*cp
, const string
§ion
)
297 UNSERIALIZE_ENUM(_status
);
298 BaseCPU::unserialize(cp
, section
);
299 // UNSERIALIZE_SCALAR(inst);
300 thread
->unserialize(cp
, csprintf("%s.xc.0", section
));
304 change_thread_state(ThreadID tid
, int activate
, int priority
)
309 BaseSimpleCPU::dbg_vtophys(Addr addr
)
311 return vtophys(tc
, addr
);
315 BaseSimpleCPU::wakeup()
317 if (thread
->status() != ThreadContext::Suspended
)
320 DPRINTF(Quiesce
,"Suspended Processor awoke\n");
325 BaseSimpleCPU::checkForInterrupts()
327 if (checkInterrupts(tc
)) {
328 Fault interrupt
= interrupts
->getInterrupt(tc
);
330 if (interrupt
!= NoFault
) {
332 interrupts
->updateIntrInfo(tc
);
333 interrupt
->invoke(tc
);
334 thread
->decoder
.reset();
341 BaseSimpleCPU::setupFetchRequest(Request
*req
)
343 Addr instAddr
= thread
->instAddr();
345 // set up memory request for instruction fetch
346 DPRINTF(Fetch
, "Fetch: PC:%08p\n", instAddr
);
348 Addr fetchPC
= (instAddr
& PCMask
) + fetchOffset
;
349 req
->setVirt(0, fetchPC
, sizeof(MachInst
), Request::INST_FETCH
, instMasterId(),
355 BaseSimpleCPU::preExecute()
357 // maintain $r0 semantics
358 thread
->setIntReg(ZeroReg
, 0);
359 #if THE_ISA == ALPHA_ISA
360 thread
->setFloatReg(ZeroReg
, 0.0);
363 // check for instruction-count-based events
364 comInstEventQueue
[0]->serviceEvents(numInst
);
365 system
->instEventQueue
.serviceEvents(system
->totalNumInsts
);
367 // decode the instruction
370 TheISA::PCState pcState
= thread
->pcState();
372 if (isRomMicroPC(pcState
.microPC())) {
374 curStaticInst
= microcodeRom
.fetchMicroop(pcState
.microPC(),
376 } else if (!curMacroStaticInst
) {
377 //We're not in the middle of a macro instruction
378 StaticInstPtr instPtr
= NULL
;
380 TheISA::Decoder
*decoder
= &(thread
->decoder
);
382 //Predecode, ie bundle up an ExtMachInst
383 //This should go away once the constructor can be set up properly
384 decoder
->setTC(thread
->getTC());
385 //If more fetch data is needed, pass it in.
386 Addr fetchPC
= (pcState
.instAddr() & PCMask
) + fetchOffset
;
387 //if(decoder->needMoreBytes())
388 decoder
->moreBytes(pcState
, fetchPC
, inst
);
390 // decoder->process();
392 //Decode an instruction if one is ready. Otherwise, we'll have to
393 //fetch beyond the MachInst at the current pc.
394 instPtr
= decoder
->decode(pcState
);
397 thread
->pcState(pcState
);
400 fetchOffset
+= sizeof(MachInst
);
403 //If we decoded an instruction and it's microcoded, start pulling
405 if (instPtr
&& instPtr
->isMacroop()) {
406 curMacroStaticInst
= instPtr
;
407 curStaticInst
= curMacroStaticInst
->fetchMicroop(pcState
.microPC());
409 curStaticInst
= instPtr
;
412 //Read the next micro op from the macro op
413 curStaticInst
= curMacroStaticInst
->fetchMicroop(pcState
.microPC());
416 //If we decoded an instruction this "tick", record information about it.
419 traceData
= tracer
->getInstRecord(curTick(), tc
,
420 curStaticInst
, thread
->pcState(), curMacroStaticInst
);
422 DPRINTF(Decode
,"Decode: Decoded %s instruction: %#x\n",
423 curStaticInst
->getName(), curStaticInst
->machInst
);
429 BaseSimpleCPU::postExecute()
431 assert(curStaticInst
);
433 TheISA::PCState pc
= tc
->pcState();
434 Addr instAddr
= pc
.instAddr();
435 if (FullSystem
&& thread
->profile
) {
436 bool usermode
= TheISA::inUserMode(tc
);
437 thread
->profilePC
= usermode
? 1 : instAddr
;
438 ProfileNode
*node
= thread
->profile
->consume(tc
, curStaticInst
);
440 thread
->profileNode
= node
;
443 if (curStaticInst
->isMemRef()) {
447 if (curStaticInst
->isLoad()) {
449 comLoadEventQueue
[0]->serviceEvents(numLoad
);
452 if (CPA::available()) {
453 CPA::cpa()->swAutoBegin(tc
, pc
.nextInstAddr());
456 /* Power model statistics */
457 //integer alu accesses
458 if (curStaticInst
->isInteger()){
464 if (curStaticInst
->isFloating()){
469 //number of function calls/returns to get window accesses
470 if (curStaticInst
->isCall() || curStaticInst
->isReturn()){
474 //the number of branch predictions that will be made
475 if (curStaticInst
->isCondCtrl()){
480 if (curStaticInst
->isLoad()){
484 if (curStaticInst
->isStore()){
487 /* End power model statistics */
490 traceFunctions(instAddr
);
501 BaseSimpleCPU::advancePC(Fault fault
)
503 //Since we're moving to a new pc, zero out the offset
505 if (fault
!= NoFault
) {
506 curMacroStaticInst
= StaticInst::nullStaticInstPtr
;
507 fault
->invoke(tc
, curStaticInst
);
508 thread
->decoder
.reset();
511 if (curStaticInst
->isLastMicroop())
512 curMacroStaticInst
= StaticInst::nullStaticInstPtr
;
513 TheISA::PCState pcState
= thread
->pcState();
514 TheISA::advancePC(pcState
, curStaticInst
);
515 thread
->pcState(pcState
);
521 BaseSimpleCPU::CacheOp(uint8_t Op, Addr EffAddr)
523 // translate to physical address
524 Fault fault = NoFault;
525 int CacheID = Op & 0x3; // Lower 3 bits identify Cache
526 int CacheOP = Op >> 2; // Upper 3 bits identify Cache Operation
529 warn("CacheOps not implemented for secondary/tertiary caches\n");
534 { // Fill Packet Type
535 case 0: warn("Invalidate Cache Op\n");
537 case 1: warn("Index Load Tag Cache Op\n");
539 case 2: warn("Index Store Tag Cache Op\n");
541 case 4: warn("Hit Invalidate Cache Op\n");
543 case 5: warn("Fill/Hit Writeback Invalidate Cache Op\n");
545 case 6: warn("Hit Writeback\n");
547 case 7: warn("Fetch & Lock Cache Op\n");
549 default: warn("Unimplemented Cache Op\n");