src/cpu/simple/base.hh

   1 /*
   2  * Copyright (c) 2011-2012,2015 ARM Limited
   3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
   4  * All rights reserved
   5  *
   6  * The license below extends only to copyright in the software and shall
   7  * not be construed as granting a license to any other intellectual
   8  * property including but not limited to intellectual property relating
   9  * to a hardware implementation of the functionality of the software
  10  * licensed hereunder.  You may use the software subject to the license
  11  * terms below provided that you ensure that this notice is replicated
  12  * unmodified and in its entirety in all distributions of the software,
  13  * modified or unmodified, in source code or in binary form.
  14  *
  15  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * Authors: Steve Reinhardt
  42  *          Dave Greene
  43  *          Nathan Binkert
  44  */
  45
  46 #ifndef __CPU_SIMPLE_BASE_HH__
  47 #define __CPU_SIMPLE_BASE_HH__
  48
  49 #include "base/statistics.hh"
  50 #include "config/the_isa.hh"
  51 #include "cpu/base.hh"
  52 #include "cpu/checker/cpu.hh"
  53 #include "cpu/exec_context.hh"
  54 #include "cpu/pc_event.hh"
  55 #include "cpu/simple_thread.hh"
  56 #include "cpu/static_inst.hh"
  57 #include "mem/packet.hh"
  58 #include "mem/port.hh"
  59 #include "mem/request.hh"
  60 #include "sim/eventq.hh"
  61 #include "sim/full_system.hh"
  62 #include "sim/system.hh"
  63
  64 // forward declarations
  65 class Checkpoint;
  66 class Process;
  67 class Processor;
  68 class ThreadContext;
  69
  70 namespace TheISA
  71 {
  72     class DTB;
  73     class ITB;
  74 }
  75
  76 namespace Trace {
  77     class InstRecord;
  78 }
  79
  80 struct BaseSimpleCPUParams;
  81 class BPredUnit;
  82 class SimpleExecContext;
  83
  84 class BaseSimpleCPU : public BaseCPU
  85 {
  86   protected:
  87     ThreadID curThread;
  88     BPredUnit *branchPred;
  89
  90     void checkPcEventQueue();
  91     void swapActiveThread();
  92
  93   public:
  94     BaseSimpleCPU(BaseSimpleCPUParams *params);
  95     virtual ~BaseSimpleCPU();
  96     void wakeup(ThreadID tid) override;
  97     void init() override;
  98   public:
  99     Trace::InstRecord *traceData;
 100     CheckerCPU *checker;
 101
 102     std::vector<SimpleExecContext*> threadInfo;
 103     std::list<ThreadID> activeThreads;
 104
 105     /** Current instruction */
 106     TheISA::MachInst inst;
 107     StaticInstPtr curStaticInst;
 108     StaticInstPtr curMacroStaticInst;
 109
 110   protected:
 111     enum Status {
 112         Idle,
 113         Running,
 114         Faulting,
 115         ITBWaitResponse,
 116         IcacheRetry,
 117         IcacheWaitResponse,
 118         IcacheWaitSwitch,
 119         DTBWaitResponse,
 120         DcacheRetry,
 121         DcacheWaitResponse,
 122         DcacheWaitSwitch,
 123     };
 124
 125     Status _status;
 126
 127   public:
 128     Addr dbg_vtophys(Addr addr);
 129
 130
 131     void checkForInterrupts();
 132     void setupFetchRequest(Request *req);
 133     void preExecute();
 134     void postExecute();
 135     void advancePC(const Fault &fault);
 136
 137     void haltContext(ThreadID thread_num) override;
 138
 139     // statistics
 140     void regStats() override;
 141     void resetStats() override;
 142
 143     void startup() override;
 144
 145     virtual Fault readMem(Addr addr, uint8_t* data, unsigned size,
 146                           unsigned flags) = 0;
 147
 148     virtual Fault writeMem(uint8_t* data, unsigned size, Addr addr,
 149                            unsigned flags, uint64_t* res) = 0;
 150
 151     void countInst();
 152     Counter totalInsts() const override;
 153     Counter totalOps() const override;
 154
 155     void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
 156     void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
 157
 158 };
 159
 160 #endif // __CPU_SIMPLE_BASE_HH__