2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
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8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
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11 * documentation and/or other materials provided with the distribution;
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14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
33 #ifndef __CPU_SIMPLE_BASE_HH__
34 #define __CPU_SIMPLE_BASE_HH__
36 #include "arch/predecoder.hh"
37 #include "base/statistics.hh"
38 #include "config/full_system.hh"
39 #include "config/the_isa.hh"
40 #include "cpu/base.hh"
41 #include "cpu/simple_thread.hh"
42 #include "cpu/pc_event.hh"
43 #include "cpu/static_inst.hh"
44 #include "mem/packet.hh"
45 #include "mem/port.hh"
46 #include "mem/request.hh"
47 #include "sim/eventq.hh"
48 #include "sim/system.hh"
50 // forward declarations
77 class BaseSimpleCPUParams;
80 class BaseSimpleCPU : public BaseCPU
83 typedef TheISA::MiscReg MiscReg;
84 typedef TheISA::FloatReg FloatReg;
85 typedef TheISA::FloatRegBits FloatRegBits;
88 Trace::InstRecord *traceData;
90 inline void checkPcEventQueue() {
93 oldpc = thread->readPC();
94 system->pcEventQueue.service(tc);
95 } while (oldpc != thread->readPC());
101 void zero_fill_64(Addr addr) {
102 static int warned = 0;
104 warn ("WH64 is not implemented");
110 BaseSimpleCPU(BaseSimpleCPUParams *params);
111 virtual ~BaseSimpleCPU();
114 /** SimpleThread object, provides all the architectural state. */
115 SimpleThread *thread;
117 /** ThreadContext object, provides an interface for external
118 * objects to modify this thread's state.
142 Addr dbg_vtophys(Addr addr);
147 // current instruction
148 TheISA::MachInst inst;
151 TheISA::Predecoder predecoder;
153 StaticInstPtr curStaticInst;
154 StaticInstPtr curMacroStaticInst;
156 //This is the offset from the current pc that fetch should be performed at
158 //This flag says to stay at the current pc. This is useful for
159 //instructions which go beyond MachInst boundaries.
162 void checkForInterrupts();
163 void setupFetchRequest(Request *req);
166 void advancePC(Fault fault);
168 virtual void deallocateContext(int thread_num);
169 virtual void haltContext(int thread_num);
172 virtual void regStats();
173 virtual void resetStats();
175 // number of simulated instructions
177 Counter startNumInst;
178 Stats::Scalar numInsts;
185 thread->funcExeInst++;
188 virtual Counter totalInstructions() const
190 return numInst - startNumInst;
193 // Mask to align PCs to MachInst sized boundaries
194 static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
196 // number of simulated memory references
197 Stats::Scalar numMemRefs;
199 // number of simulated loads
201 Counter startNumLoad;
203 // number of idle cycles
204 Stats::Average notIdleFraction;
205 Stats::Formula idleFraction;
207 // number of cycles stalled for I-cache responses
208 Stats::Scalar icacheStallCycles;
209 Counter lastIcacheStall;
211 // number of cycles stalled for I-cache retries
212 Stats::Scalar icacheRetryCycles;
213 Counter lastIcacheRetry;
215 // number of cycles stalled for D-cache responses
216 Stats::Scalar dcacheStallCycles;
217 Counter lastDcacheStall;
219 // number of cycles stalled for D-cache retries
220 Stats::Scalar dcacheRetryCycles;
221 Counter lastDcacheRetry;
223 virtual void serialize(std::ostream &os);
224 virtual void unserialize(Checkpoint *cp, const std::string §ion);
226 // These functions are only used in CPU models that split
227 // effective address computation from the actual memory access.
228 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
229 Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n");
232 void prefetch(Addr addr, unsigned flags);
233 void writeHint(Addr addr, int size, unsigned flags);
235 Fault copySrcTranslate(Addr src);
237 Fault copy(Addr dest);
239 // The register accessor methods provide the index of the
240 // instruction's operand (e.g., 0 or 1), not the architectural
241 // register index, to simplify the implementation of register
242 // renaming. We find the architectural register index by indexing
243 // into the instruction's own operand index table. Note that a
244 // raw pointer to the StaticInst is provided instead of a
245 // ref-counted StaticInstPtr to redice overhead. This is fine as
246 // long as these methods don't copy the pointer into any long-term
247 // storage (which is pretty hard to imagine they would have reason
250 uint64_t readIntRegOperand(const StaticInst *si, int idx)
252 return thread->readIntReg(si->srcRegIdx(idx));
255 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
257 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
258 return thread->readFloatReg(reg_idx);
261 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
263 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
264 return thread->readFloatRegBits(reg_idx);
267 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
269 thread->setIntReg(si->destRegIdx(idx), val);
272 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
274 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
275 thread->setFloatReg(reg_idx, val);
278 void setFloatRegOperandBits(const StaticInst *si, int idx,
281 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
282 thread->setFloatRegBits(reg_idx, val);
285 uint64_t readPC() { return thread->readPC(); }
286 uint64_t readMicroPC() { return thread->readMicroPC(); }
287 uint64_t readNextPC() { return thread->readNextPC(); }
288 uint64_t readNextMicroPC() { return thread->readNextMicroPC(); }
289 uint64_t readNextNPC() { return thread->readNextNPC(); }
291 void setPC(uint64_t val) { thread->setPC(val); }
292 void setMicroPC(uint64_t val) { thread->setMicroPC(val); }
293 void setNextPC(uint64_t val) { thread->setNextPC(val); }
294 void setNextMicroPC(uint64_t val) { thread->setNextMicroPC(val); }
295 void setNextNPC(uint64_t val) { thread->setNextNPC(val); }
297 MiscReg readMiscRegNoEffect(int misc_reg)
299 return thread->readMiscRegNoEffect(misc_reg);
302 MiscReg readMiscReg(int misc_reg)
304 return thread->readMiscReg(misc_reg);
307 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
309 return thread->setMiscRegNoEffect(misc_reg, val);
312 void setMiscReg(int misc_reg, const MiscReg &val)
314 return thread->setMiscReg(misc_reg, val);
317 MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx)
319 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
320 return thread->readMiscRegNoEffect(reg_idx);
323 MiscReg readMiscRegOperand(const StaticInst *si, int idx)
325 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
326 return thread->readMiscReg(reg_idx);
329 void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val)
331 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
332 return thread->setMiscRegNoEffect(reg_idx, val);
335 void setMiscRegOperand(
336 const StaticInst *si, int idx, const MiscReg &val)
338 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
339 return thread->setMiscReg(reg_idx, val);
342 void demapPage(Addr vaddr, uint64_t asn)
344 thread->demapPage(vaddr, asn);
347 void demapInstPage(Addr vaddr, uint64_t asn)
349 thread->demapInstPage(vaddr, asn);
352 void demapDataPage(Addr vaddr, uint64_t asn)
354 thread->demapDataPage(vaddr, asn);
357 unsigned readStCondFailures() {
358 return thread->readStCondFailures();
361 void setStCondFailures(unsigned sc_failures) {
362 thread->setStCondFailures(sc_failures);
365 MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID)
367 panic("Simple CPU models do not support multithreaded "
368 "register access.\n");
371 void setRegOtherThread(int regIdx, const MiscReg &val,
372 ThreadID tid = InvalidThreadID)
374 panic("Simple CPU models do not support multithreaded "
375 "register access.\n");
378 //Fault CacheOp(uint8_t Op, Addr EA);
381 Fault hwrei() { return thread->hwrei(); }
382 void ev5_trap(Fault fault) { fault->invoke(tc); }
383 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
385 void syscall(int64_t callnum) { thread->syscall(callnum); }
388 bool misspeculating() { return thread->misspeculating(); }
389 ThreadContext *tcBase() { return tc; }
392 #endif // __CPU_SIMPLE_BASE_HH__