2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
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11 * documentation and/or other materials provided with the distribution;
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14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
33 #ifndef __CPU_SIMPLE_BASE_HH__
34 #define __CPU_SIMPLE_BASE_HH__
36 #include "arch/predecoder.hh"
37 #include "base/statistics.hh"
38 #include "config/full_system.hh"
39 #include "cpu/base.hh"
40 #include "cpu/simple_thread.hh"
41 #include "cpu/pc_event.hh"
42 #include "cpu/static_inst.hh"
43 #include "mem/packet.hh"
44 #include "mem/port.hh"
45 #include "mem/request.hh"
46 #include "sim/eventq.hh"
48 // forward declarations
79 class BaseSimpleCPU : public BaseCPU
82 typedef TheISA::MiscReg MiscReg;
83 typedef TheISA::FloatReg FloatReg;
84 typedef TheISA::FloatRegBits FloatRegBits;
87 Trace::InstRecord *traceData;
90 void post_interrupt(int int_num, int index);
92 void zero_fill_64(Addr addr) {
93 static int warned = 0;
95 warn ("WH64 is not implemented");
101 struct Params : public BaseCPU::Params
110 BaseSimpleCPU(Params *params);
111 virtual ~BaseSimpleCPU();
114 /** SimpleThread object, provides all the architectural state. */
115 SimpleThread *thread;
117 /** ThreadContext object, provides an interface for external
118 * objects to modify this thread's state.
123 Addr dbg_vtophys(Addr addr);
128 // current instruction
129 TheISA::MachInst inst;
132 TheISA::Predecoder predecoder;
134 // Static data storage
135 TheISA::LargestRead dataReg;
137 StaticInstPtr curStaticInst;
138 StaticInstPtr curMacroStaticInst;
140 //This is the offset from the current pc that fetch should be performed at
142 //This flag says to stay at the current pc. This is useful for
143 //instructions which go beyond MachInst boundaries.
146 void checkForInterrupts();
147 Fault setupFetchRequest(Request *req);
150 void advancePC(Fault fault);
152 virtual void deallocateContext(int thread_num);
153 virtual void haltContext(int thread_num);
156 virtual void regStats();
157 virtual void resetStats();
159 // number of simulated instructions
161 Counter startNumInst;
162 Stats::Scalar<> numInsts;
164 virtual Counter totalInstructions() const
166 return numInst - startNumInst;
169 // Mask to align PCs to MachInst sized boundaries
170 static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
172 // number of simulated memory references
173 Stats::Scalar<> numMemRefs;
175 // number of simulated loads
177 Counter startNumLoad;
179 // number of idle cycles
180 Stats::Average<> notIdleFraction;
181 Stats::Formula idleFraction;
183 // number of cycles stalled for I-cache responses
184 Stats::Scalar<> icacheStallCycles;
185 Counter lastIcacheStall;
187 // number of cycles stalled for I-cache retries
188 Stats::Scalar<> icacheRetryCycles;
189 Counter lastIcacheRetry;
191 // number of cycles stalled for D-cache responses
192 Stats::Scalar<> dcacheStallCycles;
193 Counter lastDcacheStall;
195 // number of cycles stalled for D-cache retries
196 Stats::Scalar<> dcacheRetryCycles;
197 Counter lastDcacheRetry;
199 virtual void serialize(std::ostream &os);
200 virtual void unserialize(Checkpoint *cp, const std::string §ion);
202 // These functions are only used in CPU models that split
203 // effective address computation from the actual memory access.
204 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
205 Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n");
208 void prefetch(Addr addr, unsigned flags)
210 // need to do this...
213 void writeHint(Addr addr, int size, unsigned flags)
215 // need to do this...
219 Fault copySrcTranslate(Addr src);
221 Fault copy(Addr dest);
223 // The register accessor methods provide the index of the
224 // instruction's operand (e.g., 0 or 1), not the architectural
225 // register index, to simplify the implementation of register
226 // renaming. We find the architectural register index by indexing
227 // into the instruction's own operand index table. Note that a
228 // raw pointer to the StaticInst is provided instead of a
229 // ref-counted StaticInstPtr to redice overhead. This is fine as
230 // long as these methods don't copy the pointer into any long-term
231 // storage (which is pretty hard to imagine they would have reason
234 uint64_t readIntRegOperand(const StaticInst *si, int idx)
236 return thread->readIntReg(si->srcRegIdx(idx));
239 FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
241 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
242 return thread->readFloatReg(reg_idx, width);
245 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
247 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
248 return thread->readFloatReg(reg_idx);
251 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
254 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
255 return thread->readFloatRegBits(reg_idx, width);
258 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
260 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
261 return thread->readFloatRegBits(reg_idx);
264 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
266 thread->setIntReg(si->destRegIdx(idx), val);
269 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
272 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
273 thread->setFloatReg(reg_idx, val, width);
276 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
278 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
279 thread->setFloatReg(reg_idx, val);
282 void setFloatRegOperandBits(const StaticInst *si, int idx,
283 FloatRegBits val, int width)
285 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
286 thread->setFloatRegBits(reg_idx, val, width);
289 void setFloatRegOperandBits(const StaticInst *si, int idx,
292 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
293 thread->setFloatRegBits(reg_idx, val);
296 uint64_t readPC() { return thread->readPC(); }
297 uint64_t readNextPC() { return thread->readNextPC(); }
298 uint64_t readNextNPC() { return thread->readNextNPC(); }
300 void setPC(uint64_t val) { thread->setPC(val); }
301 void setNextPC(uint64_t val) { thread->setNextPC(val); }
302 void setNextNPC(uint64_t val) { thread->setNextNPC(val); }
304 MiscReg readMiscRegNoEffect(int misc_reg)
306 return thread->readMiscRegNoEffect(misc_reg);
309 MiscReg readMiscReg(int misc_reg)
311 return thread->readMiscReg(misc_reg);
314 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
316 return thread->setMiscRegNoEffect(misc_reg, val);
319 void setMiscReg(int misc_reg, const MiscReg &val)
321 return thread->setMiscReg(misc_reg, val);
324 MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx)
326 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
327 return thread->readMiscRegNoEffect(reg_idx);
330 MiscReg readMiscRegOperand(const StaticInst *si, int idx)
332 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
333 return thread->readMiscReg(reg_idx);
336 void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val)
338 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
339 return thread->setMiscRegNoEffect(reg_idx, val);
342 void setMiscRegOperand(
343 const StaticInst *si, int idx, const MiscReg &val)
345 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
346 return thread->setMiscReg(reg_idx, val);
349 unsigned readStCondFailures() {
350 return thread->readStCondFailures();
353 void setStCondFailures(unsigned sc_failures) {
354 thread->setStCondFailures(sc_failures);
357 MiscReg readRegOtherThread(int regIdx, int tid = -1)
359 panic("Simple CPU models do not support multithreaded "
360 "register access.\n");
363 void setRegOtherThread(int regIdx, const MiscReg &val, int tid = -1)
365 panic("Simple CPU models do not support multithreaded "
366 "register access.\n");
370 Fault hwrei() { return thread->hwrei(); }
371 void ev5_trap(Fault fault) { fault->invoke(tc); }
372 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
374 void syscall(int64_t callnum) { thread->syscall(callnum); }
377 bool misspeculating() { return thread->misspeculating(); }
378 ThreadContext *tcBase() { return tc; }
381 #endif // __CPU_SIMPLE_BASE_HH__