src/cpu/simple/base.hh

   1 /*
   2  * Copyright (c) 2011-2012,2015,2018 ARM Limited
   3  * Copyright (c) 2013 Advanced Micro Devices, Inc.
   4  * All rights reserved
   5  *
   6  * The license below extends only to copyright in the software and shall
   7  * not be construed as granting a license to any other intellectual
   8  * property including but not limited to intellectual property relating
   9  * to a hardware implementation of the functionality of the software
  10  * licensed hereunder.  You may use the software subject to the license
  11  * terms below provided that you ensure that this notice is replicated
  12  * unmodified and in its entirety in all distributions of the software,
  13  * modified or unmodified, in source code or in binary form.
  14  *
  15  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  */
  41
  42 #ifndef __CPU_SIMPLE_BASE_HH__
  43 #define __CPU_SIMPLE_BASE_HH__
  44
  45 #include "base/statistics.hh"
  46 #include "config/the_isa.hh"
  47 #include "cpu/base.hh"
  48 #include "cpu/checker/cpu.hh"
  49 #include "cpu/exec_context.hh"
  50 #include "cpu/pc_event.hh"
  51 #include "cpu/simple_thread.hh"
  52 #include "cpu/static_inst.hh"
  53 #include "mem/packet.hh"
  54 #include "mem/port.hh"
  55 #include "mem/request.hh"
  56 #include "sim/eventq.hh"
  57 #include "sim/full_system.hh"
  58 #include "sim/system.hh"
  59
  60 // forward declarations
  61 class Checkpoint;
  62 class Process;
  63 class Processor;
  64 class ThreadContext;
  65
  66 namespace TheISA
  67 {
  68     class DTB;
  69     class ITB;
  70 }
  71
  72 namespace Trace {
  73     class InstRecord;
  74 }
  75
  76 struct BaseSimpleCPUParams;
  77 class BPredUnit;
  78 class SimpleExecContext;
  79
  80 class BaseSimpleCPU : public BaseCPU
  81 {
  82   protected:
  83     ThreadID curThread;
  84     BPredUnit *branchPred;
  85
  86     void checkPcEventQueue();
  87     void swapActiveThread();
  88
  89   public:
  90     BaseSimpleCPU(BaseSimpleCPUParams *params);
  91     virtual ~BaseSimpleCPU();
  92     void wakeup(ThreadID tid) override;
  93     void init() override;
  94   public:
  95     Trace::InstRecord *traceData;
  96     CheckerCPU *checker;
  97
  98     std::vector<SimpleExecContext*> threadInfo;
  99     std::list<ThreadID> activeThreads;
 100
 101     /** Current instruction */
 102     TheISA::MachInst inst;
 103     StaticInstPtr curStaticInst;
 104     StaticInstPtr curMacroStaticInst;
 105
 106   protected:
 107     enum Status {
 108         Idle,
 109         Running,
 110         Faulting,
 111         ITBWaitResponse,
 112         IcacheRetry,
 113         IcacheWaitResponse,
 114         IcacheWaitSwitch,
 115         DTBWaitResponse,
 116         DcacheRetry,
 117         DcacheWaitResponse,
 118         DcacheWaitSwitch,
 119     };
 120
 121     Status _status;
 122
 123   public:
 124     void checkForInterrupts();
 125     void setupFetchRequest(const RequestPtr &req);
 126     void preExecute();
 127     void postExecute();
 128     void advancePC(const Fault &fault);
 129
 130     void haltContext(ThreadID thread_num) override;
 131
 132     // statistics
 133     void regStats() override;
 134     void resetStats() override;
 135
 136     virtual Fault readMem(Addr addr, uint8_t* data, unsigned size,
 137                           Request::Flags flags,
 138                           const std::vector<bool>& byte_enable =
 139                               std::vector<bool>())
 140     { panic("readMem() is not implemented\n"); }
 141
 142     virtual Fault initiateMemRead(Addr addr, unsigned size,
 143                                   Request::Flags flags,
 144                                   const std::vector<bool>& byte_enable =
 145                                       std::vector<bool>())
 146     { panic("initiateMemRead() is not implemented\n"); }
 147
 148     virtual Fault writeMem(uint8_t* data, unsigned size, Addr addr,
 149                            Request::Flags flags, uint64_t* res,
 150                            const std::vector<bool>& byte_enable =
 151                                std::vector<bool>())
 152     { panic("writeMem() is not implemented\n"); }
 153
 154     virtual Fault amoMem(Addr addr, uint8_t* data, unsigned size,
 155                          Request::Flags flags,
 156                          AtomicOpFunctorPtr amo_op)
 157     { panic("amoMem() is not implemented\n"); }
 158
 159     virtual Fault initiateMemAMO(Addr addr, unsigned size,
 160                                  Request::Flags flags,
 161                                  AtomicOpFunctorPtr amo_op)
 162     { panic("initiateMemAMO() is not implemented\n"); }
 163
 164     void countInst();
 165     Counter totalInsts() const override;
 166     Counter totalOps() const override;
 167
 168     void serializeThread(CheckpointOut &cp, ThreadID tid) const override;
 169     void unserializeThread(CheckpointIn &cp, ThreadID tid) override;
 170
 171 };
 172
 173 #endif // __CPU_SIMPLE_BASE_HH__