2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
33 #ifndef __CPU_SIMPLE_BASE_HH__
34 #define __CPU_SIMPLE_BASE_HH__
36 #include "base/statistics.hh"
37 #include "config/full_system.hh"
38 #include "cpu/base.hh"
39 #include "cpu/simple_thread.hh"
40 #include "cpu/pc_event.hh"
41 #include "cpu/static_inst.hh"
42 #include "mem/packet.hh"
43 #include "mem/port.hh"
44 #include "mem/request.hh"
45 #include "sim/eventq.hh"
47 // forward declarations
71 class BaseSimpleCPU : public BaseCPU
74 typedef TheISA::MachInst MachInst;
75 typedef TheISA::MiscReg MiscReg;
76 typedef TheISA::FloatReg FloatReg;
77 typedef TheISA::FloatRegBits FloatRegBits;
82 Trace::InstRecord *traceData;
85 void post_interrupt(int int_num, int index);
87 void zero_fill_64(Addr addr) {
88 static int warned = 0;
90 warn ("WH64 is not implemented");
96 struct Params : public BaseCPU::Params
106 BaseSimpleCPU(Params *params);
107 virtual ~BaseSimpleCPU();
110 /** SimpleThread object, provides all the architectural state. */
111 SimpleThread *thread;
113 /** ThreadContext object, provides an interface for external
114 * objects to modify this thread's state.
119 Addr dbg_vtophys(Addr addr);
124 // current instruction
127 // Static data storage
128 TheISA::IntReg dataReg;
130 StaticInstPtr curStaticInst;
132 void checkForInterrupts();
133 Fault setupFetchRequest(Request *req);
136 void advancePC(Fault fault);
138 virtual void deallocateContext(int thread_num);
139 virtual void haltContext(int thread_num);
142 virtual void regStats();
143 virtual void resetStats();
145 // number of simulated instructions
147 Counter startNumInst;
148 Stats::Scalar<> numInsts;
150 virtual Counter totalInstructions() const
152 return numInst - startNumInst;
155 // number of simulated memory references
156 Stats::Scalar<> numMemRefs;
158 // number of simulated loads
160 Counter startNumLoad;
162 // number of idle cycles
163 Stats::Average<> notIdleFraction;
164 Stats::Formula idleFraction;
166 // number of cycles stalled for I-cache responses
167 Stats::Scalar<> icacheStallCycles;
168 Counter lastIcacheStall;
170 // number of cycles stalled for I-cache retries
171 Stats::Scalar<> icacheRetryCycles;
172 Counter lastIcacheRetry;
174 // number of cycles stalled for D-cache responses
175 Stats::Scalar<> dcacheStallCycles;
176 Counter lastDcacheStall;
178 // number of cycles stalled for D-cache retries
179 Stats::Scalar<> dcacheRetryCycles;
180 Counter lastDcacheRetry;
182 virtual void serialize(std::ostream &os);
183 virtual void unserialize(Checkpoint *cp, const std::string §ion);
185 // These functions are only used in CPU models that split
186 // effective address computation from the actual memory access.
187 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
188 Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n"); }
190 void prefetch(Addr addr, unsigned flags)
192 // need to do this...
195 void writeHint(Addr addr, int size, unsigned flags)
197 // need to do this...
200 Fault copySrcTranslate(Addr src);
202 Fault copy(Addr dest);
204 // The register accessor methods provide the index of the
205 // instruction's operand (e.g., 0 or 1), not the architectural
206 // register index, to simplify the implementation of register
207 // renaming. We find the architectural register index by indexing
208 // into the instruction's own operand index table. Note that a
209 // raw pointer to the StaticInst is provided instead of a
210 // ref-counted StaticInstPtr to redice overhead. This is fine as
211 // long as these methods don't copy the pointer into any long-term
212 // storage (which is pretty hard to imagine they would have reason
215 uint64_t readIntReg(const StaticInst *si, int idx)
217 return thread->readIntReg(si->srcRegIdx(idx));
220 FloatReg readFloatReg(const StaticInst *si, int idx, int width)
222 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
223 return thread->readFloatReg(reg_idx, width);
226 FloatReg readFloatReg(const StaticInst *si, int idx)
228 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
229 return thread->readFloatReg(reg_idx);
232 FloatRegBits readFloatRegBits(const StaticInst *si, int idx, int width)
234 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
235 return thread->readFloatRegBits(reg_idx, width);
238 FloatRegBits readFloatRegBits(const StaticInst *si, int idx)
240 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
241 return thread->readFloatRegBits(reg_idx);
244 void setIntReg(const StaticInst *si, int idx, uint64_t val)
246 thread->setIntReg(si->destRegIdx(idx), val);
249 void setFloatReg(const StaticInst *si, int idx, FloatReg val, int width)
251 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
252 thread->setFloatReg(reg_idx, val, width);
255 void setFloatReg(const StaticInst *si, int idx, FloatReg val)
257 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
258 thread->setFloatReg(reg_idx, val);
261 void setFloatRegBits(const StaticInst *si, int idx,
262 FloatRegBits val, int width)
264 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
265 thread->setFloatRegBits(reg_idx, val, width);
268 void setFloatRegBits(const StaticInst *si, int idx, FloatRegBits val)
270 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
271 thread->setFloatRegBits(reg_idx, val);
274 uint64_t readPC() { return thread->readPC(); }
275 uint64_t readNextPC() { return thread->readNextPC(); }
276 uint64_t readNextNPC() { return thread->readNextNPC(); }
278 void setPC(uint64_t val) { thread->setPC(val); }
279 void setNextPC(uint64_t val) { thread->setNextPC(val); }
280 void setNextNPC(uint64_t val) { thread->setNextNPC(val); }
282 MiscReg readMiscReg(int misc_reg)
284 return thread->readMiscReg(misc_reg);
287 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
289 return thread->readMiscRegWithEffect(misc_reg, fault);
292 Fault setMiscReg(int misc_reg, const MiscReg &val)
294 return thread->setMiscReg(misc_reg, val);
297 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
299 return thread->setMiscRegWithEffect(misc_reg, val);
303 Fault hwrei() { return thread->hwrei(); }
304 int readIntrFlag() { return thread->readIntrFlag(); }
305 void setIntrFlag(int val) { thread->setIntrFlag(val); }
306 bool inPalMode() { return thread->inPalMode(); }
307 void ev5_trap(Fault fault) { fault->invoke(tc); }
308 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
310 void syscall(int64_t callnum) { thread->syscall(callnum); }
313 bool misspeculating() { return thread->misspeculating(); }
314 ThreadContext *tcBase() { return tc; }
317 #endif // __CPU_SIMPLE_BASE_HH__