2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
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14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
33 #ifndef __CPU_SIMPLE_BASE_HH__
34 #define __CPU_SIMPLE_BASE_HH__
36 #include "arch/predecoder.hh"
37 #include "base/statistics.hh"
38 #include "config/full_system.hh"
39 #include "cpu/base.hh"
40 #include "cpu/simple_thread.hh"
41 #include "cpu/pc_event.hh"
42 #include "cpu/static_inst.hh"
43 #include "mem/packet.hh"
44 #include "mem/port.hh"
45 #include "mem/request.hh"
46 #include "sim/eventq.hh"
47 #include "sim/system.hh"
49 // forward declarations
79 class BaseSimpleCPUParams;
82 class BaseSimpleCPU : public BaseCPU
85 typedef TheISA::MiscReg MiscReg;
86 typedef TheISA::FloatReg FloatReg;
87 typedef TheISA::FloatRegBits FloatRegBits;
90 Trace::InstRecord *traceData;
92 inline void checkPcEventQueue() {
95 oldpc = thread->readPC();
96 system->pcEventQueue.service(tc);
97 } while (oldpc != thread->readPC());
103 void zero_fill_64(Addr addr) {
104 static int warned = 0;
106 warn ("WH64 is not implemented");
112 BaseSimpleCPU(BaseSimpleCPUParams *params);
113 virtual ~BaseSimpleCPU();
116 /** SimpleThread object, provides all the architectural state. */
117 SimpleThread *thread;
119 /** ThreadContext object, provides an interface for external
120 * objects to modify this thread's state.
144 Addr dbg_vtophys(Addr addr);
149 // current instruction
150 TheISA::MachInst inst;
153 TheISA::Predecoder predecoder;
155 StaticInstPtr curStaticInst;
156 StaticInstPtr curMacroStaticInst;
158 //This is the offset from the current pc that fetch should be performed at
160 //This flag says to stay at the current pc. This is useful for
161 //instructions which go beyond MachInst boundaries.
164 void checkForInterrupts();
165 void setupFetchRequest(Request *req);
168 void advancePC(Fault fault);
170 virtual void deallocateContext(int thread_num);
171 virtual void haltContext(int thread_num);
174 virtual void regStats();
175 virtual void resetStats();
177 // number of simulated instructions
179 Counter startNumInst;
180 Stats::Scalar numInsts;
187 thread->funcExeInst++;
190 virtual Counter totalInstructions() const
192 return numInst - startNumInst;
195 // Mask to align PCs to MachInst sized boundaries
196 static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
198 // number of simulated memory references
199 Stats::Scalar numMemRefs;
201 // number of simulated loads
203 Counter startNumLoad;
205 // number of idle cycles
206 Stats::Average notIdleFraction;
207 Stats::Formula idleFraction;
209 // number of cycles stalled for I-cache responses
210 Stats::Scalar icacheStallCycles;
211 Counter lastIcacheStall;
213 // number of cycles stalled for I-cache retries
214 Stats::Scalar icacheRetryCycles;
215 Counter lastIcacheRetry;
217 // number of cycles stalled for D-cache responses
218 Stats::Scalar dcacheStallCycles;
219 Counter lastDcacheStall;
221 // number of cycles stalled for D-cache retries
222 Stats::Scalar dcacheRetryCycles;
223 Counter lastDcacheRetry;
225 virtual void serialize(std::ostream &os);
226 virtual void unserialize(Checkpoint *cp, const std::string §ion);
228 // These functions are only used in CPU models that split
229 // effective address computation from the actual memory access.
230 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
231 Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n");
234 void prefetch(Addr addr, unsigned flags)
236 // need to do this...
239 void writeHint(Addr addr, int size, unsigned flags)
241 // need to do this...
245 Fault copySrcTranslate(Addr src);
247 Fault copy(Addr dest);
249 // The register accessor methods provide the index of the
250 // instruction's operand (e.g., 0 or 1), not the architectural
251 // register index, to simplify the implementation of register
252 // renaming. We find the architectural register index by indexing
253 // into the instruction's own operand index table. Note that a
254 // raw pointer to the StaticInst is provided instead of a
255 // ref-counted StaticInstPtr to redice overhead. This is fine as
256 // long as these methods don't copy the pointer into any long-term
257 // storage (which is pretty hard to imagine they would have reason
260 uint64_t readIntRegOperand(const StaticInst *si, int idx)
262 return thread->readIntReg(si->srcRegIdx(idx));
265 FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
267 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
268 return thread->readFloatReg(reg_idx, width);
271 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
273 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
274 return thread->readFloatReg(reg_idx);
277 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
280 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
281 return thread->readFloatRegBits(reg_idx, width);
284 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
286 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
287 return thread->readFloatRegBits(reg_idx);
290 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
292 thread->setIntReg(si->destRegIdx(idx), val);
295 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
298 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
299 thread->setFloatReg(reg_idx, val, width);
302 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
304 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
305 thread->setFloatReg(reg_idx, val);
308 void setFloatRegOperandBits(const StaticInst *si, int idx,
309 FloatRegBits val, int width)
311 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
312 thread->setFloatRegBits(reg_idx, val, width);
315 void setFloatRegOperandBits(const StaticInst *si, int idx,
318 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
319 thread->setFloatRegBits(reg_idx, val);
322 uint64_t readPC() { return thread->readPC(); }
323 uint64_t readMicroPC() { return thread->readMicroPC(); }
324 uint64_t readNextPC() { return thread->readNextPC(); }
325 uint64_t readNextMicroPC() { return thread->readNextMicroPC(); }
326 uint64_t readNextNPC() { return thread->readNextNPC(); }
328 void setPC(uint64_t val) { thread->setPC(val); }
329 void setMicroPC(uint64_t val) { thread->setMicroPC(val); }
330 void setNextPC(uint64_t val) { thread->setNextPC(val); }
331 void setNextMicroPC(uint64_t val) { thread->setNextMicroPC(val); }
332 void setNextNPC(uint64_t val) { thread->setNextNPC(val); }
334 MiscReg readMiscRegNoEffect(int misc_reg)
336 return thread->readMiscRegNoEffect(misc_reg);
339 MiscReg readMiscReg(int misc_reg)
341 return thread->readMiscReg(misc_reg);
344 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
346 return thread->setMiscRegNoEffect(misc_reg, val);
349 void setMiscReg(int misc_reg, const MiscReg &val)
351 return thread->setMiscReg(misc_reg, val);
354 MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx)
356 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
357 return thread->readMiscRegNoEffect(reg_idx);
360 MiscReg readMiscRegOperand(const StaticInst *si, int idx)
362 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
363 return thread->readMiscReg(reg_idx);
366 void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val)
368 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
369 return thread->setMiscRegNoEffect(reg_idx, val);
372 void setMiscRegOperand(
373 const StaticInst *si, int idx, const MiscReg &val)
375 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
376 return thread->setMiscReg(reg_idx, val);
379 void demapPage(Addr vaddr, uint64_t asn)
381 thread->demapPage(vaddr, asn);
384 void demapInstPage(Addr vaddr, uint64_t asn)
386 thread->demapInstPage(vaddr, asn);
389 void demapDataPage(Addr vaddr, uint64_t asn)
391 thread->demapDataPage(vaddr, asn);
394 unsigned readStCondFailures() {
395 return thread->readStCondFailures();
398 void setStCondFailures(unsigned sc_failures) {
399 thread->setStCondFailures(sc_failures);
402 MiscReg readRegOtherThread(int regIdx, int tid = -1)
404 panic("Simple CPU models do not support multithreaded "
405 "register access.\n");
408 void setRegOtherThread(int regIdx, const MiscReg &val, int tid = -1)
410 panic("Simple CPU models do not support multithreaded "
411 "register access.\n");
414 //Fault CacheOp(uint8_t Op, Addr EA);
417 Fault hwrei() { return thread->hwrei(); }
418 void ev5_trap(Fault fault) { fault->invoke(tc); }
419 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
421 void syscall(int64_t callnum) { thread->syscall(callnum); }
424 bool misspeculating() { return thread->misspeculating(); }
425 ThreadContext *tcBase() { return tc; }
428 #endif // __CPU_SIMPLE_BASE_HH__