2 * Copyright (c) 2011-2012 ARM Limited
3 * Copyright (c) 2013 Advanced Micro Devices, Inc.
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15 * Copyright (c) 2002-2005 The Regents of The University of Michigan
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19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
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27 * this software without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 * Authors: Steve Reinhardt
46 #ifndef __CPU_SIMPLE_BASE_HH__
47 #define __CPU_SIMPLE_BASE_HH__
49 #include "base/statistics.hh"
50 #include "config/the_isa.hh"
51 #include "cpu/base.hh"
52 #include "cpu/checker/cpu.hh"
53 #include "cpu/pc_event.hh"
54 #include "cpu/simple_thread.hh"
55 #include "cpu/static_inst.hh"
56 #include "mem/packet.hh"
57 #include "mem/port.hh"
58 #include "mem/request.hh"
59 #include "sim/eventq.hh"
60 #include "sim/full_system.hh"
61 #include "sim/system.hh"
63 // forward declarations
79 struct BaseSimpleCPUParams;
82 class BaseSimpleCPU : public BaseCPU
85 typedef TheISA::MiscReg MiscReg;
86 typedef TheISA::FloatReg FloatReg;
87 typedef TheISA::FloatRegBits FloatRegBits;
88 typedef TheISA::CCReg CCReg;
90 BPredUnit *branchPred;
93 Trace::InstRecord *traceData;
95 inline void checkPcEventQueue() {
96 Addr oldpc, pc = thread->instAddr();
99 system->pcEventQueue.service(tc);
100 pc = thread->instAddr();
101 } while (oldpc != pc);
107 void zero_fill_64(Addr addr) {
108 static int warned = 0;
110 warn ("WH64 is not implemented");
116 BaseSimpleCPU(BaseSimpleCPUParams *params);
117 virtual ~BaseSimpleCPU();
120 /** SimpleThread object, provides all the architectural state. */
121 SimpleThread *thread;
123 /** ThreadContext object, provides an interface for external
124 * objects to modify this thread's state.
150 Addr dbg_vtophys(Addr addr);
154 // current instruction
155 TheISA::MachInst inst;
157 StaticInstPtr curStaticInst;
158 StaticInstPtr curMacroStaticInst;
160 //This is the offset from the current pc that fetch should be performed at
162 //This flag says to stay at the current pc. This is useful for
163 //instructions which go beyond MachInst boundaries.
166 void checkForInterrupts();
167 void setupFetchRequest(Request *req);
170 void advancePC(Fault fault);
172 virtual void deallocateContext(ThreadID thread_num);
173 virtual void haltContext(ThreadID thread_num);
176 virtual void regStats();
177 virtual void resetStats();
179 virtual void startup();
181 // number of simulated instructions
183 Counter startNumInst;
184 Stats::Scalar numInsts;
187 Stats::Scalar numOps;
191 if (!curStaticInst->isMicroop() || curStaticInst->isLastMicroop()) {
198 system->totalNumInsts++;
199 thread->funcExeInst++;
202 virtual Counter totalInsts() const
204 return numInst - startNumInst;
207 virtual Counter totalOps() const
209 return numOp - startNumOp;
212 //number of integer alu accesses
213 Stats::Scalar numIntAluAccesses;
215 //number of float alu accesses
216 Stats::Scalar numFpAluAccesses;
218 //number of function calls/returns
219 Stats::Scalar numCallsReturns;
221 //conditional control instructions;
222 Stats::Scalar numCondCtrlInsts;
224 //number of int instructions
225 Stats::Scalar numIntInsts;
227 //number of float instructions
228 Stats::Scalar numFpInsts;
230 //number of integer register file accesses
231 Stats::Scalar numIntRegReads;
232 Stats::Scalar numIntRegWrites;
234 //number of float register file accesses
235 Stats::Scalar numFpRegReads;
236 Stats::Scalar numFpRegWrites;
238 //number of condition code register file accesses
239 Stats::Scalar numCCRegReads;
240 Stats::Scalar numCCRegWrites;
242 // number of simulated memory references
243 Stats::Scalar numMemRefs;
244 Stats::Scalar numLoadInsts;
245 Stats::Scalar numStoreInsts;
247 // number of idle cycles
248 Stats::Formula numIdleCycles;
250 // number of busy cycles
251 Stats::Formula numBusyCycles;
253 // number of simulated loads
255 Counter startNumLoad;
257 // number of idle cycles
258 Stats::Average notIdleFraction;
259 Stats::Formula idleFraction;
261 // number of cycles stalled for I-cache responses
262 Stats::Scalar icacheStallCycles;
263 Counter lastIcacheStall;
265 // number of cycles stalled for I-cache retries
266 Stats::Scalar icacheRetryCycles;
267 Counter lastIcacheRetry;
269 // number of cycles stalled for D-cache responses
270 Stats::Scalar dcacheStallCycles;
271 Counter lastDcacheStall;
273 // number of cycles stalled for D-cache retries
274 Stats::Scalar dcacheRetryCycles;
275 Counter lastDcacheRetry;
278 /// Total number of branches fetched
279 Stats::Scalar numBranches;
280 /// Number of branches predicted as taken
281 Stats::Scalar numPredictedBranches;
282 /// Number of misprediced branches
283 Stats::Scalar numBranchMispred;
286 // instruction mix histogram by OpClass
287 Stats::Vector statExecutedInstType;
289 void serializeThread(std::ostream &os, ThreadID tid);
290 void unserializeThread(Checkpoint *cp, const std::string §ion,
293 // These functions are only used in CPU models that split
294 // effective address computation from the actual memory access.
295 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
296 Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n");
299 // The register accessor methods provide the index of the
300 // instruction's operand (e.g., 0 or 1), not the architectural
301 // register index, to simplify the implementation of register
302 // renaming. We find the architectural register index by indexing
303 // into the instruction's own operand index table. Note that a
304 // raw pointer to the StaticInst is provided instead of a
305 // ref-counted StaticInstPtr to redice overhead. This is fine as
306 // long as these methods don't copy the pointer into any long-term
307 // storage (which is pretty hard to imagine they would have reason
310 uint64_t readIntRegOperand(const StaticInst *si, int idx)
313 return thread->readIntReg(si->srcRegIdx(idx));
316 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
319 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
320 return thread->readFloatReg(reg_idx);
323 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
326 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
327 return thread->readFloatRegBits(reg_idx);
330 CCReg readCCRegOperand(const StaticInst *si, int idx)
333 int reg_idx = si->srcRegIdx(idx) - TheISA::CC_Reg_Base;
334 return thread->readCCReg(reg_idx);
337 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
340 thread->setIntReg(si->destRegIdx(idx), val);
343 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
346 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
347 thread->setFloatReg(reg_idx, val);
350 void setFloatRegOperandBits(const StaticInst *si, int idx,
354 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
355 thread->setFloatRegBits(reg_idx, val);
358 void setCCRegOperand(const StaticInst *si, int idx, CCReg val)
361 int reg_idx = si->destRegIdx(idx) - TheISA::CC_Reg_Base;
362 thread->setCCReg(reg_idx, val);
365 bool readPredicate() { return thread->readPredicate(); }
366 void setPredicate(bool val)
368 thread->setPredicate(val);
370 traceData->setPredicate(val);
373 TheISA::PCState pcState() { return thread->pcState(); }
374 void pcState(const TheISA::PCState &val) { thread->pcState(val); }
375 Addr instAddr() { return thread->instAddr(); }
376 Addr nextInstAddr() { return thread->nextInstAddr(); }
377 MicroPC microPC() { return thread->microPC(); }
379 MiscReg readMiscRegNoEffect(int misc_reg)
381 return thread->readMiscRegNoEffect(misc_reg);
384 MiscReg readMiscReg(int misc_reg)
387 return thread->readMiscReg(misc_reg);
390 void setMiscReg(int misc_reg, const MiscReg &val)
393 return thread->setMiscReg(misc_reg, val);
396 MiscReg readMiscRegOperand(const StaticInst *si, int idx)
399 int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base;
400 return thread->readMiscReg(reg_idx);
403 void setMiscRegOperand(
404 const StaticInst *si, int idx, const MiscReg &val)
407 int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
408 return thread->setMiscReg(reg_idx, val);
411 void demapPage(Addr vaddr, uint64_t asn)
413 thread->demapPage(vaddr, asn);
416 void demapInstPage(Addr vaddr, uint64_t asn)
418 thread->demapInstPage(vaddr, asn);
421 void demapDataPage(Addr vaddr, uint64_t asn)
423 thread->demapDataPage(vaddr, asn);
426 unsigned readStCondFailures() {
427 return thread->readStCondFailures();
430 void setStCondFailures(unsigned sc_failures) {
431 thread->setStCondFailures(sc_failures);
434 MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID)
436 panic("Simple CPU models do not support multithreaded "
437 "register access.\n");
440 void setRegOtherThread(int regIdx, const MiscReg &val,
441 ThreadID tid = InvalidThreadID)
443 panic("Simple CPU models do not support multithreaded "
444 "register access.\n");
447 //Fault CacheOp(uint8_t Op, Addr EA);
449 Fault hwrei() { return thread->hwrei(); }
450 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
453 syscall(int64_t callnum)
456 panic("Syscall emulation isn't available in FS mode.\n");
458 thread->syscall(callnum);
461 bool misspeculating() { return thread->misspeculating(); }
462 ThreadContext *tcBase() { return tc; }
465 TheISA::PCState pred_pc;
468 #endif // __CPU_SIMPLE_BASE_HH__