2 * Copyright (c) 2011-2012 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
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12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
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18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
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26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Steve Reinhardt
45 #ifndef __CPU_SIMPLE_BASE_HH__
46 #define __CPU_SIMPLE_BASE_HH__
48 #include "base/statistics.hh"
49 #include "config/the_isa.hh"
50 #include "cpu/base.hh"
51 #include "cpu/checker/cpu.hh"
52 #include "cpu/pc_event.hh"
53 #include "cpu/simple_thread.hh"
54 #include "cpu/static_inst.hh"
55 #include "mem/packet.hh"
56 #include "mem/port.hh"
57 #include "mem/request.hh"
58 #include "sim/eventq.hh"
59 #include "sim/full_system.hh"
60 #include "sim/system.hh"
62 // forward declarations
78 struct BaseSimpleCPUParams;
81 class BaseSimpleCPU : public BaseCPU
84 typedef TheISA::MiscReg MiscReg;
85 typedef TheISA::FloatReg FloatReg;
86 typedef TheISA::FloatRegBits FloatRegBits;
89 Trace::InstRecord *traceData;
91 inline void checkPcEventQueue() {
92 Addr oldpc, pc = thread->instAddr();
95 system->pcEventQueue.service(tc);
96 pc = thread->instAddr();
97 } while (oldpc != pc);
103 void zero_fill_64(Addr addr) {
104 static int warned = 0;
106 warn ("WH64 is not implemented");
112 BaseSimpleCPU(BaseSimpleCPUParams *params);
113 virtual ~BaseSimpleCPU();
116 /** SimpleThread object, provides all the architectural state. */
117 SimpleThread *thread;
119 /** ThreadContext object, provides an interface for external
120 * objects to modify this thread's state.
146 Addr dbg_vtophys(Addr addr);
150 // current instruction
151 TheISA::MachInst inst;
153 StaticInstPtr curStaticInst;
154 StaticInstPtr curMacroStaticInst;
156 //This is the offset from the current pc that fetch should be performed at
158 //This flag says to stay at the current pc. This is useful for
159 //instructions which go beyond MachInst boundaries.
162 void checkForInterrupts();
163 void setupFetchRequest(Request *req);
166 void advancePC(Fault fault);
168 virtual void deallocateContext(ThreadID thread_num);
169 virtual void haltContext(ThreadID thread_num);
172 virtual void regStats();
173 virtual void resetStats();
175 virtual void startup();
177 // number of simulated instructions
179 Counter startNumInst;
180 Stats::Scalar numInsts;
183 Stats::Scalar numOps;
187 if (!curStaticInst->isMicroop() || curStaticInst->isLastMicroop()) {
194 system->totalNumInsts++;
195 thread->funcExeInst++;
198 virtual Counter totalInsts() const
200 return numInst - startNumInst;
203 virtual Counter totalOps() const
205 return numOp - startNumOp;
208 //number of integer alu accesses
209 Stats::Scalar numIntAluAccesses;
211 //number of float alu accesses
212 Stats::Scalar numFpAluAccesses;
214 //number of function calls/returns
215 Stats::Scalar numCallsReturns;
217 //conditional control instructions;
218 Stats::Scalar numCondCtrlInsts;
220 //number of int instructions
221 Stats::Scalar numIntInsts;
223 //number of float instructions
224 Stats::Scalar numFpInsts;
226 //number of integer register file accesses
227 Stats::Scalar numIntRegReads;
228 Stats::Scalar numIntRegWrites;
230 //number of float register file accesses
231 Stats::Scalar numFpRegReads;
232 Stats::Scalar numFpRegWrites;
234 // number of simulated memory references
235 Stats::Scalar numMemRefs;
236 Stats::Scalar numLoadInsts;
237 Stats::Scalar numStoreInsts;
239 // number of idle cycles
240 Stats::Formula numIdleCycles;
242 // number of busy cycles
243 Stats::Formula numBusyCycles;
245 // number of simulated loads
247 Counter startNumLoad;
249 // number of idle cycles
250 Stats::Average notIdleFraction;
251 Stats::Formula idleFraction;
253 // number of cycles stalled for I-cache responses
254 Stats::Scalar icacheStallCycles;
255 Counter lastIcacheStall;
257 // number of cycles stalled for I-cache retries
258 Stats::Scalar icacheRetryCycles;
259 Counter lastIcacheRetry;
261 // number of cycles stalled for D-cache responses
262 Stats::Scalar dcacheStallCycles;
263 Counter lastDcacheStall;
265 // number of cycles stalled for D-cache retries
266 Stats::Scalar dcacheRetryCycles;
267 Counter lastDcacheRetry;
269 void serializeThread(std::ostream &os, ThreadID tid);
270 void unserializeThread(Checkpoint *cp, const std::string §ion,
273 // These functions are only used in CPU models that split
274 // effective address computation from the actual memory access.
275 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
276 Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n");
279 // The register accessor methods provide the index of the
280 // instruction's operand (e.g., 0 or 1), not the architectural
281 // register index, to simplify the implementation of register
282 // renaming. We find the architectural register index by indexing
283 // into the instruction's own operand index table. Note that a
284 // raw pointer to the StaticInst is provided instead of a
285 // ref-counted StaticInstPtr to redice overhead. This is fine as
286 // long as these methods don't copy the pointer into any long-term
287 // storage (which is pretty hard to imagine they would have reason
290 uint64_t readIntRegOperand(const StaticInst *si, int idx)
293 return thread->readIntReg(si->srcRegIdx(idx));
296 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
299 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
300 return thread->readFloatReg(reg_idx);
303 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
306 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Reg_Base;
307 return thread->readFloatRegBits(reg_idx);
310 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
313 thread->setIntReg(si->destRegIdx(idx), val);
316 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
319 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
320 thread->setFloatReg(reg_idx, val);
323 void setFloatRegOperandBits(const StaticInst *si, int idx,
327 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Reg_Base;
328 thread->setFloatRegBits(reg_idx, val);
331 bool readPredicate() { return thread->readPredicate(); }
332 void setPredicate(bool val)
334 thread->setPredicate(val);
336 traceData->setPredicate(val);
339 TheISA::PCState pcState() { return thread->pcState(); }
340 void pcState(const TheISA::PCState &val) { thread->pcState(val); }
341 Addr instAddr() { return thread->instAddr(); }
342 Addr nextInstAddr() { return thread->nextInstAddr(); }
343 MicroPC microPC() { return thread->microPC(); }
345 MiscReg readMiscRegNoEffect(int misc_reg)
347 return thread->readMiscRegNoEffect(misc_reg);
350 MiscReg readMiscReg(int misc_reg)
353 return thread->readMiscReg(misc_reg);
356 void setMiscReg(int misc_reg, const MiscReg &val)
359 return thread->setMiscReg(misc_reg, val);
362 MiscReg readMiscRegOperand(const StaticInst *si, int idx)
365 int reg_idx = si->srcRegIdx(idx) - TheISA::Misc_Reg_Base;
366 return thread->readMiscReg(reg_idx);
369 void setMiscRegOperand(
370 const StaticInst *si, int idx, const MiscReg &val)
373 int reg_idx = si->destRegIdx(idx) - TheISA::Misc_Reg_Base;
374 return thread->setMiscReg(reg_idx, val);
377 void demapPage(Addr vaddr, uint64_t asn)
379 thread->demapPage(vaddr, asn);
382 void demapInstPage(Addr vaddr, uint64_t asn)
384 thread->demapInstPage(vaddr, asn);
387 void demapDataPage(Addr vaddr, uint64_t asn)
389 thread->demapDataPage(vaddr, asn);
392 unsigned readStCondFailures() {
393 return thread->readStCondFailures();
396 void setStCondFailures(unsigned sc_failures) {
397 thread->setStCondFailures(sc_failures);
400 MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID)
402 panic("Simple CPU models do not support multithreaded "
403 "register access.\n");
406 void setRegOtherThread(int regIdx, const MiscReg &val,
407 ThreadID tid = InvalidThreadID)
409 panic("Simple CPU models do not support multithreaded "
410 "register access.\n");
413 //Fault CacheOp(uint8_t Op, Addr EA);
415 Fault hwrei() { return thread->hwrei(); }
416 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
419 syscall(int64_t callnum)
422 panic("Syscall emulation isn't available in FS mode.\n");
424 thread->syscall(callnum);
427 bool misspeculating() { return thread->misspeculating(); }
428 ThreadContext *tcBase() { return tc; }
431 #endif // __CPU_SIMPLE_BASE_HH__