2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
33 #ifndef __CPU_SIMPLE_BASE_HH__
34 #define __CPU_SIMPLE_BASE_HH__
36 #include "arch/predecoder.hh"
37 #include "base/statistics.hh"
38 #include "config/full_system.hh"
39 #include "cpu/base.hh"
40 #include "cpu/simple_thread.hh"
41 #include "cpu/pc_event.hh"
42 #include "cpu/static_inst.hh"
43 #include "mem/packet.hh"
44 #include "mem/port.hh"
45 #include "mem/request.hh"
46 #include "sim/eventq.hh"
48 // forward declarations
79 class BaseSimpleCPU : public BaseCPU
82 typedef TheISA::MiscReg MiscReg;
83 typedef TheISA::FloatReg FloatReg;
84 typedef TheISA::FloatRegBits FloatRegBits;
87 Trace::InstRecord *traceData;
90 void post_interrupt(int int_num, int index);
92 void zero_fill_64(Addr addr) {
93 static int warned = 0;
95 warn ("WH64 is not implemented");
101 struct Params : public BaseCPU::Params
110 BaseSimpleCPU(Params *params);
111 virtual ~BaseSimpleCPU();
114 /** SimpleThread object, provides all the architectural state. */
115 SimpleThread *thread;
117 /** ThreadContext object, provides an interface for external
118 * objects to modify this thread's state.
123 Addr dbg_vtophys(Addr addr);
128 // current instruction
129 TheISA::MachInst inst;
132 TheISA::Predecoder predecoder;
134 // Static data storage
135 TheISA::LargestRead dataReg;
137 StaticInstPtr curStaticInst;
138 StaticInstPtr curMacroStaticInst;
140 void checkForInterrupts();
141 Fault setupFetchRequest(Request *req);
144 void advancePC(Fault fault);
146 virtual void deallocateContext(int thread_num);
147 virtual void haltContext(int thread_num);
150 virtual void regStats();
151 virtual void resetStats();
153 // number of simulated instructions
155 Counter startNumInst;
156 Stats::Scalar<> numInsts;
158 virtual Counter totalInstructions() const
160 return numInst - startNumInst;
163 // number of simulated memory references
164 Stats::Scalar<> numMemRefs;
166 // number of simulated loads
168 Counter startNumLoad;
170 // number of idle cycles
171 Stats::Average<> notIdleFraction;
172 Stats::Formula idleFraction;
174 // number of cycles stalled for I-cache responses
175 Stats::Scalar<> icacheStallCycles;
176 Counter lastIcacheStall;
178 // number of cycles stalled for I-cache retries
179 Stats::Scalar<> icacheRetryCycles;
180 Counter lastIcacheRetry;
182 // number of cycles stalled for D-cache responses
183 Stats::Scalar<> dcacheStallCycles;
184 Counter lastDcacheStall;
186 // number of cycles stalled for D-cache retries
187 Stats::Scalar<> dcacheRetryCycles;
188 Counter lastDcacheRetry;
190 virtual void serialize(std::ostream &os);
191 virtual void unserialize(Checkpoint *cp, const std::string §ion);
193 // These functions are only used in CPU models that split
194 // effective address computation from the actual memory access.
195 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
196 Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n");
199 void prefetch(Addr addr, unsigned flags)
201 // need to do this...
204 void writeHint(Addr addr, int size, unsigned flags)
206 // need to do this...
209 Fault copySrcTranslate(Addr src);
211 Fault copy(Addr dest);
213 // The register accessor methods provide the index of the
214 // instruction's operand (e.g., 0 or 1), not the architectural
215 // register index, to simplify the implementation of register
216 // renaming. We find the architectural register index by indexing
217 // into the instruction's own operand index table. Note that a
218 // raw pointer to the StaticInst is provided instead of a
219 // ref-counted StaticInstPtr to redice overhead. This is fine as
220 // long as these methods don't copy the pointer into any long-term
221 // storage (which is pretty hard to imagine they would have reason
224 uint64_t readIntRegOperand(const StaticInst *si, int idx)
226 return thread->readIntReg(si->srcRegIdx(idx));
229 FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
231 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
232 return thread->readFloatReg(reg_idx, width);
235 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
237 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
238 return thread->readFloatReg(reg_idx);
241 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
244 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
245 return thread->readFloatRegBits(reg_idx, width);
248 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
250 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
251 return thread->readFloatRegBits(reg_idx);
254 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
256 thread->setIntReg(si->destRegIdx(idx), val);
259 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
262 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
263 thread->setFloatReg(reg_idx, val, width);
266 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
268 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
269 thread->setFloatReg(reg_idx, val);
272 void setFloatRegOperandBits(const StaticInst *si, int idx,
273 FloatRegBits val, int width)
275 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
276 thread->setFloatRegBits(reg_idx, val, width);
279 void setFloatRegOperandBits(const StaticInst *si, int idx,
282 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
283 thread->setFloatRegBits(reg_idx, val);
286 uint64_t readPC() { return thread->readPC(); }
287 uint64_t readNextPC() { return thread->readNextPC(); }
288 uint64_t readNextNPC() { return thread->readNextNPC(); }
290 void setPC(uint64_t val) { thread->setPC(val); }
291 void setNextPC(uint64_t val) { thread->setNextPC(val); }
292 void setNextNPC(uint64_t val) { thread->setNextNPC(val); }
294 MiscReg readMiscRegNoEffect(int misc_reg)
296 return thread->readMiscRegNoEffect(misc_reg);
299 MiscReg readMiscReg(int misc_reg)
301 return thread->readMiscReg(misc_reg);
304 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
306 return thread->setMiscRegNoEffect(misc_reg, val);
309 void setMiscReg(int misc_reg, const MiscReg &val)
311 return thread->setMiscReg(misc_reg, val);
314 MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx)
316 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
317 return thread->readMiscRegNoEffect(reg_idx);
320 MiscReg readMiscRegOperand(const StaticInst *si, int idx)
322 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
323 return thread->readMiscReg(reg_idx);
326 void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val)
328 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
329 return thread->setMiscRegNoEffect(reg_idx, val);
332 void setMiscRegOperand(
333 const StaticInst *si, int idx, const MiscReg &val)
335 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
336 return thread->setMiscReg(reg_idx, val);
339 unsigned readStCondFailures() {
340 return thread->readStCondFailures();
343 void setStCondFailures(unsigned sc_failures) {
344 thread->setStCondFailures(sc_failures);
348 Fault hwrei() { return thread->hwrei(); }
349 void ev5_trap(Fault fault) { fault->invoke(tc); }
350 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
352 void syscall(int64_t callnum) { thread->syscall(callnum); }
355 bool misspeculating() { return thread->misspeculating(); }
356 ThreadContext *tcBase() { return tc; }
359 #endif // __CPU_SIMPLE_BASE_HH__