2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
33 #ifndef __CPU_SIMPLE_BASE_HH__
34 #define __CPU_SIMPLE_BASE_HH__
36 #include "arch/predecoder.hh"
37 #include "base/statistics.hh"
38 #include "config/full_system.hh"
39 #include "cpu/base.hh"
40 #include "cpu/simple_thread.hh"
41 #include "cpu/pc_event.hh"
42 #include "cpu/static_inst.hh"
43 #include "mem/packet.hh"
44 #include "mem/port.hh"
45 #include "mem/request.hh"
46 #include "sim/eventq.hh"
48 // forward declarations
79 class BaseSimpleCPU : public BaseCPU
82 typedef TheISA::MiscReg MiscReg;
83 typedef TheISA::FloatReg FloatReg;
84 typedef TheISA::FloatRegBits FloatRegBits;
87 Trace::InstRecord *traceData;
90 void post_interrupt(int int_num, int index);
92 void zero_fill_64(Addr addr) {
93 static int warned = 0;
95 warn ("WH64 is not implemented");
101 struct Params : public BaseCPU::Params
110 BaseSimpleCPU(Params *params);
111 virtual ~BaseSimpleCPU();
114 /** SimpleThread object, provides all the architectural state. */
115 SimpleThread *thread;
117 /** ThreadContext object, provides an interface for external
118 * objects to modify this thread's state.
123 Addr dbg_vtophys(Addr addr);
128 // current instruction
129 TheISA::MachInst inst;
132 TheISA::Predecoder predecoder;
134 // Static data storage
135 TheISA::LargestRead dataReg;
137 StaticInstPtr curStaticInst;
138 StaticInstPtr curMacroStaticInst;
140 //This is the offset from the current pc that fetch should be performed at
142 //This flag says to stay at the current pc. This is useful for
143 //instructions which go beyond MachInst boundaries.
146 void checkForInterrupts();
147 Fault setupFetchRequest(Request *req);
150 void advancePC(Fault fault);
152 virtual void deallocateContext(int thread_num);
153 virtual void haltContext(int thread_num);
156 virtual void regStats();
157 virtual void resetStats();
159 // number of simulated instructions
161 Counter startNumInst;
162 Stats::Scalar<> numInsts;
164 virtual Counter totalInstructions() const
166 return numInst - startNumInst;
169 // number of simulated memory references
170 Stats::Scalar<> numMemRefs;
172 // number of simulated loads
174 Counter startNumLoad;
176 // number of idle cycles
177 Stats::Average<> notIdleFraction;
178 Stats::Formula idleFraction;
180 // number of cycles stalled for I-cache responses
181 Stats::Scalar<> icacheStallCycles;
182 Counter lastIcacheStall;
184 // number of cycles stalled for I-cache retries
185 Stats::Scalar<> icacheRetryCycles;
186 Counter lastIcacheRetry;
188 // number of cycles stalled for D-cache responses
189 Stats::Scalar<> dcacheStallCycles;
190 Counter lastDcacheStall;
192 // number of cycles stalled for D-cache retries
193 Stats::Scalar<> dcacheRetryCycles;
194 Counter lastDcacheRetry;
196 virtual void serialize(std::ostream &os);
197 virtual void unserialize(Checkpoint *cp, const std::string §ion);
199 // These functions are only used in CPU models that split
200 // effective address computation from the actual memory access.
201 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
202 Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n");
205 void prefetch(Addr addr, unsigned flags)
207 // need to do this...
210 void writeHint(Addr addr, int size, unsigned flags)
212 // need to do this...
215 Fault copySrcTranslate(Addr src);
217 Fault copy(Addr dest);
219 // The register accessor methods provide the index of the
220 // instruction's operand (e.g., 0 or 1), not the architectural
221 // register index, to simplify the implementation of register
222 // renaming. We find the architectural register index by indexing
223 // into the instruction's own operand index table. Note that a
224 // raw pointer to the StaticInst is provided instead of a
225 // ref-counted StaticInstPtr to redice overhead. This is fine as
226 // long as these methods don't copy the pointer into any long-term
227 // storage (which is pretty hard to imagine they would have reason
230 uint64_t readIntRegOperand(const StaticInst *si, int idx)
232 return thread->readIntReg(si->srcRegIdx(idx));
235 FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
237 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
238 return thread->readFloatReg(reg_idx, width);
241 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
243 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
244 return thread->readFloatReg(reg_idx);
247 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
250 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
251 return thread->readFloatRegBits(reg_idx, width);
254 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
256 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
257 return thread->readFloatRegBits(reg_idx);
260 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
262 thread->setIntReg(si->destRegIdx(idx), val);
265 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
268 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
269 thread->setFloatReg(reg_idx, val, width);
272 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
274 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
275 thread->setFloatReg(reg_idx, val);
278 void setFloatRegOperandBits(const StaticInst *si, int idx,
279 FloatRegBits val, int width)
281 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
282 thread->setFloatRegBits(reg_idx, val, width);
285 void setFloatRegOperandBits(const StaticInst *si, int idx,
288 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
289 thread->setFloatRegBits(reg_idx, val);
292 uint64_t readPC() { return thread->readPC(); }
293 uint64_t readNextPC() { return thread->readNextPC(); }
294 uint64_t readNextNPC() { return thread->readNextNPC(); }
296 void setPC(uint64_t val) { thread->setPC(val); }
297 void setNextPC(uint64_t val) { thread->setNextPC(val); }
298 void setNextNPC(uint64_t val) { thread->setNextNPC(val); }
300 MiscReg readMiscRegNoEffect(int misc_reg)
302 return thread->readMiscRegNoEffect(misc_reg);
305 MiscReg readMiscReg(int misc_reg)
307 return thread->readMiscReg(misc_reg);
310 void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
312 return thread->setMiscRegNoEffect(misc_reg, val);
315 void setMiscReg(int misc_reg, const MiscReg &val)
317 return thread->setMiscReg(misc_reg, val);
320 MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx)
322 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
323 return thread->readMiscRegNoEffect(reg_idx);
326 MiscReg readMiscRegOperand(const StaticInst *si, int idx)
328 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
329 return thread->readMiscReg(reg_idx);
332 void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val)
334 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
335 return thread->setMiscRegNoEffect(reg_idx, val);
338 void setMiscRegOperand(
339 const StaticInst *si, int idx, const MiscReg &val)
341 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
342 return thread->setMiscReg(reg_idx, val);
345 unsigned readStCondFailures() {
346 return thread->readStCondFailures();
349 void setStCondFailures(unsigned sc_failures) {
350 thread->setStCondFailures(sc_failures);
354 Fault hwrei() { return thread->hwrei(); }
355 void ev5_trap(Fault fault) { fault->invoke(tc); }
356 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
358 void syscall(int64_t callnum) { thread->syscall(callnum); }
361 bool misspeculating() { return thread->misspeculating(); }
362 ThreadContext *tcBase() { return tc; }
365 #endif // __CPU_SIMPLE_BASE_HH__