src/cpu/simple/base.hh

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  *          Dave Greene
  30  *          Nathan Binkert
  31  */
  32
  33 #ifndef __CPU_SIMPLE_BASE_HH__
  34 #define __CPU_SIMPLE_BASE_HH__
  35
  36 #include "arch/predecoder.hh"
  37 #include "base/statistics.hh"
  38 #include "config/full_system.hh"
  39 #include "cpu/base.hh"
  40 #include "cpu/simple_thread.hh"
  41 #include "cpu/pc_event.hh"
  42 #include "cpu/static_inst.hh"
  43 #include "mem/packet.hh"
  44 #include "mem/port.hh"
  45 #include "mem/request.hh"
  46 #include "sim/eventq.hh"
  47
  48 // forward declarations
  49 #if FULL_SYSTEM
  50 class Processor;
  51 namespace TheISA
  52 {
  53     class ITB;
  54     class DTB;
  55 }
  56 class MemObject;
  57
  58 #else
  59
  60 class Process;
  61
  62 #endif // FULL_SYSTEM
  63
  64 class RemoteGDB;
  65 class GDBListener;
  66
  67 namespace TheISA
  68 {
  69     class Predecoder;
  70 }
  71 class ThreadContext;
  72 class Checkpoint;
  73
  74 namespace Trace {
  75     class InstRecord;
  76 }
  77
  78
  79 class BaseSimpleCPU : public BaseCPU
  80 {
  81   protected:
  82     typedef TheISA::MiscReg MiscReg;
  83     typedef TheISA::FloatReg FloatReg;
  84     typedef TheISA::FloatRegBits FloatRegBits;
  85
  86   protected:
  87     Trace::InstRecord *traceData;
  88
  89   public:
  90     void post_interrupt(int int_num, int index);
  91
  92     void zero_fill_64(Addr addr) {
  93       static int warned = 0;
  94       if (!warned) {
  95         warn ("WH64 is not implemented");
  96         warned = 1;
  97       }
  98     };
  99
 100   public:
 101     struct Params : public BaseCPU::Params
 102     {
 103 #if FULL_SYSTEM
 104         TheISA::ITB *itb;
 105         TheISA::DTB *dtb;
 106 #else
 107         Process *process;
 108 #endif
 109     };
 110     BaseSimpleCPU(Params *params);
 111     virtual ~BaseSimpleCPU();
 112
 113   public:
 114     /** SimpleThread object, provides all the architectural state. */
 115     SimpleThread *thread;
 116
 117     /** ThreadContext object, provides an interface for external
 118      * objects to modify this thread's state.
 119      */
 120     ThreadContext *tc;
 121
 122 #if FULL_SYSTEM
 123     Addr dbg_vtophys(Addr addr);
 124
 125     bool interval_stats;
 126 #endif
 127
 128     // current instruction
 129     TheISA::MachInst inst;
 130
 131     // The predecoder
 132     TheISA::Predecoder predecoder;
 133
 134     StaticInstPtr curStaticInst;
 135     StaticInstPtr curMacroStaticInst;
 136
 137     //This is the offset from the current pc that fetch should be performed at
 138     Addr fetchOffset;
 139     //This flag says to stay at the current pc. This is useful for
 140     //instructions which go beyond MachInst boundaries.
 141     bool stayAtPC;
 142
 143     void checkForInterrupts();
 144     Fault setupFetchRequest(Request *req);
 145     void preExecute();
 146     void postExecute();
 147     void advancePC(Fault fault);
 148
 149     virtual void deallocateContext(int thread_num);
 150     virtual void haltContext(int thread_num);
 151
 152     // statistics
 153     virtual void regStats();
 154     virtual void resetStats();
 155
 156     // number of simulated instructions
 157     Counter numInst;
 158     Counter startNumInst;
 159     Stats::Scalar<> numInsts;
 160
 161     virtual Counter totalInstructions() const
 162     {
 163         return numInst - startNumInst;
 164     }
 165
 166     // Mask to align PCs to MachInst sized boundaries
 167     static const Addr PCMask = ~((Addr)sizeof(TheISA::MachInst) - 1);
 168
 169     // number of simulated memory references
 170     Stats::Scalar<> numMemRefs;
 171
 172     // number of simulated loads
 173     Counter numLoad;
 174     Counter startNumLoad;
 175
 176     // number of idle cycles
 177     Stats::Average<> notIdleFraction;
 178     Stats::Formula idleFraction;
 179
 180     // number of cycles stalled for I-cache responses
 181     Stats::Scalar<> icacheStallCycles;
 182     Counter lastIcacheStall;
 183
 184     // number of cycles stalled for I-cache retries
 185     Stats::Scalar<> icacheRetryCycles;
 186     Counter lastIcacheRetry;
 187
 188     // number of cycles stalled for D-cache responses
 189     Stats::Scalar<> dcacheStallCycles;
 190     Counter lastDcacheStall;
 191
 192     // number of cycles stalled for D-cache retries
 193     Stats::Scalar<> dcacheRetryCycles;
 194     Counter lastDcacheRetry;
 195
 196     virtual void serialize(std::ostream &os);
 197     virtual void unserialize(Checkpoint *cp, const std::string &section);
 198
 199     // These functions are only used in CPU models that split
 200     // effective address computation from the actual memory access.
 201     void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
 202     Addr getEA()        { panic("BaseSimpleCPU::getEA() not implemented\n");
 203         M5_DUMMY_RETURN}
 204
 205     void prefetch(Addr addr, unsigned flags)
 206     {
 207         // need to do this...
 208     }
 209
 210     void writeHint(Addr addr, int size, unsigned flags)
 211     {
 212         // need to do this...
 213     }
 214
 215
 216     Fault copySrcTranslate(Addr src);
 217
 218     Fault copy(Addr dest);
 219
 220     // The register accessor methods provide the index of the
 221     // instruction's operand (e.g., 0 or 1), not the architectural
 222     // register index, to simplify the implementation of register
 223     // renaming.  We find the architectural register index by indexing
 224     // into the instruction's own operand index table.  Note that a
 225     // raw pointer to the StaticInst is provided instead of a
 226     // ref-counted StaticInstPtr to redice overhead.  This is fine as
 227     // long as these methods don't copy the pointer into any long-term
 228     // storage (which is pretty hard to imagine they would have reason
 229     // to do).
 230
 231     uint64_t readIntRegOperand(const StaticInst *si, int idx)
 232     {
 233         return thread->readIntReg(si->srcRegIdx(idx));
 234     }
 235
 236     FloatReg readFloatRegOperand(const StaticInst *si, int idx, int width)
 237     {
 238         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
 239         return thread->readFloatReg(reg_idx, width);
 240     }
 241
 242     FloatReg readFloatRegOperand(const StaticInst *si, int idx)
 243     {
 244         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
 245         return thread->readFloatReg(reg_idx);
 246     }
 247
 248     FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx,
 249                                          int width)
 250     {
 251         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
 252         return thread->readFloatRegBits(reg_idx, width);
 253     }
 254
 255     FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
 256     {
 257         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
 258         return thread->readFloatRegBits(reg_idx);
 259     }
 260
 261     void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
 262     {
 263         thread->setIntReg(si->destRegIdx(idx), val);
 264     }
 265
 266     void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val,
 267                             int width)
 268     {
 269         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
 270         thread->setFloatReg(reg_idx, val, width);
 271     }
 272
 273     void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
 274     {
 275         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
 276         thread->setFloatReg(reg_idx, val);
 277     }
 278
 279     void setFloatRegOperandBits(const StaticInst *si, int idx,
 280                                 FloatRegBits val, int width)
 281     {
 282         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
 283         thread->setFloatRegBits(reg_idx, val, width);
 284     }
 285
 286     void setFloatRegOperandBits(const StaticInst *si, int idx,
 287                                 FloatRegBits val)
 288     {
 289         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
 290         thread->setFloatRegBits(reg_idx, val);
 291     }
 292
 293     uint64_t readPC() { return thread->readPC(); }
 294     uint64_t readNextPC() { return thread->readNextPC(); }
 295     uint64_t readNextNPC() { return thread->readNextNPC(); }
 296
 297     void setPC(uint64_t val) { thread->setPC(val); }
 298     void setNextPC(uint64_t val) { thread->setNextPC(val); }
 299     void setNextNPC(uint64_t val) { thread->setNextNPC(val); }
 300
 301     MiscReg readMiscRegNoEffect(int misc_reg)
 302     {
 303         return thread->readMiscRegNoEffect(misc_reg);
 304     }
 305
 306     MiscReg readMiscReg(int misc_reg)
 307     {
 308         return thread->readMiscReg(misc_reg);
 309     }
 310
 311     void setMiscRegNoEffect(int misc_reg, const MiscReg &val)
 312     {
 313         return thread->setMiscRegNoEffect(misc_reg, val);
 314     }
 315
 316     void setMiscReg(int misc_reg, const MiscReg &val)
 317     {
 318         return thread->setMiscReg(misc_reg, val);
 319     }
 320
 321     MiscReg readMiscRegOperandNoEffect(const StaticInst *si, int idx)
 322     {
 323         int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
 324         return thread->readMiscRegNoEffect(reg_idx);
 325     }
 326
 327     MiscReg readMiscRegOperand(const StaticInst *si, int idx)
 328     {
 329         int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
 330         return thread->readMiscReg(reg_idx);
 331     }
 332
 333     void setMiscRegOperandNoEffect(const StaticInst *si, int idx, const MiscReg &val)
 334     {
 335         int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
 336         return thread->setMiscRegNoEffect(reg_idx, val);
 337     }
 338
 339     void setMiscRegOperand(
 340             const StaticInst *si, int idx, const MiscReg &val)
 341     {
 342         int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
 343         return thread->setMiscReg(reg_idx, val);
 344     }
 345
 346     unsigned readStCondFailures() {
 347         return thread->readStCondFailures();
 348     }
 349
 350     void setStCondFailures(unsigned sc_failures) {
 351         thread->setStCondFailures(sc_failures);
 352     }
 353
 354      MiscReg readRegOtherThread(int regIdx, int tid = -1)
 355      {
 356         panic("Simple CPU models do not support multithreaded "
 357               "register access.\n");
 358      }
 359
 360      void setRegOtherThread(int regIdx, const MiscReg &val, int tid = -1)
 361      {
 362         panic("Simple CPU models do not support multithreaded "
 363               "register access.\n");
 364      }
 365
 366 #if FULL_SYSTEM
 367     Fault hwrei() { return thread->hwrei(); }
 368     void ev5_trap(Fault fault) { fault->invoke(tc); }
 369     bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
 370 #else
 371     void syscall(int64_t callnum) { thread->syscall(callnum); }
 372 #endif
 373
 374     bool misspeculating() { return thread->misspeculating(); }
 375     ThreadContext *tcBase() { return tc; }
 376 };
 377
 378 #endif // __CPU_SIMPLE_BASE_HH__