2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
33 #ifndef __CPU_SIMPLE_BASE_HH__
34 #define __CPU_SIMPLE_BASE_HH__
36 #include "arch/predecoder.hh"
37 #include "base/statistics.hh"
38 #include "config/the_isa.hh"
39 #include "cpu/base.hh"
40 #include "cpu/decode.hh"
41 #include "cpu/pc_event.hh"
42 #include "cpu/simple_thread.hh"
43 #include "cpu/static_inst.hh"
44 #include "mem/packet.hh"
45 #include "mem/port.hh"
46 #include "mem/request.hh"
47 #include "sim/eventq.hh"
48 #include "sim/full_system.hh"
49 #include "sim/system.hh"
51 // forward declarations
69 class BaseSimpleCPUParams;
72 class BaseSimpleCPU : public BaseCPU
75 typedef TheISA::MiscReg MiscReg;
76 typedef TheISA::FloatReg FloatReg;
77 typedef TheISA::FloatRegBits FloatRegBits;
80 Trace::InstRecord *traceData;
82 inline void checkPcEventQueue() {
83 Addr oldpc, pc = thread->instAddr();
86 system->pcEventQueue.service(tc);
87 pc = thread->instAddr();
88 } while (oldpc != pc);
94 void zero_fill_64(Addr addr) {
95 static int warned = 0;
97 warn ("WH64 is not implemented");
103 BaseSimpleCPU(BaseSimpleCPUParams *params);
104 virtual ~BaseSimpleCPU();
107 /** SimpleThread object, provides all the architectural state. */
108 SimpleThread *thread;
110 /** ThreadContext object, provides an interface for external
111 * objects to modify this thread's state.
135 Addr dbg_vtophys(Addr addr);
139 // current instruction
140 TheISA::MachInst inst;
143 TheISA::Predecoder predecoder;
145 StaticInstPtr curStaticInst;
146 StaticInstPtr curMacroStaticInst;
148 //This is the offset from the current pc that fetch should be performed at
150 //This flag says to stay at the current pc. This is useful for
151 //instructions which go beyond MachInst boundaries.
154 void checkForInterrupts();
155 void setupFetchRequest(Request *req);
158 void advancePC(Fault fault);
160 virtual void deallocateContext(int thread_num);
161 virtual void haltContext(int thread_num);
164 virtual void regStats();
165 virtual void resetStats();
167 // number of simulated instructions
169 Counter startNumInst;
170 Stats::Scalar numInsts;
176 system->totalNumInsts++;
177 thread->funcExeInst++;
180 virtual Counter totalInstructions() const
182 return numInst - startNumInst;
185 //number of integer alu accesses
186 Stats::Scalar numIntAluAccesses;
188 //number of float alu accesses
189 Stats::Scalar numFpAluAccesses;
191 //number of function calls/returns
192 Stats::Scalar numCallsReturns;
194 //conditional control instructions;
195 Stats::Scalar numCondCtrlInsts;
197 //number of int instructions
198 Stats::Scalar numIntInsts;
200 //number of float instructions
201 Stats::Scalar numFpInsts;
203 //number of integer register file accesses
204 Stats::Scalar numIntRegReads;
205 Stats::Scalar numIntRegWrites;
207 //number of float register file accesses
208 Stats::Scalar numFpRegReads;
209 Stats::Scalar numFpRegWrites;
211 // number of simulated memory references
212 Stats::Scalar numMemRefs;
213 Stats::Scalar numLoadInsts;
214 Stats::Scalar numStoreInsts;
216 // number of idle cycles
217 Stats::Formula numIdleCycles;
219 // number of busy cycles
220 Stats::Formula numBusyCycles;
222 // number of simulated loads
224 Counter startNumLoad;
226 // number of idle cycles
227 Stats::Average notIdleFraction;
228 Stats::Formula idleFraction;
230 // number of cycles stalled for I-cache responses
231 Stats::Scalar icacheStallCycles;
232 Counter lastIcacheStall;
234 // number of cycles stalled for I-cache retries
235 Stats::Scalar icacheRetryCycles;
236 Counter lastIcacheRetry;
238 // number of cycles stalled for D-cache responses
239 Stats::Scalar dcacheStallCycles;
240 Counter lastDcacheStall;
242 // number of cycles stalled for D-cache retries
243 Stats::Scalar dcacheRetryCycles;
244 Counter lastDcacheRetry;
246 virtual void serialize(std::ostream &os);
247 virtual void unserialize(Checkpoint *cp, const std::string §ion);
249 // These functions are only used in CPU models that split
250 // effective address computation from the actual memory access.
251 void setEA(Addr EA) { panic("BaseSimpleCPU::setEA() not implemented\n"); }
252 Addr getEA() { panic("BaseSimpleCPU::getEA() not implemented\n");
255 // The register accessor methods provide the index of the
256 // instruction's operand (e.g., 0 or 1), not the architectural
257 // register index, to simplify the implementation of register
258 // renaming. We find the architectural register index by indexing
259 // into the instruction's own operand index table. Note that a
260 // raw pointer to the StaticInst is provided instead of a
261 // ref-counted StaticInstPtr to redice overhead. This is fine as
262 // long as these methods don't copy the pointer into any long-term
263 // storage (which is pretty hard to imagine they would have reason
266 uint64_t readIntRegOperand(const StaticInst *si, int idx)
269 return thread->readIntReg(si->srcRegIdx(idx));
272 FloatReg readFloatRegOperand(const StaticInst *si, int idx)
275 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
276 return thread->readFloatReg(reg_idx);
279 FloatRegBits readFloatRegOperandBits(const StaticInst *si, int idx)
282 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
283 return thread->readFloatRegBits(reg_idx);
286 void setIntRegOperand(const StaticInst *si, int idx, uint64_t val)
289 thread->setIntReg(si->destRegIdx(idx), val);
292 void setFloatRegOperand(const StaticInst *si, int idx, FloatReg val)
295 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
296 thread->setFloatReg(reg_idx, val);
299 void setFloatRegOperandBits(const StaticInst *si, int idx,
303 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
304 thread->setFloatRegBits(reg_idx, val);
307 bool readPredicate() { return thread->readPredicate(); }
308 void setPredicate(bool val)
310 thread->setPredicate(val);
312 traceData->setPredicate(val);
315 TheISA::PCState pcState() { return thread->pcState(); }
316 void pcState(const TheISA::PCState &val) { thread->pcState(val); }
317 Addr instAddr() { return thread->instAddr(); }
318 Addr nextInstAddr() { return thread->nextInstAddr(); }
319 MicroPC microPC() { return thread->microPC(); }
321 MiscReg readMiscRegNoEffect(int misc_reg)
323 return thread->readMiscRegNoEffect(misc_reg);
326 MiscReg readMiscReg(int misc_reg)
329 return thread->readMiscReg(misc_reg);
332 void setMiscReg(int misc_reg, const MiscReg &val)
335 return thread->setMiscReg(misc_reg, val);
338 MiscReg readMiscRegOperand(const StaticInst *si, int idx)
341 int reg_idx = si->srcRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
342 return thread->readMiscReg(reg_idx);
345 void setMiscRegOperand(
346 const StaticInst *si, int idx, const MiscReg &val)
349 int reg_idx = si->destRegIdx(idx) - TheISA::Ctrl_Base_DepTag;
350 return thread->setMiscReg(reg_idx, val);
353 void demapPage(Addr vaddr, uint64_t asn)
355 thread->demapPage(vaddr, asn);
358 void demapInstPage(Addr vaddr, uint64_t asn)
360 thread->demapInstPage(vaddr, asn);
363 void demapDataPage(Addr vaddr, uint64_t asn)
365 thread->demapDataPage(vaddr, asn);
368 unsigned readStCondFailures() {
369 return thread->readStCondFailures();
372 void setStCondFailures(unsigned sc_failures) {
373 thread->setStCondFailures(sc_failures);
376 MiscReg readRegOtherThread(int regIdx, ThreadID tid = InvalidThreadID)
378 panic("Simple CPU models do not support multithreaded "
379 "register access.\n");
382 void setRegOtherThread(int regIdx, const MiscReg &val,
383 ThreadID tid = InvalidThreadID)
385 panic("Simple CPU models do not support multithreaded "
386 "register access.\n");
389 //Fault CacheOp(uint8_t Op, Addr EA);
391 Fault hwrei() { return thread->hwrei(); }
392 bool simPalCheck(int palFunc) { return thread->simPalCheck(palFunc); }
395 syscall(int64_t callnum)
398 panic("Syscall emulation isn't available in FS mode.\n");
400 thread->syscall(callnum);
403 bool misspeculating() { return thread->misspeculating(); }
404 ThreadContext *tcBase() { return tc; }
407 #endif // __CPU_SIMPLE_BASE_HH__