2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
31 #include "arch/utility.hh"
32 #include "cpu/exetrace.hh"
33 #include "cpu/simple/timing.hh"
34 #include "mem/packet_impl.hh"
35 #include "sim/builder.hh"
36 #include "sim/system.hh"
39 using namespace TheISA
;
42 TimingSimpleCPU::getPort(const std::string
&if_name
, int idx
)
44 if (if_name
== "dcache_port")
46 else if (if_name
== "icache_port")
49 panic("No Such Port\n");
53 TimingSimpleCPU::init()
57 for (int i
= 0; i
< threadContexts
.size(); ++i
) {
58 ThreadContext
*tc
= threadContexts
[i
];
60 // initialize CPU, including PC
61 TheISA::initCPU(tc
, tc
->readCpuId());
67 TimingSimpleCPU::CpuPort::recvAtomic(Packet
*pkt
)
69 panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
74 TimingSimpleCPU::CpuPort::recvFunctional(Packet
*pkt
)
76 panic("TimingSimpleCPU doesn't expect recvFunctional callback!");
80 TimingSimpleCPU::CpuPort::recvStatusChange(Status status
)
82 if (status
== RangeChange
)
85 panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
90 TimingSimpleCPU::CpuPort::TickEvent::schedule(Packet
*_pkt
, Tick t
)
96 TimingSimpleCPU::TimingSimpleCPU(Params
*p
)
97 : BaseSimpleCPU(p
), icachePort(this, p
->clock
), dcachePort(this, p
->clock
)
100 ifetch_pkt
= dcache_pkt
= NULL
;
103 changeState(SimObject::Running
);
107 TimingSimpleCPU::~TimingSimpleCPU()
112 TimingSimpleCPU::serialize(ostream
&os
)
114 SimObject::State so_state
= SimObject::getState();
115 SERIALIZE_ENUM(so_state
);
116 BaseSimpleCPU::serialize(os
);
120 TimingSimpleCPU::unserialize(Checkpoint
*cp
, const string
§ion
)
122 SimObject::State so_state
;
123 UNSERIALIZE_ENUM(so_state
);
124 BaseSimpleCPU::unserialize(cp
, section
);
128 TimingSimpleCPU::drain(Event
*drain_event
)
130 // TimingSimpleCPU is ready to drain if it's not waiting for
131 // an access to complete.
132 if (status() == Idle
|| status() == Running
|| status() == SwitchedOut
) {
133 changeState(SimObject::Drained
);
136 changeState(SimObject::Draining
);
137 drainEvent
= drain_event
;
143 TimingSimpleCPU::resume()
145 if (_status
!= SwitchedOut
&& _status
!= Idle
) {
146 // Delete the old event if it existed.
148 if (fetchEvent
->scheduled())
149 fetchEvent
->deschedule();
155 new EventWrapper
<TimingSimpleCPU
, &TimingSimpleCPU::fetch
>(this, false);
156 fetchEvent
->schedule(curTick
);
159 assert(system
->getMemoryMode() == System::Timing
);
160 changeState(SimObject::Running
);
164 TimingSimpleCPU::switchOut()
166 assert(status() == Running
|| status() == Idle
);
167 _status
= SwitchedOut
;
169 // If we've been scheduled to resume but are then told to switch out,
170 // we'll need to cancel it.
171 if (fetchEvent
&& fetchEvent
->scheduled())
172 fetchEvent
->deschedule();
177 TimingSimpleCPU::takeOverFrom(BaseCPU
*oldCPU
)
179 BaseCPU::takeOverFrom(oldCPU
);
181 // if any of this CPU's ThreadContexts are active, mark the CPU as
182 // running and schedule its tick event.
183 for (int i
= 0; i
< threadContexts
.size(); ++i
) {
184 ThreadContext
*tc
= threadContexts
[i
];
185 if (tc
->status() == ThreadContext::Active
&& _status
!= Running
) {
194 TimingSimpleCPU::activateContext(int thread_num
, int delay
)
196 assert(thread_num
== 0);
199 assert(_status
== Idle
);
203 // kick things off by initiating the fetch of the next instruction
205 new EventWrapper
<TimingSimpleCPU
, &TimingSimpleCPU::fetch
>(this, false);
206 fetchEvent
->schedule(curTick
+ cycles(delay
));
211 TimingSimpleCPU::suspendContext(int thread_num
)
213 assert(thread_num
== 0);
216 assert(_status
== Running
);
218 // just change status to Idle... if status != Running,
219 // completeInst() will not initiate fetch of next instruction.
228 TimingSimpleCPU::read(Addr addr
, T
&data
, unsigned flags
)
230 // need to fill in CPU & thread IDs here
231 Request
*data_read_req
= new Request();
232 data_read_req
->setThreadContext(0,0); //Need CPU/Thread IDS HERE
233 data_read_req
->setVirt(0, addr
, sizeof(T
), flags
, thread
->readPC());
236 traceData
->setAddr(data_read_req
->getVaddr());
239 // translate to physical address
240 Fault fault
= thread
->translateDataReadReq(data_read_req
);
242 // Now do the access.
243 if (fault
== NoFault
) {
244 Packet
*data_read_pkt
=
245 new Packet(data_read_req
, Packet::ReadReq
, Packet::Broadcast
);
246 data_read_pkt
->dataDynamic
<T
>(new T
);
248 if (!dcachePort
.sendTiming(data_read_pkt
)) {
249 _status
= DcacheRetry
;
250 dcache_pkt
= data_read_pkt
;
252 _status
= DcacheWaitResponse
;
257 // This will need a new way to tell if it has a dcache attached.
258 if (data_read_req
->getFlags() & UNCACHEABLE
)
259 recordEvent("Uncached Read");
264 #ifndef DOXYGEN_SHOULD_SKIP_THIS
268 TimingSimpleCPU::read(Addr addr
, uint64_t &data
, unsigned flags
);
272 TimingSimpleCPU::read(Addr addr
, uint32_t &data
, unsigned flags
);
276 TimingSimpleCPU::read(Addr addr
, uint16_t &data
, unsigned flags
);
280 TimingSimpleCPU::read(Addr addr
, uint8_t &data
, unsigned flags
);
282 #endif //DOXYGEN_SHOULD_SKIP_THIS
286 TimingSimpleCPU::read(Addr addr
, double &data
, unsigned flags
)
288 return read(addr
, *(uint64_t*)&data
, flags
);
293 TimingSimpleCPU::read(Addr addr
, float &data
, unsigned flags
)
295 return read(addr
, *(uint32_t*)&data
, flags
);
301 TimingSimpleCPU::read(Addr addr
, int32_t &data
, unsigned flags
)
303 return read(addr
, (uint32_t&)data
, flags
);
309 TimingSimpleCPU::write(T data
, Addr addr
, unsigned flags
, uint64_t *res
)
311 // need to fill in CPU & thread IDs here
312 Request
*data_write_req
= new Request();
313 data_write_req
->setThreadContext(0,0); //Need CPU/Thread IDS HERE
314 data_write_req
->setVirt(0, addr
, sizeof(T
), flags
, thread
->readPC());
316 // translate to physical address
317 Fault fault
= thread
->translateDataWriteReq(data_write_req
);
318 // Now do the access.
319 if (fault
== NoFault
) {
320 Packet
*data_write_pkt
=
321 new Packet(data_write_req
, Packet::WriteReq
, Packet::Broadcast
);
322 data_write_pkt
->allocate();
323 data_write_pkt
->set(data
);
325 if (!dcachePort
.sendTiming(data_write_pkt
)) {
326 _status
= DcacheRetry
;
327 dcache_pkt
= data_write_pkt
;
329 _status
= DcacheWaitResponse
;
334 // This will need a new way to tell if it's hooked up to a cache or not.
335 if (data_write_req
->getFlags() & UNCACHEABLE
)
336 recordEvent("Uncached Write");
338 // If the write needs to have a fault on the access, consider calling
339 // changeStatus() and changing it to "bad addr write" or something.
344 #ifndef DOXYGEN_SHOULD_SKIP_THIS
347 TimingSimpleCPU::write(uint64_t data
, Addr addr
,
348 unsigned flags
, uint64_t *res
);
352 TimingSimpleCPU::write(uint32_t data
, Addr addr
,
353 unsigned flags
, uint64_t *res
);
357 TimingSimpleCPU::write(uint16_t data
, Addr addr
,
358 unsigned flags
, uint64_t *res
);
362 TimingSimpleCPU::write(uint8_t data
, Addr addr
,
363 unsigned flags
, uint64_t *res
);
365 #endif //DOXYGEN_SHOULD_SKIP_THIS
369 TimingSimpleCPU::write(double data
, Addr addr
, unsigned flags
, uint64_t *res
)
371 return write(*(uint64_t*)&data
, addr
, flags
, res
);
376 TimingSimpleCPU::write(float data
, Addr addr
, unsigned flags
, uint64_t *res
)
378 return write(*(uint32_t*)&data
, addr
, flags
, res
);
384 TimingSimpleCPU::write(int32_t data
, Addr addr
, unsigned flags
, uint64_t *res
)
386 return write((uint32_t)data
, addr
, flags
, res
);
391 TimingSimpleCPU::fetch()
393 checkForInterrupts();
395 // need to fill in CPU & thread IDs here
396 Request
*ifetch_req
= new Request();
397 ifetch_req
->setThreadContext(0,0); //Need CPU/Thread IDS HERE
398 Fault fault
= setupFetchRequest(ifetch_req
);
400 ifetch_pkt
= new Packet(ifetch_req
, Packet::ReadReq
, Packet::Broadcast
);
401 ifetch_pkt
->dataStatic(&inst
);
403 if (fault
== NoFault
) {
404 if (!icachePort
.sendTiming(ifetch_pkt
)) {
405 // Need to wait for retry
406 _status
= IcacheRetry
;
408 // Need to wait for cache to respond
409 _status
= IcacheWaitResponse
;
410 // ownership of packet transferred to memory system
414 // fetch fault: advance directly to next instruction (fault handler)
421 TimingSimpleCPU::advanceInst(Fault fault
)
425 if (_status
== Running
) {
426 // kick off fetch of next instruction... callback from icache
427 // response will cause that instruction to be executed,
428 // keeping the CPU running.
435 TimingSimpleCPU::completeIfetch(Packet
*pkt
)
437 // received a response from the icache: execute the received
439 assert(pkt
->result
== Packet::Success
);
440 assert(_status
== IcacheWaitResponse
);
447 if (getState() == SimObject::Draining
) {
453 if (curStaticInst
->isMemRef() && !curStaticInst
->isDataPrefetch()) {
454 // load or store: just send to dcache
455 Fault fault
= curStaticInst
->initiateAcc(this, traceData
);
456 if (fault
== NoFault
) {
457 // successfully initiated access: instruction will
458 // complete in dcache response callback
459 assert(_status
== DcacheWaitResponse
);
461 // fault: complete now to invoke fault handler
466 // non-memory instruction: execute completely now
467 Fault fault
= curStaticInst
->execute(this, traceData
);
474 TimingSimpleCPU::IcachePort::ITickEvent::process()
476 cpu
->completeIfetch(pkt
);
480 TimingSimpleCPU::IcachePort::recvTiming(Packet
*pkt
)
482 // These next few lines could be replaced with something faster
483 // who knows what though
484 Tick time
= pkt
->req
->getTime();
485 while (time
< curTick
)
489 cpu
->completeIfetch(pkt
);
491 tickEvent
.schedule(pkt
, time
);
497 TimingSimpleCPU::IcachePort::recvRetry()
499 // we shouldn't get a retry unless we have a packet that we're
500 // waiting to transmit
501 assert(cpu
->ifetch_pkt
!= NULL
);
502 assert(cpu
->_status
== IcacheRetry
);
503 Packet
*tmp
= cpu
->ifetch_pkt
;
504 if (sendTiming(tmp
)) {
505 cpu
->_status
= IcacheWaitResponse
;
506 cpu
->ifetch_pkt
= NULL
;
511 TimingSimpleCPU::completeDataAccess(Packet
*pkt
)
513 // received a response from the dcache: complete the load or store
515 assert(pkt
->result
== Packet::Success
);
516 assert(_status
== DcacheWaitResponse
);
519 if (getState() == SimObject::Draining
) {
528 Fault fault
= curStaticInst
->completeAcc(pkt
, this, traceData
);
539 TimingSimpleCPU::completeDrain()
541 DPRINTF(Config
, "Done draining\n");
542 changeState(SimObject::Drained
);
543 drainEvent
->process();
547 TimingSimpleCPU::DcachePort::recvTiming(Packet
*pkt
)
549 Tick time
= pkt
->req
->getTime();
550 while (time
< curTick
)
554 cpu
->completeDataAccess(pkt
);
556 tickEvent
.schedule(pkt
, time
);
562 TimingSimpleCPU::DcachePort::DTickEvent::process()
564 cpu
->completeDataAccess(pkt
);
568 TimingSimpleCPU::DcachePort::recvRetry()
570 // we shouldn't get a retry unless we have a packet that we're
571 // waiting to transmit
572 assert(cpu
->dcache_pkt
!= NULL
);
573 assert(cpu
->_status
== DcacheRetry
);
574 Packet
*tmp
= cpu
->dcache_pkt
;
575 if (sendTiming(tmp
)) {
576 cpu
->_status
= DcacheWaitResponse
;
577 cpu
->dcache_pkt
= NULL
;
582 ////////////////////////////////////////////////////////////////////////
584 // TimingSimpleCPU Simulation Object
586 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU
)
588 Param
<Counter
> max_insts_any_thread
;
589 Param
<Counter
> max_insts_all_threads
;
590 Param
<Counter
> max_loads_any_thread
;
591 Param
<Counter
> max_loads_all_threads
;
592 Param
<Tick
> progress_interval
;
593 SimObjectParam
<MemObject
*> mem
;
594 SimObjectParam
<System
*> system
;
597 SimObjectParam
<AlphaITB
*> itb
;
598 SimObjectParam
<AlphaDTB
*> dtb
;
602 SimObjectParam
<Process
*> workload
;
603 #endif // FULL_SYSTEM
607 Param
<bool> defer_registration
;
609 Param
<bool> function_trace
;
610 Param
<Tick
> function_trace_start
;
611 Param
<bool> simulate_stalls
;
613 END_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU
)
615 BEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU
)
617 INIT_PARAM(max_insts_any_thread
,
618 "terminate when any thread reaches this inst count"),
619 INIT_PARAM(max_insts_all_threads
,
620 "terminate when all threads have reached this inst count"),
621 INIT_PARAM(max_loads_any_thread
,
622 "terminate when any thread reaches this load count"),
623 INIT_PARAM(max_loads_all_threads
,
624 "terminate when all threads have reached this load count"),
625 INIT_PARAM(progress_interval
, "Progress interval"),
626 INIT_PARAM(mem
, "memory"),
627 INIT_PARAM(system
, "system object"),
630 INIT_PARAM(itb
, "Instruction TLB"),
631 INIT_PARAM(dtb
, "Data TLB"),
632 INIT_PARAM(cpu_id
, "processor ID"),
633 INIT_PARAM(profile
, ""),
635 INIT_PARAM(workload
, "processes to run"),
636 #endif // FULL_SYSTEM
638 INIT_PARAM(clock
, "clock speed"),
639 INIT_PARAM(defer_registration
, "defer system registration (for sampling)"),
640 INIT_PARAM(width
, "cpu width"),
641 INIT_PARAM(function_trace
, "Enable function trace"),
642 INIT_PARAM(function_trace_start
, "Cycle to start function trace"),
643 INIT_PARAM(simulate_stalls
, "Simulate cache stall cycles")
645 END_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU
)
648 CREATE_SIM_OBJECT(TimingSimpleCPU
)
650 TimingSimpleCPU::Params
*params
= new TimingSimpleCPU::Params();
651 params
->name
= getInstanceName();
652 params
->numberOfThreads
= 1;
653 params
->max_insts_any_thread
= max_insts_any_thread
;
654 params
->max_insts_all_threads
= max_insts_all_threads
;
655 params
->max_loads_any_thread
= max_loads_any_thread
;
656 params
->max_loads_all_threads
= max_loads_all_threads
;
657 params
->progress_interval
= progress_interval
;
658 params
->deferRegistration
= defer_registration
;
659 params
->clock
= clock
;
660 params
->functionTrace
= function_trace
;
661 params
->functionTraceStart
= function_trace_start
;
663 params
->system
= system
;
668 params
->cpu_id
= cpu_id
;
669 params
->profile
= profile
;
671 params
->process
= workload
;
674 TimingSimpleCPU
*cpu
= new TimingSimpleCPU(params
);
678 REGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU
)