src/cpu/simple/timing.cc

   1 /*
   2  * Copyright 2014 Google, Inc.
   3  * Copyright (c) 2010-2013,2015 ARM Limited
   4  * All rights reserved
   5  *
   6  * The license below extends only to copyright in the software and shall
   7  * not be construed as granting a license to any other intellectual
   8  * property including but not limited to intellectual property relating
   9  * to a hardware implementation of the functionality of the software
  10  * licensed hereunder.  You may use the software subject to the license
  11  * terms below provided that you ensure that this notice is replicated
  12  * unmodified and in its entirety in all distributions of the software,
  13  * modified or unmodified, in source code or in binary form.
  14  *
  15  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * Authors: Steve Reinhardt
  42  */
  43
  44 #include "cpu/simple/timing.hh"
  45
  46 #include "arch/locked_mem.hh"
  47 #include "arch/mmapped_ipr.hh"
  48 #include "arch/utility.hh"
  49 #include "base/bigint.hh"
  50 #include "config/the_isa.hh"
  51 #include "cpu/exetrace.hh"
  52 #include "debug/Config.hh"
  53 #include "debug/Drain.hh"
  54 #include "debug/ExecFaulting.hh"
  55 #include "debug/Mwait.hh"
  56 #include "debug/SimpleCPU.hh"
  57 #include "mem/packet.hh"
  58 #include "mem/packet_access.hh"
  59 #include "params/TimingSimpleCPU.hh"
  60 #include "sim/faults.hh"
  61 #include "sim/full_system.hh"
  62 #include "sim/system.hh"
  63
  64 using namespace std;
  65 using namespace TheISA;
  66
  67 void
  68 TimingSimpleCPU::init()
  69 {
  70     BaseSimpleCPU::init();
  71 }
  72
  73 void
  74 TimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
  75 {
  76     pkt = _pkt;
  77     cpu->schedule(this, t);
  78 }
  79
  80 TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p)
  81     : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this),
  82       dcachePort(this), ifetch_pkt(NULL), dcache_pkt(NULL), previousCycle(0),
  83       fetchEvent(this)
  84 {
  85     _status = Idle;
  86 }
  87
  88
  89
  90 TimingSimpleCPU::~TimingSimpleCPU()
  91 {
  92 }
  93
  94 DrainState
  95 TimingSimpleCPU::drain()
  96 {
  97     if (switchedOut())
  98         return DrainState::Drained;
  99
 100     if (_status == Idle ||
 101         (_status == BaseSimpleCPU::Running && isDrained())) {
 102         DPRINTF(Drain, "No need to drain.\n");
 103         activeThreads.clear();
 104         return DrainState::Drained;
 105     } else {
 106         DPRINTF(Drain, "Requesting drain.\n");
 107
 108         // The fetch event can become descheduled if a drain didn't
 109         // succeed on the first attempt. We need to reschedule it if
 110         // the CPU is waiting for a microcode routine to complete.
 111         if (_status == BaseSimpleCPU::Running && !fetchEvent.scheduled())
 112             schedule(fetchEvent, clockEdge());
 113
 114         return DrainState::Draining;
 115     }
 116 }
 117
 118 void
 119 TimingSimpleCPU::drainResume()
 120 {
 121     assert(!fetchEvent.scheduled());
 122     if (switchedOut())
 123         return;
 124
 125     DPRINTF(SimpleCPU, "Resume\n");
 126     verifyMemoryMode();
 127
 128     assert(!threadContexts.empty());
 129
 130     _status = BaseSimpleCPU::Idle;
 131
 132     for (ThreadID tid = 0; tid < numThreads; tid++) {
 133         if (threadInfo[tid]->thread->status() == ThreadContext::Active) {
 134             threadInfo[tid]->notIdleFraction = 1;
 135
 136             activeThreads.push_back(tid);
 137
 138             _status = BaseSimpleCPU::Running;
 139
 140             // Fetch if any threads active
 141             if (!fetchEvent.scheduled()) {
 142                 schedule(fetchEvent, nextCycle());
 143             }
 144         } else {
 145             threadInfo[tid]->notIdleFraction = 0;
 146         }
 147     }
 148
 149     system->totalNumInsts = 0;
 150 }
 151
 152 bool
 153 TimingSimpleCPU::tryCompleteDrain()
 154 {
 155     if (drainState() != DrainState::Draining)
 156         return false;
 157
 158     DPRINTF(Drain, "tryCompleteDrain.\n");
 159     if (!isDrained())
 160         return false;
 161
 162     DPRINTF(Drain, "CPU done draining, processing drain event\n");
 163     signalDrainDone();
 164
 165     return true;
 166 }
 167
 168 void
 169 TimingSimpleCPU::switchOut()
 170 {
 171     SimpleExecContext& t_info = *threadInfo[curThread];
 172     M5_VAR_USED SimpleThread* thread = t_info.thread;
 173
 174     BaseSimpleCPU::switchOut();
 175
 176     assert(!fetchEvent.scheduled());
 177     assert(_status == BaseSimpleCPU::Running || _status == Idle);
 178     assert(!t_info.stayAtPC);
 179     assert(thread->microPC() == 0);
 180
 181     updateCycleCounts();
 182 }
 183
 184
 185 void
 186 TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
 187 {
 188     BaseSimpleCPU::takeOverFrom(oldCPU);
 189
 190     previousCycle = curCycle();
 191 }
 192
 193 void
 194 TimingSimpleCPU::verifyMemoryMode() const
 195 {
 196     if (!system->isTimingMode()) {
 197         fatal("The timing CPU requires the memory system to be in "
 198               "'timing' mode.\n");
 199     }
 200 }
 201
 202 void
 203 TimingSimpleCPU::activateContext(ThreadID thread_num)
 204 {
 205     DPRINTF(SimpleCPU, "ActivateContext %d\n", thread_num);
 206
 207     assert(thread_num < numThreads);
 208
 209     threadInfo[thread_num]->notIdleFraction = 1;
 210     if (_status == BaseSimpleCPU::Idle)
 211         _status = BaseSimpleCPU::Running;
 212
 213     // kick things off by initiating the fetch of the next instruction
 214     if (!fetchEvent.scheduled())
 215         schedule(fetchEvent, clockEdge(Cycles(0)));
 216
 217     if (std::find(activeThreads.begin(), activeThreads.end(), thread_num)
 218          == activeThreads.end()) {
 219         activeThreads.push_back(thread_num);
 220     }
 221
 222     BaseCPU::activateContext(thread_num);
 223 }
 224
 225
 226 void
 227 TimingSimpleCPU::suspendContext(ThreadID thread_num)
 228 {
 229     DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
 230
 231     assert(thread_num < numThreads);
 232     activeThreads.remove(thread_num);
 233
 234     if (_status == Idle)
 235         return;
 236
 237     assert(_status == BaseSimpleCPU::Running);
 238
 239     threadInfo[thread_num]->notIdleFraction = 0;
 240
 241     if (activeThreads.empty()) {
 242         _status = Idle;
 243
 244         if (fetchEvent.scheduled()) {
 245             deschedule(fetchEvent);
 246         }
 247     }
 248
 249     BaseCPU::suspendContext(thread_num);
 250 }
 251
 252 bool
 253 TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
 254 {
 255     SimpleExecContext &t_info = *threadInfo[curThread];
 256     SimpleThread* thread = t_info.thread;
 257
 258     RequestPtr req = pkt->req;
 259
 260     // We're about the issues a locked load, so tell the monitor
 261     // to start caring about this address
 262     if (pkt->isRead() && pkt->req->isLLSC()) {
 263         TheISA::handleLockedRead(thread, pkt->req);
 264     }
 265     if (req->isMmappedIpr()) {
 266         Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt);
 267         new IprEvent(pkt, this, clockEdge(delay));
 268         _status = DcacheWaitResponse;
 269         dcache_pkt = NULL;
 270     } else if (!dcachePort.sendTimingReq(pkt)) {
 271         _status = DcacheRetry;
 272         dcache_pkt = pkt;
 273     } else {
 274         _status = DcacheWaitResponse;
 275         // memory system takes ownership of packet
 276         dcache_pkt = NULL;
 277     }
 278     return dcache_pkt == NULL;
 279 }
 280
 281 void
 282 TimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res,
 283                           bool read)
 284 {
 285     SimpleExecContext &t_info = *threadInfo[curThread];
 286     SimpleThread* thread = t_info.thread;
 287
 288     PacketPtr pkt = buildPacket(req, read);
 289     pkt->dataDynamic<uint8_t>(data);
 290     if (req->getFlags().isSet(Request::NO_ACCESS)) {
 291         assert(!dcache_pkt);
 292         pkt->makeResponse();
 293         completeDataAccess(pkt);
 294     } else if (read) {
 295         handleReadPacket(pkt);
 296     } else {
 297         bool do_access = true;  // flag to suppress cache access
 298
 299         if (req->isLLSC()) {
 300             do_access = TheISA::handleLockedWrite(thread, req, dcachePort.cacheBlockMask);
 301         } else if (req->isCondSwap()) {
 302             assert(res);
 303             req->setExtraData(*res);
 304         }
 305
 306         if (do_access) {
 307             dcache_pkt = pkt;
 308             handleWritePacket();
 309             threadSnoop(pkt, curThread);
 310         } else {
 311             _status = DcacheWaitResponse;
 312             completeDataAccess(pkt);
 313         }
 314     }
 315 }
 316
 317 void
 318 TimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2,
 319                                RequestPtr req, uint8_t *data, bool read)
 320 {
 321     PacketPtr pkt1, pkt2;
 322     buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read);
 323     if (req->getFlags().isSet(Request::NO_ACCESS)) {
 324         assert(!dcache_pkt);
 325         pkt1->makeResponse();
 326         completeDataAccess(pkt1);
 327     } else if (read) {
 328         SplitFragmentSenderState * send_state =
 329             dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
 330         if (handleReadPacket(pkt1)) {
 331             send_state->clearFromParent();
 332             send_state = dynamic_cast<SplitFragmentSenderState *>(
 333                     pkt2->senderState);
 334             if (handleReadPacket(pkt2)) {
 335                 send_state->clearFromParent();
 336             }
 337         }
 338     } else {
 339         dcache_pkt = pkt1;
 340         SplitFragmentSenderState * send_state =
 341             dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
 342         if (handleWritePacket()) {
 343             send_state->clearFromParent();
 344             dcache_pkt = pkt2;
 345             send_state = dynamic_cast<SplitFragmentSenderState *>(
 346                     pkt2->senderState);
 347             if (handleWritePacket()) {
 348                 send_state->clearFromParent();
 349             }
 350         }
 351     }
 352 }
 353
 354 void
 355 TimingSimpleCPU::translationFault(const Fault &fault)
 356 {
 357     // fault may be NoFault in cases where a fault is suppressed,
 358     // for instance prefetches.
 359     updateCycleCounts();
 360
 361     if (traceData) {
 362         // Since there was a fault, we shouldn't trace this instruction.
 363         delete traceData;
 364         traceData = NULL;
 365     }
 366
 367     postExecute();
 368
 369     advanceInst(fault);
 370 }
 371
 372 PacketPtr
 373 TimingSimpleCPU::buildPacket(RequestPtr req, bool read)
 374 {
 375     return read ? Packet::createRead(req) : Packet::createWrite(req);
 376 }
 377
 378 void
 379 TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
 380         RequestPtr req1, RequestPtr req2, RequestPtr req,
 381         uint8_t *data, bool read)
 382 {
 383     pkt1 = pkt2 = NULL;
 384
 385     assert(!req1->isMmappedIpr() && !req2->isMmappedIpr());
 386
 387     if (req->getFlags().isSet(Request::NO_ACCESS)) {
 388         pkt1 = buildPacket(req, read);
 389         return;
 390     }
 391
 392     pkt1 = buildPacket(req1, read);
 393     pkt2 = buildPacket(req2, read);
 394
 395     PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand());
 396
 397     pkt->dataDynamic<uint8_t>(data);
 398     pkt1->dataStatic<uint8_t>(data);
 399     pkt2->dataStatic<uint8_t>(data + req1->getSize());
 400
 401     SplitMainSenderState * main_send_state = new SplitMainSenderState;
 402     pkt->senderState = main_send_state;
 403     main_send_state->fragments[0] = pkt1;
 404     main_send_state->fragments[1] = pkt2;
 405     main_send_state->outstanding = 2;
 406     pkt1->senderState = new SplitFragmentSenderState(pkt, 0);
 407     pkt2->senderState = new SplitFragmentSenderState(pkt, 1);
 408 }
 409
 410 Fault
 411 TimingSimpleCPU::readMem(Addr addr, uint8_t *data,
 412                          unsigned size, Request::Flags flags)
 413 {
 414     panic("readMem() is for atomic accesses, and should "
 415           "never be called on TimingSimpleCPU.\n");
 416 }
 417
 418 Fault
 419 TimingSimpleCPU::initiateMemRead(Addr addr, unsigned size,
 420                                  Request::Flags flags)
 421 {
 422     SimpleExecContext &t_info = *threadInfo[curThread];
 423     SimpleThread* thread = t_info.thread;
 424
 425     Fault fault;
 426     const int asid = 0;
 427     const Addr pc = thread->instAddr();
 428     unsigned block_size = cacheLineSize();
 429     BaseTLB::Mode mode = BaseTLB::Read;
 430
 431     if (traceData)
 432         traceData->setMem(addr, size, flags);
 433
 434     RequestPtr req = new Request(asid, addr, size, flags, dataMasterId(), pc,
 435                                  thread->contextId());
 436
 437     req->taskId(taskId());
 438
 439     Addr split_addr = roundDown(addr + size - 1, block_size);
 440     assert(split_addr <= addr || split_addr - addr < block_size);
 441
 442     _status = DTBWaitResponse;
 443     if (split_addr > addr) {
 444         RequestPtr req1, req2;
 445         assert(!req->isLLSC() && !req->isSwap());
 446         req->splitOnVaddr(split_addr, req1, req2);
 447
 448         WholeTranslationState *state =
 449             new WholeTranslationState(req, req1, req2, new uint8_t[size],
 450                                       NULL, mode);
 451         DataTranslation<TimingSimpleCPU *> *trans1 =
 452             new DataTranslation<TimingSimpleCPU *>(this, state, 0);
 453         DataTranslation<TimingSimpleCPU *> *trans2 =
 454             new DataTranslation<TimingSimpleCPU *>(this, state, 1);
 455
 456         thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode);
 457         thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode);
 458     } else {
 459         WholeTranslationState *state =
 460             new WholeTranslationState(req, new uint8_t[size], NULL, mode);
 461         DataTranslation<TimingSimpleCPU *> *translation
 462             = new DataTranslation<TimingSimpleCPU *>(this, state);
 463         thread->dtb->translateTiming(req, thread->getTC(), translation, mode);
 464     }
 465
 466     return NoFault;
 467 }
 468
 469 bool
 470 TimingSimpleCPU::handleWritePacket()
 471 {
 472     SimpleExecContext &t_info = *threadInfo[curThread];
 473     SimpleThread* thread = t_info.thread;
 474
 475     RequestPtr req = dcache_pkt->req;
 476     if (req->isMmappedIpr()) {
 477         Cycles delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
 478         new IprEvent(dcache_pkt, this, clockEdge(delay));
 479         _status = DcacheWaitResponse;
 480         dcache_pkt = NULL;
 481     } else if (!dcachePort.sendTimingReq(dcache_pkt)) {
 482         _status = DcacheRetry;
 483     } else {
 484         _status = DcacheWaitResponse;
 485         // memory system takes ownership of packet
 486         dcache_pkt = NULL;
 487     }
 488     return dcache_pkt == NULL;
 489 }
 490
 491 Fault
 492 TimingSimpleCPU::writeMem(uint8_t *data, unsigned size,
 493                           Addr addr, Request::Flags flags, uint64_t *res)
 494 {
 495     SimpleExecContext &t_info = *threadInfo[curThread];
 496     SimpleThread* thread = t_info.thread;
 497
 498     uint8_t *newData = new uint8_t[size];
 499     const int asid = 0;
 500     const Addr pc = thread->instAddr();
 501     unsigned block_size = cacheLineSize();
 502     BaseTLB::Mode mode = BaseTLB::Write;
 503
 504     if (data == NULL) {
 505         assert(flags & Request::CACHE_BLOCK_ZERO);
 506         // This must be a cache block cleaning request
 507         memset(newData, 0, size);
 508     } else {
 509         memcpy(newData, data, size);
 510     }
 511
 512     if (traceData)
 513         traceData->setMem(addr, size, flags);
 514
 515     RequestPtr req = new Request(asid, addr, size, flags, dataMasterId(), pc,
 516                                  thread->contextId());
 517
 518     req->taskId(taskId());
 519
 520     Addr split_addr = roundDown(addr + size - 1, block_size);
 521     assert(split_addr <= addr || split_addr - addr < block_size);
 522
 523     _status = DTBWaitResponse;
 524     if (split_addr > addr) {
 525         RequestPtr req1, req2;
 526         assert(!req->isLLSC() && !req->isSwap());
 527         req->splitOnVaddr(split_addr, req1, req2);
 528
 529         WholeTranslationState *state =
 530             new WholeTranslationState(req, req1, req2, newData, res, mode);
 531         DataTranslation<TimingSimpleCPU *> *trans1 =
 532             new DataTranslation<TimingSimpleCPU *>(this, state, 0);
 533         DataTranslation<TimingSimpleCPU *> *trans2 =
 534             new DataTranslation<TimingSimpleCPU *>(this, state, 1);
 535
 536         thread->dtb->translateTiming(req1, thread->getTC(), trans1, mode);
 537         thread->dtb->translateTiming(req2, thread->getTC(), trans2, mode);
 538     } else {
 539         WholeTranslationState *state =
 540             new WholeTranslationState(req, newData, res, mode);
 541         DataTranslation<TimingSimpleCPU *> *translation =
 542             new DataTranslation<TimingSimpleCPU *>(this, state);
 543         thread->dtb->translateTiming(req, thread->getTC(), translation, mode);
 544     }
 545
 546     // Translation faults will be returned via finishTranslation()
 547     return NoFault;
 548 }
 549
 550 void
 551 TimingSimpleCPU::threadSnoop(PacketPtr pkt, ThreadID sender)
 552 {
 553     for (ThreadID tid = 0; tid < numThreads; tid++) {
 554         if (tid != sender) {
 555             if (getCpuAddrMonitor(tid)->doMonitor(pkt)) {
 556                 wakeup(tid);
 557             }
 558             TheISA::handleLockedSnoop(threadInfo[tid]->thread, pkt,
 559                     dcachePort.cacheBlockMask);
 560         }
 561     }
 562 }
 563
 564 void
 565 TimingSimpleCPU::finishTranslation(WholeTranslationState *state)
 566 {
 567     _status = BaseSimpleCPU::Running;
 568
 569     if (state->getFault() != NoFault) {
 570         if (state->isPrefetch()) {
 571             state->setNoFault();
 572         }
 573         delete [] state->data;
 574         state->deleteReqs();
 575         translationFault(state->getFault());
 576     } else {
 577         if (!state->isSplit) {
 578             sendData(state->mainReq, state->data, state->res,
 579                      state->mode == BaseTLB::Read);
 580         } else {
 581             sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq,
 582                           state->data, state->mode == BaseTLB::Read);
 583         }
 584     }
 585
 586     delete state;
 587 }
 588
 589
 590 void
 591 TimingSimpleCPU::fetch()
 592 {
 593     // Change thread if multi-threaded
 594     swapActiveThread();
 595
 596     SimpleExecContext &t_info = *threadInfo[curThread];
 597     SimpleThread* thread = t_info.thread;
 598
 599     DPRINTF(SimpleCPU, "Fetch\n");
 600
 601     if (!curStaticInst || !curStaticInst->isDelayedCommit()) {
 602         checkForInterrupts();
 603         checkPcEventQueue();
 604     }
 605
 606     // We must have just got suspended by a PC event
 607     if (_status == Idle)
 608         return;
 609
 610     TheISA::PCState pcState = thread->pcState();
 611     bool needToFetch = !isRomMicroPC(pcState.microPC()) &&
 612                        !curMacroStaticInst;
 613
 614     if (needToFetch) {
 615         _status = BaseSimpleCPU::Running;
 616         Request *ifetch_req = new Request();
 617         ifetch_req->taskId(taskId());
 618         ifetch_req->setContext(thread->contextId());
 619         setupFetchRequest(ifetch_req);
 620         DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr());
 621         thread->itb->translateTiming(ifetch_req, thread->getTC(),
 622                 &fetchTranslation, BaseTLB::Execute);
 623     } else {
 624         _status = IcacheWaitResponse;
 625         completeIfetch(NULL);
 626
 627         updateCycleCounts();
 628     }
 629 }
 630
 631
 632 void
 633 TimingSimpleCPU::sendFetch(const Fault &fault, RequestPtr req,
 634                            ThreadContext *tc)
 635 {
 636     if (fault == NoFault) {
 637         DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n",
 638                 req->getVaddr(), req->getPaddr());
 639         ifetch_pkt = new Packet(req, MemCmd::ReadReq);
 640         ifetch_pkt->dataStatic(&inst);
 641         DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr());
 642
 643         if (!icachePort.sendTimingReq(ifetch_pkt)) {
 644             // Need to wait for retry
 645             _status = IcacheRetry;
 646         } else {
 647             // Need to wait for cache to respond
 648             _status = IcacheWaitResponse;
 649             // ownership of packet transferred to memory system
 650             ifetch_pkt = NULL;
 651         }
 652     } else {
 653         DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr());
 654         delete req;
 655         // fetch fault: advance directly to next instruction (fault handler)
 656         _status = BaseSimpleCPU::Running;
 657         advanceInst(fault);
 658     }
 659
 660     updateCycleCounts();
 661 }
 662
 663
 664 void
 665 TimingSimpleCPU::advanceInst(const Fault &fault)
 666 {
 667     SimpleExecContext &t_info = *threadInfo[curThread];
 668
 669     if (_status == Faulting)
 670         return;
 671
 672     if (fault != NoFault) {
 673         advancePC(fault);
 674         DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n");
 675         reschedule(fetchEvent, clockEdge(), true);
 676         _status = Faulting;
 677         return;
 678     }
 679
 680
 681     if (!t_info.stayAtPC)
 682         advancePC(fault);
 683
 684     if (tryCompleteDrain())
 685             return;
 686
 687     if (_status == BaseSimpleCPU::Running) {
 688         // kick off fetch of next instruction... callback from icache
 689         // response will cause that instruction to be executed,
 690         // keeping the CPU running.
 691         fetch();
 692     }
 693 }
 694
 695
 696 void
 697 TimingSimpleCPU::completeIfetch(PacketPtr pkt)
 698 {
 699     SimpleExecContext& t_info = *threadInfo[curThread];
 700
 701     DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ?
 702             pkt->getAddr() : 0);
 703
 704     // received a response from the icache: execute the received
 705     // instruction
 706     assert(!pkt || !pkt->isError());
 707     assert(_status == IcacheWaitResponse);
 708
 709     _status = BaseSimpleCPU::Running;
 710
 711     updateCycleCounts();
 712
 713     if (pkt)
 714         pkt->req->setAccessLatency();
 715
 716
 717     preExecute();
 718     if (curStaticInst && curStaticInst->isMemRef()) {
 719         // load or store: just send to dcache
 720         Fault fault = curStaticInst->initiateAcc(&t_info, traceData);
 721
 722         // If we're not running now the instruction will complete in a dcache
 723         // response callback or the instruction faulted and has started an
 724         // ifetch
 725         if (_status == BaseSimpleCPU::Running) {
 726             if (fault != NoFault && traceData) {
 727                 // If there was a fault, we shouldn't trace this instruction.
 728                 delete traceData;
 729                 traceData = NULL;
 730             }
 731
 732             postExecute();
 733             // @todo remove me after debugging with legion done
 734             if (curStaticInst && (!curStaticInst->isMicroop() ||
 735                         curStaticInst->isFirstMicroop()))
 736                 instCnt++;
 737             advanceInst(fault);
 738         }
 739     } else if (curStaticInst) {
 740         // non-memory instruction: execute completely now
 741         Fault fault = curStaticInst->execute(&t_info, traceData);
 742
 743         // keep an instruction count
 744         if (fault == NoFault)
 745             countInst();
 746         else if (traceData && !DTRACE(ExecFaulting)) {
 747             delete traceData;
 748             traceData = NULL;
 749         }
 750
 751         postExecute();
 752         // @todo remove me after debugging with legion done
 753         if (curStaticInst && (!curStaticInst->isMicroop() ||
 754                 curStaticInst->isFirstMicroop()))
 755             instCnt++;
 756         advanceInst(fault);
 757     } else {
 758         advanceInst(NoFault);
 759     }
 760
 761     if (pkt) {
 762         delete pkt->req;
 763         delete pkt;
 764     }
 765 }
 766
 767 void
 768 TimingSimpleCPU::IcachePort::ITickEvent::process()
 769 {
 770     cpu->completeIfetch(pkt);
 771 }
 772
 773 bool
 774 TimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt)
 775 {
 776     DPRINTF(SimpleCPU, "Received fetch response %#x\n", pkt->getAddr());
 777     // we should only ever see one response per cycle since we only
 778     // issue a new request once this response is sunk
 779     assert(!tickEvent.scheduled());
 780     // delay processing of returned data until next CPU clock edge
 781     tickEvent.schedule(pkt, cpu->clockEdge());
 782
 783     return true;
 784 }
 785
 786 void
 787 TimingSimpleCPU::IcachePort::recvReqRetry()
 788 {
 789     // we shouldn't get a retry unless we have a packet that we're
 790     // waiting to transmit
 791     assert(cpu->ifetch_pkt != NULL);
 792     assert(cpu->_status == IcacheRetry);
 793     PacketPtr tmp = cpu->ifetch_pkt;
 794     if (sendTimingReq(tmp)) {
 795         cpu->_status = IcacheWaitResponse;
 796         cpu->ifetch_pkt = NULL;
 797     }
 798 }
 799
 800 void
 801 TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
 802 {
 803     // received a response from the dcache: complete the load or store
 804     // instruction
 805     assert(!pkt->isError());
 806     assert(_status == DcacheWaitResponse || _status == DTBWaitResponse ||
 807            pkt->req->getFlags().isSet(Request::NO_ACCESS));
 808
 809     pkt->req->setAccessLatency();
 810
 811     updateCycleCounts();
 812
 813     if (pkt->senderState) {
 814         SplitFragmentSenderState * send_state =
 815             dynamic_cast<SplitFragmentSenderState *>(pkt->senderState);
 816         assert(send_state);
 817         delete pkt->req;
 818         delete pkt;
 819         PacketPtr big_pkt = send_state->bigPkt;
 820         delete send_state;
 821
 822         SplitMainSenderState * main_send_state =
 823             dynamic_cast<SplitMainSenderState *>(big_pkt->senderState);
 824         assert(main_send_state);
 825         // Record the fact that this packet is no longer outstanding.
 826         assert(main_send_state->outstanding != 0);
 827         main_send_state->outstanding--;
 828
 829         if (main_send_state->outstanding) {
 830             return;
 831         } else {
 832             delete main_send_state;
 833             big_pkt->senderState = NULL;
 834             pkt = big_pkt;
 835         }
 836     }
 837
 838     _status = BaseSimpleCPU::Running;
 839
 840     Fault fault = curStaticInst->completeAcc(pkt, threadInfo[curThread],
 841                                              traceData);
 842
 843     // keep an instruction count
 844     if (fault == NoFault)
 845         countInst();
 846     else if (traceData) {
 847         // If there was a fault, we shouldn't trace this instruction.
 848         delete traceData;
 849         traceData = NULL;
 850     }
 851
 852     delete pkt->req;
 853     delete pkt;
 854
 855     postExecute();
 856
 857     advanceInst(fault);
 858 }
 859
 860 void
 861 TimingSimpleCPU::updateCycleCounts()
 862 {
 863     const Cycles delta(curCycle() - previousCycle);
 864
 865     numCycles += delta;
 866     ppCycles->notify(delta);
 867
 868     previousCycle = curCycle();
 869 }
 870
 871 void
 872 TimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt)
 873 {
 874     for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
 875         if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
 876             cpu->wakeup(tid);
 877         }
 878     }
 879
 880     // Making it uniform across all CPUs:
 881     // The CPUs need to be woken up only on an invalidation packet (when using caches)
 882     // or on an incoming write packet (when not using caches)
 883     // It is not necessary to wake up the processor on all incoming packets
 884     if (pkt->isInvalidate() || pkt->isWrite()) {
 885         for (auto &t_info : cpu->threadInfo) {
 886             TheISA::handleLockedSnoop(t_info->thread, pkt, cacheBlockMask);
 887         }
 888     }
 889 }
 890
 891 void
 892 TimingSimpleCPU::DcachePort::recvFunctionalSnoop(PacketPtr pkt)
 893 {
 894     for (ThreadID tid = 0; tid < cpu->numThreads; tid++) {
 895         if (cpu->getCpuAddrMonitor(tid)->doMonitor(pkt)) {
 896             cpu->wakeup(tid);
 897         }
 898     }
 899 }
 900
 901 bool
 902 TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt)
 903 {
 904     DPRINTF(SimpleCPU, "Received load/store response %#x\n", pkt->getAddr());
 905
 906     // The timing CPU is not really ticked, instead it relies on the
 907     // memory system (fetch and load/store) to set the pace.
 908     if (!tickEvent.scheduled()) {
 909         // Delay processing of returned data until next CPU clock edge
 910         tickEvent.schedule(pkt, cpu->clockEdge());
 911         return true;
 912     } else {
 913         // In the case of a split transaction and a cache that is
 914         // faster than a CPU we could get two responses in the
 915         // same tick, delay the second one
 916         if (!retryRespEvent.scheduled())
 917             cpu->schedule(retryRespEvent, cpu->clockEdge(Cycles(1)));
 918         return false;
 919     }
 920 }
 921
 922 void
 923 TimingSimpleCPU::DcachePort::DTickEvent::process()
 924 {
 925     cpu->completeDataAccess(pkt);
 926 }
 927
 928 void
 929 TimingSimpleCPU::DcachePort::recvReqRetry()
 930 {
 931     // we shouldn't get a retry unless we have a packet that we're
 932     // waiting to transmit
 933     assert(cpu->dcache_pkt != NULL);
 934     assert(cpu->_status == DcacheRetry);
 935     PacketPtr tmp = cpu->dcache_pkt;
 936     if (tmp->senderState) {
 937         // This is a packet from a split access.
 938         SplitFragmentSenderState * send_state =
 939             dynamic_cast<SplitFragmentSenderState *>(tmp->senderState);
 940         assert(send_state);
 941         PacketPtr big_pkt = send_state->bigPkt;
 942
 943         SplitMainSenderState * main_send_state =
 944             dynamic_cast<SplitMainSenderState *>(big_pkt->senderState);
 945         assert(main_send_state);
 946
 947         if (sendTimingReq(tmp)) {
 948             // If we were able to send without retrying, record that fact
 949             // and try sending the other fragment.
 950             send_state->clearFromParent();
 951             int other_index = main_send_state->getPendingFragment();
 952             if (other_index > 0) {
 953                 tmp = main_send_state->fragments[other_index];
 954                 cpu->dcache_pkt = tmp;
 955                 if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) ||
 956                         (big_pkt->isWrite() && cpu->handleWritePacket())) {
 957                     main_send_state->fragments[other_index] = NULL;
 958                 }
 959             } else {
 960                 cpu->_status = DcacheWaitResponse;
 961                 // memory system takes ownership of packet
 962                 cpu->dcache_pkt = NULL;
 963             }
 964         }
 965     } else if (sendTimingReq(tmp)) {
 966         cpu->_status = DcacheWaitResponse;
 967         // memory system takes ownership of packet
 968         cpu->dcache_pkt = NULL;
 969     }
 970 }
 971
 972 TimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu,
 973     Tick t)
 974     : pkt(_pkt), cpu(_cpu)
 975 {
 976     cpu->schedule(this, t);
 977 }
 978
 979 void
 980 TimingSimpleCPU::IprEvent::process()
 981 {
 982     cpu->completeDataAccess(pkt);
 983 }
 984
 985 const char *
 986 TimingSimpleCPU::IprEvent::description() const
 987 {
 988     return "Timing Simple CPU Delay IPR event";
 989 }
 990
 991
 992 void
 993 TimingSimpleCPU::printAddr(Addr a)
 994 {
 995     dcachePort.printAddr(a);
 996 }
 997
 998
 999 ////////////////////////////////////////////////////////////////////////
1000 //
1001 //  TimingSimpleCPU Simulation Object
1002 //
1003 TimingSimpleCPU *
1004 TimingSimpleCPUParams::create()
1005 {
1006     return new TimingSimpleCPU(this);
1007 }