2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
31 #include "arch/locked_mem.hh"
32 #include "arch/mmaped_ipr.hh"
33 #include "arch/utility.hh"
34 #include "base/bigint.hh"
35 #include "cpu/exetrace.hh"
36 #include "cpu/simple/timing.hh"
37 #include "mem/packet.hh"
38 #include "mem/packet_access.hh"
39 #include "params/TimingSimpleCPU.hh"
40 #include "sim/system.hh"
43 using namespace TheISA
;
46 TimingSimpleCPU::getPort(const std::string
&if_name
, int idx
)
48 if (if_name
== "dcache_port")
50 else if (if_name
== "icache_port")
53 panic("No Such Port\n");
57 TimingSimpleCPU::init()
61 for (int i
= 0; i
< threadContexts
.size(); ++i
) {
62 ThreadContext
*tc
= threadContexts
[i
];
64 // initialize CPU, including PC
65 TheISA::initCPU(tc
, _cpuId
);
71 TimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt
)
73 panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
78 TimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt
)
80 //No internal storage to update, jusst return
85 TimingSimpleCPU::CpuPort::recvStatusChange(Status status
)
87 if (status
== RangeChange
) {
88 if (!snoopRangeSent
) {
89 snoopRangeSent
= true;
90 sendStatusChange(Port::RangeChange
);
95 panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
100 TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt
, Tick t
)
103 cpu
->schedule(this, t
);
106 TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams
*p
)
107 : BaseSimpleCPU(p
), icachePort(this, p
->clock
), dcachePort(this, p
->clock
), fetchEvent(this)
111 icachePort
.snoopRangeSent
= false;
112 dcachePort
.snoopRangeSent
= false;
114 ifetch_pkt
= dcache_pkt
= NULL
;
117 changeState(SimObject::Running
);
121 TimingSimpleCPU::~TimingSimpleCPU()
126 TimingSimpleCPU::serialize(ostream
&os
)
128 SimObject::State so_state
= SimObject::getState();
129 SERIALIZE_ENUM(so_state
);
130 BaseSimpleCPU::serialize(os
);
134 TimingSimpleCPU::unserialize(Checkpoint
*cp
, const string
§ion
)
136 SimObject::State so_state
;
137 UNSERIALIZE_ENUM(so_state
);
138 BaseSimpleCPU::unserialize(cp
, section
);
142 TimingSimpleCPU::drain(Event
*drain_event
)
144 // TimingSimpleCPU is ready to drain if it's not waiting for
145 // an access to complete.
146 if (_status
== Idle
|| _status
== Running
|| _status
== SwitchedOut
) {
147 changeState(SimObject::Drained
);
150 changeState(SimObject::Draining
);
151 drainEvent
= drain_event
;
157 TimingSimpleCPU::resume()
159 DPRINTF(SimpleCPU
, "Resume\n");
160 if (_status
!= SwitchedOut
&& _status
!= Idle
) {
161 assert(system
->getMemoryMode() == Enums::timing
);
163 if (fetchEvent
.scheduled())
164 deschedule(fetchEvent
);
166 schedule(fetchEvent
, nextCycle());
169 changeState(SimObject::Running
);
173 TimingSimpleCPU::switchOut()
175 assert(_status
== Running
|| _status
== Idle
);
176 _status
= SwitchedOut
;
177 numCycles
+= tickToCycles(curTick
- previousTick
);
179 // If we've been scheduled to resume but are then told to switch out,
180 // we'll need to cancel it.
181 if (fetchEvent
.scheduled())
182 deschedule(fetchEvent
);
187 TimingSimpleCPU::takeOverFrom(BaseCPU
*oldCPU
)
189 BaseCPU::takeOverFrom(oldCPU
, &icachePort
, &dcachePort
);
191 // if any of this CPU's ThreadContexts are active, mark the CPU as
192 // running and schedule its tick event.
193 for (int i
= 0; i
< threadContexts
.size(); ++i
) {
194 ThreadContext
*tc
= threadContexts
[i
];
195 if (tc
->status() == ThreadContext::Active
&& _status
!= Running
) {
201 if (_status
!= Running
) {
204 assert(threadContexts
.size() == 1);
205 previousTick
= curTick
;
210 TimingSimpleCPU::activateContext(int thread_num
, int delay
)
212 DPRINTF(SimpleCPU
, "ActivateContext %d (%d cycles)\n", thread_num
, delay
);
214 assert(thread_num
== 0);
217 assert(_status
== Idle
);
222 // kick things off by initiating the fetch of the next instruction
223 schedule(fetchEvent
, nextCycle(curTick
+ ticks(delay
)));
228 TimingSimpleCPU::suspendContext(int thread_num
)
230 DPRINTF(SimpleCPU
, "SuspendContext %d\n", thread_num
);
232 assert(thread_num
== 0);
235 assert(_status
== Running
);
237 // just change status to Idle... if status != Running,
238 // completeInst() will not initiate fetch of next instruction.
245 TimingSimpleCPU::handleReadPacket(PacketPtr pkt
)
247 RequestPtr req
= pkt
->req
;
248 if (req
->isMmapedIpr()) {
250 delay
= TheISA::handleIprRead(thread
->getTC(), pkt
);
251 new IprEvent(pkt
, this, nextCycle(curTick
+ delay
));
252 _status
= DcacheWaitResponse
;
254 } else if (!dcachePort
.sendTiming(pkt
)) {
255 _status
= DcacheRetry
;
258 _status
= DcacheWaitResponse
;
259 // memory system takes ownership of packet
262 return dcache_pkt
== NULL
;
266 TimingSimpleCPU::buildSplitPacket(PacketPtr
&pkt1
, PacketPtr
&pkt2
,
267 RequestPtr
&req
, Addr split_addr
, uint8_t *data
, bool read
)
270 RequestPtr req1
, req2
;
271 assert(!req
->isLocked() && !req
->isSwap());
272 req
->splitOnVaddr(split_addr
, req1
, req2
);
275 if ((fault
= buildPacket(pkt1
, req1
, read
)) != NoFault
||
276 (fault
= buildPacket(pkt2
, req2
, read
)) != NoFault
) {
284 assert(!req1
->isMmapedIpr() && !req2
->isMmapedIpr());
286 req
->setPhys(req1
->getPaddr(), req
->getSize(), req1
->getFlags());
287 PacketPtr pkt
= new Packet(req
, pkt1
->cmd
.responseCommand(),
290 pkt
->dataDynamic
<uint8_t>(data
);
291 pkt1
->dataStatic
<uint8_t>(data
);
292 pkt2
->dataStatic
<uint8_t>(data
+ req1
->getSize());
294 SplitMainSenderState
* main_send_state
= new SplitMainSenderState
;
295 pkt
->senderState
= main_send_state
;
296 main_send_state
->fragments
[0] = pkt1
;
297 main_send_state
->fragments
[1] = pkt2
;
298 main_send_state
->outstanding
= 2;
299 pkt1
->senderState
= new SplitFragmentSenderState(pkt
, 0);
300 pkt2
->senderState
= new SplitFragmentSenderState(pkt
, 1);
305 TimingSimpleCPU::buildPacket(PacketPtr
&pkt
, RequestPtr
&req
, bool read
)
307 Fault fault
= read
? thread
->translateDataReadReq(req
) :
308 thread
->translateDataWriteReq(req
);
310 if (fault
!= NoFault
) {
316 cmd
= MemCmd::ReadReq
;
318 cmd
= MemCmd::LoadLockedReq
;
320 cmd
= MemCmd::WriteReq
;
321 if (req
->isLocked()) {
322 cmd
= MemCmd::StoreCondReq
;
323 } else if (req
->isSwap()) {
324 cmd
= MemCmd::SwapReq
;
327 pkt
= new Packet(req
, cmd
, Packet::Broadcast
);
333 TimingSimpleCPU::read(Addr addr
, T
&data
, unsigned flags
)
337 const int thread_id
= 0;
338 const Addr pc
= thread
->readPC();
339 int block_size
= dcachePort
.peerBlockSize();
340 int data_size
= sizeof(T
);
343 RequestPtr req
= new Request(asid
, addr
, data_size
,
344 flags
, pc
, _cpuId
, thread_id
);
346 Addr split_addr
= roundDown(addr
+ data_size
- 1, block_size
);
347 assert(split_addr
<= addr
|| split_addr
- addr
< block_size
);
349 if (split_addr
> addr
) {
350 PacketPtr pkt1
, pkt2
;
351 this->buildSplitPacket(pkt1
, pkt2
, req
,
352 split_addr
, (uint8_t *)(new T
), true);
353 if (handleReadPacket(pkt1
)) {
354 SplitFragmentSenderState
* send_state
=
355 dynamic_cast<SplitFragmentSenderState
*>(pkt1
->senderState
);
356 send_state
->clearFromParent();
357 if (handleReadPacket(pkt2
)) {
359 dynamic_cast<SplitFragmentSenderState
*>(pkt1
->senderState
);
360 send_state
->clearFromParent();
364 Fault fault
= buildPacket(pkt
, req
, true);
365 if (fault
!= NoFault
) {
368 pkt
->dataDynamic
<T
>(new T
);
370 handleReadPacket(pkt
);
374 traceData
->setData(data
);
375 traceData
->setAddr(addr
);
378 // This will need a new way to tell if it has a dcache attached.
379 if (req
->isUncacheable())
380 recordEvent("Uncached Read");
386 TimingSimpleCPU::translateDataReadAddr(Addr vaddr
, Addr
&paddr
,
387 int size
, unsigned flags
)
390 new Request(0, vaddr
, size
, flags
, thread
->readPC(), _cpuId
, 0);
393 traceData
->setAddr(vaddr
);
396 Fault fault
= thread
->translateDataWriteReq(req
);
398 if (fault
== NoFault
)
399 paddr
= req
->getPaddr();
405 #ifndef DOXYGEN_SHOULD_SKIP_THIS
409 TimingSimpleCPU::read(Addr addr
, Twin64_t
&data
, unsigned flags
);
413 TimingSimpleCPU::read(Addr addr
, Twin32_t
&data
, unsigned flags
);
417 TimingSimpleCPU::read(Addr addr
, uint64_t &data
, unsigned flags
);
421 TimingSimpleCPU::read(Addr addr
, uint32_t &data
, unsigned flags
);
425 TimingSimpleCPU::read(Addr addr
, uint16_t &data
, unsigned flags
);
429 TimingSimpleCPU::read(Addr addr
, uint8_t &data
, unsigned flags
);
431 #endif //DOXYGEN_SHOULD_SKIP_THIS
435 TimingSimpleCPU::read(Addr addr
, double &data
, unsigned flags
)
437 return read(addr
, *(uint64_t*)&data
, flags
);
442 TimingSimpleCPU::read(Addr addr
, float &data
, unsigned flags
)
444 return read(addr
, *(uint32_t*)&data
, flags
);
450 TimingSimpleCPU::read(Addr addr
, int32_t &data
, unsigned flags
)
452 return read(addr
, (uint32_t&)data
, flags
);
456 TimingSimpleCPU::handleWritePacket()
458 RequestPtr req
= dcache_pkt
->req
;
459 if (req
->isMmapedIpr()) {
461 delay
= TheISA::handleIprWrite(thread
->getTC(), dcache_pkt
);
462 new IprEvent(dcache_pkt
, this, nextCycle(curTick
+ delay
));
463 _status
= DcacheWaitResponse
;
465 } else if (!dcachePort
.sendTiming(dcache_pkt
)) {
466 _status
= DcacheRetry
;
468 _status
= DcacheWaitResponse
;
469 // memory system takes ownership of packet
472 return dcache_pkt
== NULL
;
477 TimingSimpleCPU::write(T data
, Addr addr
, unsigned flags
, uint64_t *res
)
480 const int thread_id
= 0;
481 const Addr pc
= thread
->readPC();
482 int block_size
= dcachePort
.peerBlockSize();
483 int data_size
= sizeof(T
);
485 RequestPtr req
= new Request(asid
, addr
, data_size
,
486 flags
, pc
, _cpuId
, thread_id
);
488 Addr split_addr
= roundDown(addr
+ data_size
- 1, block_size
);
489 assert(split_addr
<= addr
|| split_addr
- addr
< block_size
);
491 if (split_addr
> addr
) {
492 PacketPtr pkt1
, pkt2
;
495 Fault fault
= this->buildSplitPacket(pkt1
, pkt2
, req
, split_addr
,
496 (uint8_t *)dataP
, false);
497 if (fault
!= NoFault
)
500 if (handleWritePacket()) {
501 SplitFragmentSenderState
* send_state
=
502 dynamic_cast<SplitFragmentSenderState
*>(pkt1
->senderState
);
503 send_state
->clearFromParent();
505 if (handleReadPacket(pkt2
)) {
507 dynamic_cast<SplitFragmentSenderState
*>(pkt1
->senderState
);
508 send_state
->clearFromParent();
512 bool do_access
= true; // flag to suppress cache access
514 Fault fault
= buildPacket(dcache_pkt
, req
, false);
515 if (fault
!= NoFault
)
518 if (req
->isLocked()) {
519 do_access
= TheISA::handleLockedWrite(thread
, req
);
520 } else if (req
->isCondSwap()) {
522 req
->setExtraData(*res
);
525 dcache_pkt
->allocate();
526 if (req
->isMmapedIpr())
527 dcache_pkt
->set(htog(data
));
529 dcache_pkt
->set(data
);
536 traceData
->setAddr(req
->getVaddr());
537 traceData
->setData(data
);
540 // This will need a new way to tell if it's hooked up to a cache or not.
541 if (req
->isUncacheable())
542 recordEvent("Uncached Write");
544 // If the write needs to have a fault on the access, consider calling
545 // changeStatus() and changing it to "bad addr write" or something.
550 TimingSimpleCPU::translateDataWriteAddr(Addr vaddr
, Addr
&paddr
,
551 int size
, unsigned flags
)
554 new Request(0, vaddr
, size
, flags
, thread
->readPC(), _cpuId
, 0);
557 traceData
->setAddr(vaddr
);
560 Fault fault
= thread
->translateDataWriteReq(req
);
562 if (fault
== NoFault
)
563 paddr
= req
->getPaddr();
570 #ifndef DOXYGEN_SHOULD_SKIP_THIS
573 TimingSimpleCPU::write(Twin32_t data
, Addr addr
,
574 unsigned flags
, uint64_t *res
);
578 TimingSimpleCPU::write(Twin64_t data
, Addr addr
,
579 unsigned flags
, uint64_t *res
);
583 TimingSimpleCPU::write(uint64_t data
, Addr addr
,
584 unsigned flags
, uint64_t *res
);
588 TimingSimpleCPU::write(uint32_t data
, Addr addr
,
589 unsigned flags
, uint64_t *res
);
593 TimingSimpleCPU::write(uint16_t data
, Addr addr
,
594 unsigned flags
, uint64_t *res
);
598 TimingSimpleCPU::write(uint8_t data
, Addr addr
,
599 unsigned flags
, uint64_t *res
);
601 #endif //DOXYGEN_SHOULD_SKIP_THIS
605 TimingSimpleCPU::write(double data
, Addr addr
, unsigned flags
, uint64_t *res
)
607 return write(*(uint64_t*)&data
, addr
, flags
, res
);
612 TimingSimpleCPU::write(float data
, Addr addr
, unsigned flags
, uint64_t *res
)
614 return write(*(uint32_t*)&data
, addr
, flags
, res
);
620 TimingSimpleCPU::write(int32_t data
, Addr addr
, unsigned flags
, uint64_t *res
)
622 return write((uint32_t)data
, addr
, flags
, res
);
627 TimingSimpleCPU::fetch()
629 DPRINTF(SimpleCPU
, "Fetch\n");
631 if (!curStaticInst
|| !curStaticInst
->isDelayedCommit())
632 checkForInterrupts();
636 bool fromRom
= isRomMicroPC(thread
->readMicroPC());
639 Request
*ifetch_req
= new Request();
640 ifetch_req
->setThreadContext(_cpuId
, /* thread ID */ 0);
641 Fault fault
= setupFetchRequest(ifetch_req
);
643 ifetch_pkt
= new Packet(ifetch_req
, MemCmd::ReadReq
, Packet::Broadcast
);
644 ifetch_pkt
->dataStatic(&inst
);
646 if (fault
== NoFault
) {
647 if (!icachePort
.sendTiming(ifetch_pkt
)) {
648 // Need to wait for retry
649 _status
= IcacheRetry
;
651 // Need to wait for cache to respond
652 _status
= IcacheWaitResponse
;
653 // ownership of packet transferred to memory system
659 // fetch fault: advance directly to next instruction (fault handler)
663 _status
= IcacheWaitResponse
;
664 completeIfetch(NULL
);
667 numCycles
+= tickToCycles(curTick
- previousTick
);
668 previousTick
= curTick
;
673 TimingSimpleCPU::advanceInst(Fault fault
)
675 if (fault
!= NoFault
|| !stayAtPC
)
678 if (_status
== Running
) {
679 // kick off fetch of next instruction... callback from icache
680 // response will cause that instruction to be executed,
681 // keeping the CPU running.
688 TimingSimpleCPU::completeIfetch(PacketPtr pkt
)
690 DPRINTF(SimpleCPU
, "Complete ICache Fetch\n");
692 // received a response from the icache: execute the received
695 assert(!pkt
|| !pkt
->isError());
696 assert(_status
== IcacheWaitResponse
);
700 numCycles
+= tickToCycles(curTick
- previousTick
);
701 previousTick
= curTick
;
703 if (getState() == SimObject::Draining
) {
715 curStaticInst
->isMemRef() && !curStaticInst
->isDataPrefetch()) {
716 // load or store: just send to dcache
717 Fault fault
= curStaticInst
->initiateAcc(this, traceData
);
718 if (_status
!= Running
) {
719 // instruction will complete in dcache response callback
720 assert(_status
== DcacheWaitResponse
|| _status
== DcacheRetry
);
721 assert(fault
== NoFault
);
723 if (fault
== NoFault
) {
724 // Note that ARM can have NULL packets if the instruction gets
725 // squashed due to predication
726 // early fail on store conditional: complete now
727 assert(dcache_pkt
!= NULL
|| THE_ISA
== ARM_ISA
);
729 fault
= curStaticInst
->completeAcc(dcache_pkt
, this,
731 if (dcache_pkt
!= NULL
)
733 delete dcache_pkt
->req
;
738 // keep an instruction count
739 if (fault
== NoFault
)
741 } else if (traceData
) {
742 // If there was a fault, we shouldn't trace this instruction.
748 // @todo remove me after debugging with legion done
749 if (curStaticInst
&& (!curStaticInst
->isMicroop() ||
750 curStaticInst
->isFirstMicroop()))
754 } else if (curStaticInst
) {
755 // non-memory instruction: execute completely now
756 Fault fault
= curStaticInst
->execute(this, traceData
);
758 // keep an instruction count
759 if (fault
== NoFault
)
761 else if (traceData
) {
762 // If there was a fault, we shouldn't trace this instruction.
768 // @todo remove me after debugging with legion done
769 if (curStaticInst
&& (!curStaticInst
->isMicroop() ||
770 curStaticInst
->isFirstMicroop()))
774 advanceInst(NoFault
);
784 TimingSimpleCPU::IcachePort::ITickEvent::process()
786 cpu
->completeIfetch(pkt
);
790 TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt
)
792 if (pkt
->isResponse() && !pkt
->wasNacked()) {
793 // delay processing of returned data until next CPU clock edge
794 Tick next_tick
= cpu
->nextCycle(curTick
);
796 if (next_tick
== curTick
)
797 cpu
->completeIfetch(pkt
);
799 tickEvent
.schedule(pkt
, next_tick
);
803 else if (pkt
->wasNacked()) {
804 assert(cpu
->_status
== IcacheWaitResponse
);
806 if (!sendTiming(pkt
)) {
807 cpu
->_status
= IcacheRetry
;
808 cpu
->ifetch_pkt
= pkt
;
811 //Snooping a Coherence Request, do nothing
816 TimingSimpleCPU::IcachePort::recvRetry()
818 // we shouldn't get a retry unless we have a packet that we're
819 // waiting to transmit
820 assert(cpu
->ifetch_pkt
!= NULL
);
821 assert(cpu
->_status
== IcacheRetry
);
822 PacketPtr tmp
= cpu
->ifetch_pkt
;
823 if (sendTiming(tmp
)) {
824 cpu
->_status
= IcacheWaitResponse
;
825 cpu
->ifetch_pkt
= NULL
;
830 TimingSimpleCPU::completeDataAccess(PacketPtr pkt
)
832 // received a response from the dcache: complete the load or store
834 assert(!pkt
->isError());
836 numCycles
+= tickToCycles(curTick
- previousTick
);
837 previousTick
= curTick
;
839 if (pkt
->senderState
) {
840 SplitFragmentSenderState
* send_state
=
841 dynamic_cast<SplitFragmentSenderState
*>(pkt
->senderState
);
845 PacketPtr big_pkt
= send_state
->bigPkt
;
848 SplitMainSenderState
* main_send_state
=
849 dynamic_cast<SplitMainSenderState
*>(big_pkt
->senderState
);
850 assert(main_send_state
);
851 // Record the fact that this packet is no longer outstanding.
852 assert(main_send_state
->outstanding
!= 0);
853 main_send_state
->outstanding
--;
855 if (main_send_state
->outstanding
) {
858 delete main_send_state
;
859 big_pkt
->senderState
= NULL
;
864 assert(_status
== DcacheWaitResponse
);
867 Fault fault
= curStaticInst
->completeAcc(pkt
, this, traceData
);
869 // keep an instruction count
870 if (fault
== NoFault
)
872 else if (traceData
) {
873 // If there was a fault, we shouldn't trace this instruction.
878 // the locked flag may be cleared on the response packet, so check
879 // pkt->req and not pkt to see if it was a load-locked
880 if (pkt
->isRead() && pkt
->req
->isLocked()) {
881 TheISA::handleLockedRead(thread
, pkt
->req
);
889 if (getState() == SimObject::Draining
) {
901 TimingSimpleCPU::completeDrain()
903 DPRINTF(Config
, "Done draining\n");
904 changeState(SimObject::Drained
);
905 drainEvent
->process();
909 TimingSimpleCPU::DcachePort::setPeer(Port
*port
)
914 // Update the ThreadContext's memory ports (Functional/Virtual
916 cpu
->tcBase()->connectMemPorts(cpu
->tcBase());
921 TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt
)
923 if (pkt
->isResponse() && !pkt
->wasNacked()) {
924 // delay processing of returned data until next CPU clock edge
925 Tick next_tick
= cpu
->nextCycle(curTick
);
927 if (next_tick
== curTick
) {
928 cpu
->completeDataAccess(pkt
);
930 tickEvent
.schedule(pkt
, next_tick
);
935 else if (pkt
->wasNacked()) {
936 assert(cpu
->_status
== DcacheWaitResponse
);
938 if (!sendTiming(pkt
)) {
939 cpu
->_status
= DcacheRetry
;
940 cpu
->dcache_pkt
= pkt
;
943 //Snooping a Coherence Request, do nothing
948 TimingSimpleCPU::DcachePort::DTickEvent::process()
950 cpu
->completeDataAccess(pkt
);
954 TimingSimpleCPU::DcachePort::recvRetry()
956 // we shouldn't get a retry unless we have a packet that we're
957 // waiting to transmit
958 assert(cpu
->dcache_pkt
!= NULL
);
959 assert(cpu
->_status
== DcacheRetry
);
960 PacketPtr tmp
= cpu
->dcache_pkt
;
961 if (tmp
->senderState
) {
962 // This is a packet from a split access.
963 SplitFragmentSenderState
* send_state
=
964 dynamic_cast<SplitFragmentSenderState
*>(tmp
->senderState
);
966 PacketPtr big_pkt
= send_state
->bigPkt
;
968 SplitMainSenderState
* main_send_state
=
969 dynamic_cast<SplitMainSenderState
*>(big_pkt
->senderState
);
970 assert(main_send_state
);
972 if (sendTiming(tmp
)) {
973 // If we were able to send without retrying, record that fact
974 // and try sending the other fragment.
975 send_state
->clearFromParent();
976 int other_index
= main_send_state
->getPendingFragment();
977 if (other_index
> 0) {
978 tmp
= main_send_state
->fragments
[other_index
];
979 cpu
->dcache_pkt
= tmp
;
980 if ((big_pkt
->isRead() && cpu
->handleReadPacket(tmp
)) ||
981 (big_pkt
->isWrite() && cpu
->handleWritePacket())) {
982 main_send_state
->fragments
[other_index
] = NULL
;
985 cpu
->_status
= DcacheWaitResponse
;
986 // memory system takes ownership of packet
987 cpu
->dcache_pkt
= NULL
;
990 } else if (sendTiming(tmp
)) {
991 cpu
->_status
= DcacheWaitResponse
;
992 // memory system takes ownership of packet
993 cpu
->dcache_pkt
= NULL
;
997 TimingSimpleCPU::IprEvent::IprEvent(Packet
*_pkt
, TimingSimpleCPU
*_cpu
,
999 : pkt(_pkt
), cpu(_cpu
)
1001 cpu
->schedule(this, t
);
1005 TimingSimpleCPU::IprEvent::process()
1007 cpu
->completeDataAccess(pkt
);
1011 TimingSimpleCPU::IprEvent::description() const
1013 return "Timing Simple CPU Delay IPR event";
1018 TimingSimpleCPU::printAddr(Addr a
)
1020 dcachePort
.printAddr(a
);
1024 ////////////////////////////////////////////////////////////////////////
1026 // TimingSimpleCPU Simulation Object
1029 TimingSimpleCPUParams::create()
1033 if (workload
.size() != 1)
1034 panic("only one workload allowed");
1036 return new TimingSimpleCPU(this);