src/cpu/simple/timing.cc

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  */
  30
  31 #include "arch/locked_mem.hh"
  32 #include "arch/utility.hh"
  33 #include "base/bigint.hh"
  34 #include "cpu/exetrace.hh"
  35 #include "cpu/simple/timing.hh"
  36 #include "mem/packet.hh"
  37 #include "mem/packet_access.hh"
  38 #include "sim/builder.hh"
  39 #include "sim/system.hh"
  40
  41 using namespace std;
  42 using namespace TheISA;
  43
  44 Port *
  45 TimingSimpleCPU::getPort(const std::string &if_name, int idx)
  46 {
  47     if (if_name == "dcache_port")
  48         return &dcachePort;
  49     else if (if_name == "icache_port")
  50         return &icachePort;
  51     else
  52         panic("No Such Port\n");
  53 }
  54
  55 void
  56 TimingSimpleCPU::init()
  57 {
  58     BaseCPU::init();
  59 #if FULL_SYSTEM
  60     for (int i = 0; i < threadContexts.size(); ++i) {
  61         ThreadContext *tc = threadContexts[i];
  62
  63         // initialize CPU, including PC
  64         TheISA::initCPU(tc, tc->readCpuId());
  65     }
  66 #endif
  67 }
  68
  69 Tick
  70 TimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
  71 {
  72     panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
  73     return curTick;
  74 }
  75
  76 void
  77 TimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
  78 {
  79     //No internal storage to update, jusst return
  80     return;
  81 }
  82
  83 void
  84 TimingSimpleCPU::CpuPort::recvStatusChange(Status status)
  85 {
  86     if (status == RangeChange) {
  87         if (!snoopRangeSent) {
  88             snoopRangeSent = true;
  89             sendStatusChange(Port::RangeChange);
  90         }
  91         return;
  92     }
  93
  94     panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
  95 }
  96
  97
  98 void
  99 TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
 100 {
 101     pkt = _pkt;
 102     Event::schedule(t);
 103 }
 104
 105 TimingSimpleCPU::TimingSimpleCPU(Params *p)
 106     : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock),
 107       cpu_id(p->cpu_id)
 108 {
 109     _status = Idle;
 110
 111     icachePort.snoopRangeSent = false;
 112     dcachePort.snoopRangeSent = false;
 113
 114     ifetch_pkt = dcache_pkt = NULL;
 115     drainEvent = NULL;
 116     fetchEvent = NULL;
 117     previousTick = 0;
 118     changeState(SimObject::Running);
 119 }
 120
 121
 122 TimingSimpleCPU::~TimingSimpleCPU()
 123 {
 124 }
 125
 126 void
 127 TimingSimpleCPU::serialize(ostream &os)
 128 {
 129     SimObject::State so_state = SimObject::getState();
 130     SERIALIZE_ENUM(so_state);
 131     BaseSimpleCPU::serialize(os);
 132 }
 133
 134 void
 135 TimingSimpleCPU::unserialize(Checkpoint *cp, const string &section)
 136 {
 137     SimObject::State so_state;
 138     UNSERIALIZE_ENUM(so_state);
 139     BaseSimpleCPU::unserialize(cp, section);
 140 }
 141
 142 unsigned int
 143 TimingSimpleCPU::drain(Event *drain_event)
 144 {
 145     // TimingSimpleCPU is ready to drain if it's not waiting for
 146     // an access to complete.
 147     if (status() == Idle || status() == Running || status() == SwitchedOut) {
 148         changeState(SimObject::Drained);
 149         return 0;
 150     } else {
 151         changeState(SimObject::Draining);
 152         drainEvent = drain_event;
 153         return 1;
 154     }
 155 }
 156
 157 void
 158 TimingSimpleCPU::resume()
 159 {
 160     if (_status != SwitchedOut && _status != Idle) {
 161         assert(system->getMemoryMode() == System::Timing);
 162
 163         // Delete the old event if it existed.
 164         if (fetchEvent) {
 165             if (fetchEvent->scheduled())
 166                 fetchEvent->deschedule();
 167
 168             delete fetchEvent;
 169         }
 170
 171         fetchEvent = new FetchEvent(this, nextCycle());
 172     }
 173
 174     changeState(SimObject::Running);
 175     previousTick = curTick;
 176 }
 177
 178 void
 179 TimingSimpleCPU::switchOut()
 180 {
 181     assert(status() == Running || status() == Idle);
 182     _status = SwitchedOut;
 183     numCycles += curTick - previousTick;
 184
 185     // If we've been scheduled to resume but are then told to switch out,
 186     // we'll need to cancel it.
 187     if (fetchEvent && fetchEvent->scheduled())
 188         fetchEvent->deschedule();
 189 }
 190
 191
 192 void
 193 TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
 194 {
 195     BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort);
 196
 197     // if any of this CPU's ThreadContexts are active, mark the CPU as
 198     // running and schedule its tick event.
 199     for (int i = 0; i < threadContexts.size(); ++i) {
 200         ThreadContext *tc = threadContexts[i];
 201         if (tc->status() == ThreadContext::Active && _status != Running) {
 202             _status = Running;
 203             break;
 204         }
 205     }
 206
 207     if (_status != Running) {
 208         _status = Idle;
 209     }
 210 }
 211
 212
 213 void
 214 TimingSimpleCPU::activateContext(int thread_num, int delay)
 215 {
 216     assert(thread_num == 0);
 217     assert(thread);
 218
 219     assert(_status == Idle);
 220
 221     notIdleFraction++;
 222     _status = Running;
 223
 224     // kick things off by initiating the fetch of the next instruction
 225     fetchEvent = new FetchEvent(this, nextCycle(curTick + cycles(delay)));
 226 }
 227
 228
 229 void
 230 TimingSimpleCPU::suspendContext(int thread_num)
 231 {
 232     assert(thread_num == 0);
 233     assert(thread);
 234
 235     assert(_status == Running);
 236
 237     // just change status to Idle... if status != Running,
 238     // completeInst() will not initiate fetch of next instruction.
 239
 240     notIdleFraction--;
 241     _status = Idle;
 242 }
 243
 244
 245 template <class T>
 246 Fault
 247 TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
 248 {
 249     Request *req =
 250         new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
 251                     cpu_id, /* thread ID */ 0);
 252
 253     if (traceData) {
 254         traceData->setAddr(req->getVaddr());
 255     }
 256
 257    // translate to physical address
 258     Fault fault = thread->translateDataReadReq(req);
 259
 260     // Now do the access.
 261     if (fault == NoFault) {
 262         PacketPtr pkt =
 263             new Packet(req,
 264                        (req->isLocked() ?
 265                         MemCmd::LoadLockedReq : MemCmd::ReadReq),
 266                        Packet::Broadcast);
 267         pkt->dataDynamic<T>(new T);
 268
 269         if (!dcachePort.sendTiming(pkt)) {
 270             _status = DcacheRetry;
 271             dcache_pkt = pkt;
 272         } else {
 273             _status = DcacheWaitResponse;
 274             // memory system takes ownership of packet
 275             dcache_pkt = NULL;
 276         }
 277
 278         // This will need a new way to tell if it has a dcache attached.
 279         if (req->isUncacheable())
 280             recordEvent("Uncached Read");
 281     } else {
 282         delete req;
 283     }
 284
 285     return fault;
 286 }
 287
 288 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 289
 290 template
 291 Fault
 292 TimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);
 293
 294 template
 295 Fault
 296 TimingSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags);
 297
 298 template
 299 Fault
 300 TimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
 301
 302 template
 303 Fault
 304 TimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
 305
 306 template
 307 Fault
 308 TimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
 309
 310 template
 311 Fault
 312 TimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
 313
 314 #endif //DOXYGEN_SHOULD_SKIP_THIS
 315
 316 template<>
 317 Fault
 318 TimingSimpleCPU::read(Addr addr, double &data, unsigned flags)
 319 {
 320     return read(addr, *(uint64_t*)&data, flags);
 321 }
 322
 323 template<>
 324 Fault
 325 TimingSimpleCPU::read(Addr addr, float &data, unsigned flags)
 326 {
 327     return read(addr, *(uint32_t*)&data, flags);
 328 }
 329
 330
 331 template<>
 332 Fault
 333 TimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
 334 {
 335     return read(addr, (uint32_t&)data, flags);
 336 }
 337
 338
 339 template <class T>
 340 Fault
 341 TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
 342 {
 343     Request *req =
 344         new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
 345                     cpu_id, /* thread ID */ 0);
 346
 347     if (traceData) {
 348         traceData->setAddr(req->getVaddr());
 349     }
 350
 351     // translate to physical address
 352     Fault fault = thread->translateDataWriteReq(req);
 353
 354     // Now do the access.
 355     if (fault == NoFault) {
 356         MemCmd cmd = MemCmd::WriteReq; // default
 357         bool do_access = true;  // flag to suppress cache access
 358
 359         assert(dcache_pkt == NULL);
 360
 361         if (req->isLocked()) {
 362             cmd = MemCmd::StoreCondReq;
 363             do_access = TheISA::handleLockedWrite(thread, req);
 364         } else if (req->isSwap()) {
 365             cmd = MemCmd::SwapReq;
 366             if (req->isCondSwap()) {
 367                 assert(res);
 368                 req->setExtraData(*res);
 369             }
 370         }
 371
 372         if (do_access) {
 373             dcache_pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast);
 374             dcache_pkt->allocate();
 375             dcache_pkt->set(data);
 376
 377             if (!dcachePort.sendTiming(dcache_pkt)) {
 378                 _status = DcacheRetry;
 379             } else {
 380                 _status = DcacheWaitResponse;
 381                 // memory system takes ownership of packet
 382                 dcache_pkt = NULL;
 383             }
 384         }
 385         // This will need a new way to tell if it's hooked up to a cache or not.
 386         if (req->isUncacheable())
 387             recordEvent("Uncached Write");
 388     } else {
 389         delete req;
 390     }
 391
 392
 393     // If the write needs to have a fault on the access, consider calling
 394     // changeStatus() and changing it to "bad addr write" or something.
 395     return fault;
 396 }
 397
 398
 399 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 400 template
 401 Fault
 402 TimingSimpleCPU::write(Twin32_t data, Addr addr,
 403                        unsigned flags, uint64_t *res);
 404
 405 template
 406 Fault
 407 TimingSimpleCPU::write(Twin64_t data, Addr addr,
 408                        unsigned flags, uint64_t *res);
 409
 410 template
 411 Fault
 412 TimingSimpleCPU::write(uint64_t data, Addr addr,
 413                        unsigned flags, uint64_t *res);
 414
 415 template
 416 Fault
 417 TimingSimpleCPU::write(uint32_t data, Addr addr,
 418                        unsigned flags, uint64_t *res);
 419
 420 template
 421 Fault
 422 TimingSimpleCPU::write(uint16_t data, Addr addr,
 423                        unsigned flags, uint64_t *res);
 424
 425 template
 426 Fault
 427 TimingSimpleCPU::write(uint8_t data, Addr addr,
 428                        unsigned flags, uint64_t *res);
 429
 430 #endif //DOXYGEN_SHOULD_SKIP_THIS
 431
 432 template<>
 433 Fault
 434 TimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
 435 {
 436     return write(*(uint64_t*)&data, addr, flags, res);
 437 }
 438
 439 template<>
 440 Fault
 441 TimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
 442 {
 443     return write(*(uint32_t*)&data, addr, flags, res);
 444 }
 445
 446
 447 template<>
 448 Fault
 449 TimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
 450 {
 451     return write((uint32_t)data, addr, flags, res);
 452 }
 453
 454
 455 void
 456 TimingSimpleCPU::fetch()
 457 {
 458     if (!curStaticInst || !curStaticInst->isDelayedCommit())
 459         checkForInterrupts();
 460
 461     Request *ifetch_req = new Request();
 462     ifetch_req->setThreadContext(cpu_id, /* thread ID */ 0);
 463     Fault fault = setupFetchRequest(ifetch_req);
 464
 465     ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast);
 466     ifetch_pkt->dataStatic(&inst);
 467
 468     if (fault == NoFault) {
 469         if (!icachePort.sendTiming(ifetch_pkt)) {
 470             // Need to wait for retry
 471             _status = IcacheRetry;
 472         } else {
 473             // Need to wait for cache to respond
 474             _status = IcacheWaitResponse;
 475             // ownership of packet transferred to memory system
 476             ifetch_pkt = NULL;
 477         }
 478     } else {
 479         delete ifetch_req;
 480         delete ifetch_pkt;
 481         // fetch fault: advance directly to next instruction (fault handler)
 482         advanceInst(fault);
 483     }
 484
 485     numCycles += curTick - previousTick;
 486     previousTick = curTick;
 487 }
 488
 489
 490 void
 491 TimingSimpleCPU::advanceInst(Fault fault)
 492 {
 493     advancePC(fault);
 494
 495     if (_status == Running) {
 496         // kick off fetch of next instruction... callback from icache
 497         // response will cause that instruction to be executed,
 498         // keeping the CPU running.
 499         fetch();
 500     }
 501 }
 502
 503
 504 void
 505 TimingSimpleCPU::completeIfetch(PacketPtr pkt)
 506 {
 507     // received a response from the icache: execute the received
 508     // instruction
 509     assert(!pkt->isError());
 510     assert(_status == IcacheWaitResponse);
 511
 512     _status = Running;
 513
 514     numCycles += curTick - previousTick;
 515     previousTick = curTick;
 516
 517     if (getState() == SimObject::Draining) {
 518         delete pkt->req;
 519         delete pkt;
 520
 521         completeDrain();
 522         return;
 523     }
 524
 525     preExecute();
 526     if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) {
 527         // load or store: just send to dcache
 528         Fault fault = curStaticInst->initiateAcc(this, traceData);
 529         if (_status != Running) {
 530             // instruction will complete in dcache response callback
 531             assert(_status == DcacheWaitResponse || _status == DcacheRetry);
 532             assert(fault == NoFault);
 533         } else {
 534             if (fault == NoFault) {
 535                 // early fail on store conditional: complete now
 536                 assert(dcache_pkt != NULL);
 537                 fault = curStaticInst->completeAcc(dcache_pkt, this,
 538                                                    traceData);
 539                 delete dcache_pkt->req;
 540                 delete dcache_pkt;
 541                 dcache_pkt = NULL;
 542             }
 543             postExecute();
 544             advanceInst(fault);
 545         }
 546     } else {
 547         // non-memory instruction: execute completely now
 548         Fault fault = curStaticInst->execute(this, traceData);
 549         postExecute();
 550         advanceInst(fault);
 551     }
 552
 553     delete pkt->req;
 554     delete pkt;
 555 }
 556
 557 void
 558 TimingSimpleCPU::IcachePort::ITickEvent::process()
 559 {
 560     cpu->completeIfetch(pkt);
 561 }
 562
 563 bool
 564 TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
 565 {
 566     if (pkt->isResponse()) {
 567         // delay processing of returned data until next CPU clock edge
 568         Tick next_tick = cpu->nextCycle(curTick);
 569
 570         if (next_tick == curTick)
 571             cpu->completeIfetch(pkt);
 572         else
 573             tickEvent.schedule(pkt, next_tick);
 574
 575         return true;
 576     }
 577     else if (pkt->wasNacked()) {
 578         assert(cpu->_status == IcacheWaitResponse);
 579         pkt->reinitNacked();
 580         if (!sendTiming(pkt)) {
 581             cpu->_status = IcacheRetry;
 582             cpu->ifetch_pkt = pkt;
 583         }
 584     }
 585     //Snooping a Coherence Request, do nothing
 586     return true;
 587 }
 588
 589 void
 590 TimingSimpleCPU::IcachePort::recvRetry()
 591 {
 592     // we shouldn't get a retry unless we have a packet that we're
 593     // waiting to transmit
 594     assert(cpu->ifetch_pkt != NULL);
 595     assert(cpu->_status == IcacheRetry);
 596     PacketPtr tmp = cpu->ifetch_pkt;
 597     if (sendTiming(tmp)) {
 598         cpu->_status = IcacheWaitResponse;
 599         cpu->ifetch_pkt = NULL;
 600     }
 601 }
 602
 603 void
 604 TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
 605 {
 606     // received a response from the dcache: complete the load or store
 607     // instruction
 608     assert(!pkt->isError());
 609     assert(_status == DcacheWaitResponse);
 610     _status = Running;
 611
 612     numCycles += curTick - previousTick;
 613     previousTick = curTick;
 614
 615     Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
 616
 617     if (pkt->isRead() && pkt->isLocked()) {
 618         TheISA::handleLockedRead(thread, pkt->req);
 619     }
 620
 621     delete pkt->req;
 622     delete pkt;
 623
 624     postExecute();
 625
 626     if (getState() == SimObject::Draining) {
 627         advancePC(fault);
 628         completeDrain();
 629
 630         return;
 631     }
 632
 633     advanceInst(fault);
 634 }
 635
 636
 637 void
 638 TimingSimpleCPU::completeDrain()
 639 {
 640     DPRINTF(Config, "Done draining\n");
 641     changeState(SimObject::Drained);
 642     drainEvent->process();
 643 }
 644
 645 void
 646 TimingSimpleCPU::DcachePort::setPeer(Port *port)
 647 {
 648     Port::setPeer(port);
 649
 650 #if FULL_SYSTEM
 651     // Update the ThreadContext's memory ports (Functional/Virtual
 652     // Ports)
 653     cpu->tcBase()->connectMemPorts();
 654 #endif
 655 }
 656
 657 bool
 658 TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
 659 {
 660     if (pkt->isResponse()) {
 661         // delay processing of returned data until next CPU clock edge
 662         Tick next_tick = cpu->nextCycle(curTick);
 663
 664         if (next_tick == curTick)
 665             cpu->completeDataAccess(pkt);
 666         else
 667             tickEvent.schedule(pkt, next_tick);
 668
 669         return true;
 670     }
 671     else if (pkt->wasNacked()) {
 672         assert(cpu->_status == DcacheWaitResponse);
 673         pkt->reinitNacked();
 674         if (!sendTiming(pkt)) {
 675             cpu->_status = DcacheRetry;
 676             cpu->dcache_pkt = pkt;
 677         }
 678     }
 679     //Snooping a Coherence Request, do nothing
 680     return true;
 681 }
 682
 683 void
 684 TimingSimpleCPU::DcachePort::DTickEvent::process()
 685 {
 686     cpu->completeDataAccess(pkt);
 687 }
 688
 689 void
 690 TimingSimpleCPU::DcachePort::recvRetry()
 691 {
 692     // we shouldn't get a retry unless we have a packet that we're
 693     // waiting to transmit
 694     assert(cpu->dcache_pkt != NULL);
 695     assert(cpu->_status == DcacheRetry);
 696     PacketPtr tmp = cpu->dcache_pkt;
 697     if (sendTiming(tmp)) {
 698         cpu->_status = DcacheWaitResponse;
 699         // memory system takes ownership of packet
 700         cpu->dcache_pkt = NULL;
 701     }
 702 }
 703
 704
 705 ////////////////////////////////////////////////////////////////////////
 706 //
 707 //  TimingSimpleCPU Simulation Object
 708 //
 709 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU)
 710
 711     Param<Counter> max_insts_any_thread;
 712     Param<Counter> max_insts_all_threads;
 713     Param<Counter> max_loads_any_thread;
 714     Param<Counter> max_loads_all_threads;
 715     Param<Tick> progress_interval;
 716     SimObjectParam<System *> system;
 717     Param<int> cpu_id;
 718
 719 #if FULL_SYSTEM
 720     SimObjectParam<TheISA::ITB *> itb;
 721     SimObjectParam<TheISA::DTB *> dtb;
 722     Param<Tick> profile;
 723
 724     Param<bool> do_quiesce;
 725     Param<bool> do_checkpoint_insts;
 726     Param<bool> do_statistics_insts;
 727 #else
 728     SimObjectParam<Process *> workload;
 729 #endif // FULL_SYSTEM
 730
 731     Param<int> clock;
 732     Param<int> phase;
 733
 734     Param<bool> defer_registration;
 735     Param<int> width;
 736     Param<bool> function_trace;
 737     Param<Tick> function_trace_start;
 738     Param<bool> simulate_stalls;
 739
 740 END_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU)
 741
 742 BEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU)
 743
 744     INIT_PARAM(max_insts_any_thread,
 745                "terminate when any thread reaches this inst count"),
 746     INIT_PARAM(max_insts_all_threads,
 747                "terminate when all threads have reached this inst count"),
 748     INIT_PARAM(max_loads_any_thread,
 749                "terminate when any thread reaches this load count"),
 750     INIT_PARAM(max_loads_all_threads,
 751                "terminate when all threads have reached this load count"),
 752     INIT_PARAM(progress_interval, "Progress interval"),
 753     INIT_PARAM(system, "system object"),
 754     INIT_PARAM(cpu_id, "processor ID"),
 755
 756 #if FULL_SYSTEM
 757     INIT_PARAM(itb, "Instruction TLB"),
 758     INIT_PARAM(dtb, "Data TLB"),
 759     INIT_PARAM(profile, ""),
 760     INIT_PARAM(do_quiesce, ""),
 761     INIT_PARAM(do_checkpoint_insts, ""),
 762     INIT_PARAM(do_statistics_insts, ""),
 763 #else
 764     INIT_PARAM(workload, "processes to run"),
 765 #endif // FULL_SYSTEM
 766
 767     INIT_PARAM(clock, "clock speed"),
 768     INIT_PARAM_DFLT(phase, "clock phase", 0),
 769     INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
 770     INIT_PARAM(width, "cpu width"),
 771     INIT_PARAM(function_trace, "Enable function trace"),
 772     INIT_PARAM(function_trace_start, "Cycle to start function trace"),
 773     INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
 774
 775 END_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU)
 776
 777
 778 CREATE_SIM_OBJECT(TimingSimpleCPU)
 779 {
 780     TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params();
 781     params->name = getInstanceName();
 782     params->numberOfThreads = 1;
 783     params->max_insts_any_thread = max_insts_any_thread;
 784     params->max_insts_all_threads = max_insts_all_threads;
 785     params->max_loads_any_thread = max_loads_any_thread;
 786     params->max_loads_all_threads = max_loads_all_threads;
 787     params->progress_interval = progress_interval;
 788     params->deferRegistration = defer_registration;
 789     params->clock = clock;
 790     params->phase = phase;
 791     params->functionTrace = function_trace;
 792     params->functionTraceStart = function_trace_start;
 793     params->system = system;
 794     params->cpu_id = cpu_id;
 795
 796 #if FULL_SYSTEM
 797     params->itb = itb;
 798     params->dtb = dtb;
 799     params->profile = profile;
 800     params->do_quiesce = do_quiesce;
 801     params->do_checkpoint_insts = do_checkpoint_insts;
 802     params->do_statistics_insts = do_statistics_insts;
 803 #else
 804     params->process = workload;
 805 #endif
 806
 807     TimingSimpleCPU *cpu = new TimingSimpleCPU(params);
 808     return cpu;
 809 }
 810
 811 REGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU)
 812