src/cpu/simple/timing.cc

   1 /*
   2  * Copyright (c) 2010-2012 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Steve Reinhardt
  41  */
  42
  43 #include "arch/locked_mem.hh"
  44 #include "arch/mmapped_ipr.hh"
  45 #include "arch/utility.hh"
  46 #include "base/bigint.hh"
  47 #include "config/the_isa.hh"
  48 #include "cpu/simple/timing.hh"
  49 #include "cpu/exetrace.hh"
  50 #include "debug/Config.hh"
  51 #include "debug/ExecFaulting.hh"
  52 #include "debug/SimpleCPU.hh"
  53 #include "mem/packet.hh"
  54 #include "mem/packet_access.hh"
  55 #include "params/TimingSimpleCPU.hh"
  56 #include "sim/faults.hh"
  57 #include "sim/full_system.hh"
  58 #include "sim/system.hh"
  59
  60 using namespace std;
  61 using namespace TheISA;
  62
  63 void
  64 TimingSimpleCPU::init()
  65 {
  66     BaseCPU::init();
  67
  68     // Initialise the ThreadContext's memory proxies
  69     tcBase()->initMemProxies(tcBase());
  70
  71     if (FullSystem && !params()->defer_registration) {
  72         for (int i = 0; i < threadContexts.size(); ++i) {
  73             ThreadContext *tc = threadContexts[i];
  74             // initialize CPU, including PC
  75             TheISA::initCPU(tc, _cpuId);
  76         }
  77     }
  78 }
  79
  80 void
  81 TimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
  82 {
  83     pkt = _pkt;
  84     cpu->schedule(this, t);
  85 }
  86
  87 TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p)
  88     : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this),
  89     dcachePort(this), fetchEvent(this)
  90 {
  91     _status = Idle;
  92
  93     ifetch_pkt = dcache_pkt = NULL;
  94     drainEvent = NULL;
  95     previousTick = 0;
  96     changeState(SimObject::Running);
  97     system->totalNumInsts = 0;
  98 }
  99
 100
 101 TimingSimpleCPU::~TimingSimpleCPU()
 102 {
 103 }
 104
 105 void
 106 TimingSimpleCPU::serialize(ostream &os)
 107 {
 108     SimObject::State so_state = SimObject::getState();
 109     SERIALIZE_ENUM(so_state);
 110     BaseSimpleCPU::serialize(os);
 111 }
 112
 113 void
 114 TimingSimpleCPU::unserialize(Checkpoint *cp, const string &section)
 115 {
 116     SimObject::State so_state;
 117     UNSERIALIZE_ENUM(so_state);
 118     BaseSimpleCPU::unserialize(cp, section);
 119 }
 120
 121 unsigned int
 122 TimingSimpleCPU::drain(Event *drain_event)
 123 {
 124     // TimingSimpleCPU is ready to drain if it's not waiting for
 125     // an access to complete.
 126     if (_status == Idle || _status == Running || _status == SwitchedOut) {
 127         changeState(SimObject::Drained);
 128         return 0;
 129     } else {
 130         changeState(SimObject::Draining);
 131         drainEvent = drain_event;
 132         return 1;
 133     }
 134 }
 135
 136 void
 137 TimingSimpleCPU::resume()
 138 {
 139     DPRINTF(SimpleCPU, "Resume\n");
 140     if (_status != SwitchedOut && _status != Idle) {
 141         assert(system->getMemoryMode() == Enums::timing);
 142
 143         if (fetchEvent.scheduled())
 144            deschedule(fetchEvent);
 145
 146         schedule(fetchEvent, nextCycle());
 147     }
 148
 149     changeState(SimObject::Running);
 150 }
 151
 152 void
 153 TimingSimpleCPU::switchOut()
 154 {
 155     assert(_status == Running || _status == Idle);
 156     _status = SwitchedOut;
 157     numCycles += tickToCycles(curTick() - previousTick);
 158
 159     // If we've been scheduled to resume but are then told to switch out,
 160     // we'll need to cancel it.
 161     if (fetchEvent.scheduled())
 162         deschedule(fetchEvent);
 163 }
 164
 165
 166 void
 167 TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
 168 {
 169     BaseCPU::takeOverFrom(oldCPU);
 170
 171     // if any of this CPU's ThreadContexts are active, mark the CPU as
 172     // running and schedule its tick event.
 173     for (int i = 0; i < threadContexts.size(); ++i) {
 174         ThreadContext *tc = threadContexts[i];
 175         if (tc->status() == ThreadContext::Active && _status != Running) {
 176             _status = Running;
 177             break;
 178         }
 179     }
 180
 181     if (_status != Running) {
 182         _status = Idle;
 183     }
 184     assert(threadContexts.size() == 1);
 185     previousTick = curTick();
 186 }
 187
 188
 189 void
 190 TimingSimpleCPU::activateContext(ThreadID thread_num, int delay)
 191 {
 192     DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
 193
 194     assert(thread_num == 0);
 195     assert(thread);
 196
 197     assert(_status == Idle);
 198
 199     notIdleFraction++;
 200     _status = Running;
 201
 202     // kick things off by initiating the fetch of the next instruction
 203     schedule(fetchEvent, nextCycle(curTick() + ticks(delay)));
 204 }
 205
 206
 207 void
 208 TimingSimpleCPU::suspendContext(ThreadID thread_num)
 209 {
 210     DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
 211
 212     assert(thread_num == 0);
 213     assert(thread);
 214
 215     if (_status == Idle)
 216         return;
 217
 218     assert(_status == Running);
 219
 220     // just change status to Idle... if status != Running,
 221     // completeInst() will not initiate fetch of next instruction.
 222
 223     notIdleFraction--;
 224     _status = Idle;
 225 }
 226
 227 bool
 228 TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
 229 {
 230     RequestPtr req = pkt->req;
 231     if (req->isMmappedIpr()) {
 232         Tick delay;
 233         delay = TheISA::handleIprRead(thread->getTC(), pkt);
 234         new IprEvent(pkt, this, nextCycle(curTick() + delay));
 235         _status = DcacheWaitResponse;
 236         dcache_pkt = NULL;
 237     } else if (!dcachePort.sendTimingReq(pkt)) {
 238         _status = DcacheRetry;
 239         dcache_pkt = pkt;
 240     } else {
 241         _status = DcacheWaitResponse;
 242         // memory system takes ownership of packet
 243         dcache_pkt = NULL;
 244     }
 245     return dcache_pkt == NULL;
 246 }
 247
 248 void
 249 TimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res,
 250                           bool read)
 251 {
 252     PacketPtr pkt;
 253     buildPacket(pkt, req, read);
 254     pkt->dataDynamicArray<uint8_t>(data);
 255     if (req->getFlags().isSet(Request::NO_ACCESS)) {
 256         assert(!dcache_pkt);
 257         pkt->makeResponse();
 258         completeDataAccess(pkt);
 259     } else if (read) {
 260         handleReadPacket(pkt);
 261     } else {
 262         bool do_access = true;  // flag to suppress cache access
 263
 264         if (req->isLLSC()) {
 265             do_access = TheISA::handleLockedWrite(thread, req);
 266         } else if (req->isCondSwap()) {
 267             assert(res);
 268             req->setExtraData(*res);
 269         }
 270
 271         if (do_access) {
 272             dcache_pkt = pkt;
 273             handleWritePacket();
 274         } else {
 275             _status = DcacheWaitResponse;
 276             completeDataAccess(pkt);
 277         }
 278     }
 279 }
 280
 281 void
 282 TimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2,
 283                                RequestPtr req, uint8_t *data, bool read)
 284 {
 285     PacketPtr pkt1, pkt2;
 286     buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read);
 287     if (req->getFlags().isSet(Request::NO_ACCESS)) {
 288         assert(!dcache_pkt);
 289         pkt1->makeResponse();
 290         completeDataAccess(pkt1);
 291     } else if (read) {
 292         SplitFragmentSenderState * send_state =
 293             dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
 294         if (handleReadPacket(pkt1)) {
 295             send_state->clearFromParent();
 296             send_state = dynamic_cast<SplitFragmentSenderState *>(
 297                     pkt2->senderState);
 298             if (handleReadPacket(pkt2)) {
 299                 send_state->clearFromParent();
 300             }
 301         }
 302     } else {
 303         dcache_pkt = pkt1;
 304         SplitFragmentSenderState * send_state =
 305             dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
 306         if (handleWritePacket()) {
 307             send_state->clearFromParent();
 308             dcache_pkt = pkt2;
 309             send_state = dynamic_cast<SplitFragmentSenderState *>(
 310                     pkt2->senderState);
 311             if (handleWritePacket()) {
 312                 send_state->clearFromParent();
 313             }
 314         }
 315     }
 316 }
 317
 318 void
 319 TimingSimpleCPU::translationFault(Fault fault)
 320 {
 321     // fault may be NoFault in cases where a fault is suppressed,
 322     // for instance prefetches.
 323     numCycles += tickToCycles(curTick() - previousTick);
 324     previousTick = curTick();
 325
 326     if (traceData) {
 327         // Since there was a fault, we shouldn't trace this instruction.
 328         delete traceData;
 329         traceData = NULL;
 330     }
 331
 332     postExecute();
 333
 334     if (getState() == SimObject::Draining) {
 335         advancePC(fault);
 336         completeDrain();
 337     } else {
 338         advanceInst(fault);
 339     }
 340 }
 341
 342 void
 343 TimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read)
 344 {
 345     MemCmd cmd;
 346     if (read) {
 347         cmd = MemCmd::ReadReq;
 348         if (req->isLLSC())
 349             cmd = MemCmd::LoadLockedReq;
 350     } else {
 351         cmd = MemCmd::WriteReq;
 352         if (req->isLLSC()) {
 353             cmd = MemCmd::StoreCondReq;
 354         } else if (req->isSwap()) {
 355             cmd = MemCmd::SwapReq;
 356         }
 357     }
 358     pkt = new Packet(req, cmd);
 359 }
 360
 361 void
 362 TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
 363         RequestPtr req1, RequestPtr req2, RequestPtr req,
 364         uint8_t *data, bool read)
 365 {
 366     pkt1 = pkt2 = NULL;
 367
 368     assert(!req1->isMmappedIpr() && !req2->isMmappedIpr());
 369
 370     if (req->getFlags().isSet(Request::NO_ACCESS)) {
 371         buildPacket(pkt1, req, read);
 372         return;
 373     }
 374
 375     buildPacket(pkt1, req1, read);
 376     buildPacket(pkt2, req2, read);
 377
 378     req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags(), dataMasterId());
 379     PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand());
 380
 381     pkt->dataDynamicArray<uint8_t>(data);
 382     pkt1->dataStatic<uint8_t>(data);
 383     pkt2->dataStatic<uint8_t>(data + req1->getSize());
 384
 385     SplitMainSenderState * main_send_state = new SplitMainSenderState;
 386     pkt->senderState = main_send_state;
 387     main_send_state->fragments[0] = pkt1;
 388     main_send_state->fragments[1] = pkt2;
 389     main_send_state->outstanding = 2;
 390     pkt1->senderState = new SplitFragmentSenderState(pkt, 0);
 391     pkt2->senderState = new SplitFragmentSenderState(pkt, 1);
 392 }
 393
 394 Fault
 395 TimingSimpleCPU::readMem(Addr addr, uint8_t *data,
 396                          unsigned size, unsigned flags)
 397 {
 398     Fault fault;
 399     const int asid = 0;
 400     const ThreadID tid = 0;
 401     const Addr pc = thread->instAddr();
 402     unsigned block_size = dcachePort.peerBlockSize();
 403     BaseTLB::Mode mode = BaseTLB::Read;
 404
 405     if (traceData) {
 406         traceData->setAddr(addr);
 407     }
 408
 409     RequestPtr req  = new Request(asid, addr, size,
 410                                   flags, dataMasterId(), pc, _cpuId, tid);
 411
 412     Addr split_addr = roundDown(addr + size - 1, block_size);
 413     assert(split_addr <= addr || split_addr - addr < block_size);
 414
 415     _status = DTBWaitResponse;
 416     if (split_addr > addr) {
 417         RequestPtr req1, req2;
 418         assert(!req->isLLSC() && !req->isSwap());
 419         req->splitOnVaddr(split_addr, req1, req2);
 420
 421         WholeTranslationState *state =
 422             new WholeTranslationState(req, req1, req2, new uint8_t[size],
 423                                       NULL, mode);
 424         DataTranslation<TimingSimpleCPU *> *trans1 =
 425             new DataTranslation<TimingSimpleCPU *>(this, state, 0);
 426         DataTranslation<TimingSimpleCPU *> *trans2 =
 427             new DataTranslation<TimingSimpleCPU *>(this, state, 1);
 428
 429         thread->dtb->translateTiming(req1, tc, trans1, mode);
 430         thread->dtb->translateTiming(req2, tc, trans2, mode);
 431     } else {
 432         WholeTranslationState *state =
 433             new WholeTranslationState(req, new uint8_t[size], NULL, mode);
 434         DataTranslation<TimingSimpleCPU *> *translation
 435             = new DataTranslation<TimingSimpleCPU *>(this, state);
 436         thread->dtb->translateTiming(req, tc, translation, mode);
 437     }
 438
 439     return NoFault;
 440 }
 441
 442 bool
 443 TimingSimpleCPU::handleWritePacket()
 444 {
 445     RequestPtr req = dcache_pkt->req;
 446     if (req->isMmappedIpr()) {
 447         Tick delay;
 448         delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
 449         new IprEvent(dcache_pkt, this, nextCycle(curTick() + delay));
 450         _status = DcacheWaitResponse;
 451         dcache_pkt = NULL;
 452     } else if (!dcachePort.sendTimingReq(dcache_pkt)) {
 453         _status = DcacheRetry;
 454     } else {
 455         _status = DcacheWaitResponse;
 456         // memory system takes ownership of packet
 457         dcache_pkt = NULL;
 458     }
 459     return dcache_pkt == NULL;
 460 }
 461
 462 Fault
 463 TimingSimpleCPU::writeMem(uint8_t *data, unsigned size,
 464                           Addr addr, unsigned flags, uint64_t *res)
 465 {
 466     uint8_t *newData = new uint8_t[size];
 467     memcpy(newData, data, size);
 468
 469     const int asid = 0;
 470     const ThreadID tid = 0;
 471     const Addr pc = thread->instAddr();
 472     unsigned block_size = dcachePort.peerBlockSize();
 473     BaseTLB::Mode mode = BaseTLB::Write;
 474
 475     if (traceData) {
 476         traceData->setAddr(addr);
 477     }
 478
 479     RequestPtr req = new Request(asid, addr, size,
 480                                  flags, dataMasterId(), pc, _cpuId, tid);
 481
 482     Addr split_addr = roundDown(addr + size - 1, block_size);
 483     assert(split_addr <= addr || split_addr - addr < block_size);
 484
 485     _status = DTBWaitResponse;
 486     if (split_addr > addr) {
 487         RequestPtr req1, req2;
 488         assert(!req->isLLSC() && !req->isSwap());
 489         req->splitOnVaddr(split_addr, req1, req2);
 490
 491         WholeTranslationState *state =
 492             new WholeTranslationState(req, req1, req2, newData, res, mode);
 493         DataTranslation<TimingSimpleCPU *> *trans1 =
 494             new DataTranslation<TimingSimpleCPU *>(this, state, 0);
 495         DataTranslation<TimingSimpleCPU *> *trans2 =
 496             new DataTranslation<TimingSimpleCPU *>(this, state, 1);
 497
 498         thread->dtb->translateTiming(req1, tc, trans1, mode);
 499         thread->dtb->translateTiming(req2, tc, trans2, mode);
 500     } else {
 501         WholeTranslationState *state =
 502             new WholeTranslationState(req, newData, res, mode);
 503         DataTranslation<TimingSimpleCPU *> *translation =
 504             new DataTranslation<TimingSimpleCPU *>(this, state);
 505         thread->dtb->translateTiming(req, tc, translation, mode);
 506     }
 507
 508     // Translation faults will be returned via finishTranslation()
 509     return NoFault;
 510 }
 511
 512
 513 void
 514 TimingSimpleCPU::finishTranslation(WholeTranslationState *state)
 515 {
 516     _status = Running;
 517
 518     if (state->getFault() != NoFault) {
 519         if (state->isPrefetch()) {
 520             state->setNoFault();
 521         }
 522         delete [] state->data;
 523         state->deleteReqs();
 524         translationFault(state->getFault());
 525     } else {
 526         if (!state->isSplit) {
 527             sendData(state->mainReq, state->data, state->res,
 528                      state->mode == BaseTLB::Read);
 529         } else {
 530             sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq,
 531                           state->data, state->mode == BaseTLB::Read);
 532         }
 533     }
 534
 535     delete state;
 536 }
 537
 538
 539 void
 540 TimingSimpleCPU::fetch()
 541 {
 542     DPRINTF(SimpleCPU, "Fetch\n");
 543
 544     if (!curStaticInst || !curStaticInst->isDelayedCommit())
 545         checkForInterrupts();
 546
 547     checkPcEventQueue();
 548
 549     // We must have just got suspended by a PC event
 550     if (_status == Idle)
 551         return;
 552
 553     TheISA::PCState pcState = thread->pcState();
 554     bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst;
 555
 556     if (needToFetch) {
 557         _status = Running;
 558         Request *ifetch_req = new Request();
 559         ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
 560         setupFetchRequest(ifetch_req);
 561         DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr());
 562         thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation,
 563                 BaseTLB::Execute);
 564     } else {
 565         _status = IcacheWaitResponse;
 566         completeIfetch(NULL);
 567
 568         numCycles += tickToCycles(curTick() - previousTick);
 569         previousTick = curTick();
 570     }
 571 }
 572
 573
 574 void
 575 TimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc)
 576 {
 577     if (fault == NoFault) {
 578         DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n",
 579                 req->getVaddr(), req->getPaddr());
 580         ifetch_pkt = new Packet(req, MemCmd::ReadReq);
 581         ifetch_pkt->dataStatic(&inst);
 582         DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr());
 583
 584         if (!icachePort.sendTimingReq(ifetch_pkt)) {
 585             // Need to wait for retry
 586             _status = IcacheRetry;
 587         } else {
 588             // Need to wait for cache to respond
 589             _status = IcacheWaitResponse;
 590             // ownership of packet transferred to memory system
 591             ifetch_pkt = NULL;
 592         }
 593     } else {
 594         DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr());
 595         delete req;
 596         // fetch fault: advance directly to next instruction (fault handler)
 597         _status = Running;
 598         advanceInst(fault);
 599     }
 600
 601     numCycles += tickToCycles(curTick() - previousTick);
 602     previousTick = curTick();
 603 }
 604
 605
 606 void
 607 TimingSimpleCPU::advanceInst(Fault fault)
 608 {
 609
 610     if (_status == Faulting)
 611         return;
 612
 613     if (fault != NoFault) {
 614         advancePC(fault);
 615         DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n");
 616         reschedule(fetchEvent, nextCycle(), true);
 617         _status = Faulting;
 618         return;
 619     }
 620
 621
 622     if (!stayAtPC)
 623         advancePC(fault);
 624
 625     if (_status == Running) {
 626         // kick off fetch of next instruction... callback from icache
 627         // response will cause that instruction to be executed,
 628         // keeping the CPU running.
 629         fetch();
 630     }
 631 }
 632
 633
 634 void
 635 TimingSimpleCPU::completeIfetch(PacketPtr pkt)
 636 {
 637     DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ?
 638             pkt->getAddr() : 0);
 639
 640     // received a response from the icache: execute the received
 641     // instruction
 642
 643     assert(!pkt || !pkt->isError());
 644     assert(_status == IcacheWaitResponse);
 645
 646     _status = Running;
 647
 648     numCycles += tickToCycles(curTick() - previousTick);
 649     previousTick = curTick();
 650
 651     if (getState() == SimObject::Draining) {
 652         if (pkt) {
 653             delete pkt->req;
 654             delete pkt;
 655         }
 656
 657         completeDrain();
 658         return;
 659     }
 660
 661     preExecute();
 662     if (curStaticInst && curStaticInst->isMemRef()) {
 663         // load or store: just send to dcache
 664         Fault fault = curStaticInst->initiateAcc(this, traceData);
 665
 666         // If we're not running now the instruction will complete in a dcache
 667         // response callback or the instruction faulted and has started an
 668         // ifetch
 669         if (_status == Running) {
 670             if (fault != NoFault && traceData) {
 671                 // If there was a fault, we shouldn't trace this instruction.
 672                 delete traceData;
 673                 traceData = NULL;
 674             }
 675
 676             postExecute();
 677             // @todo remove me after debugging with legion done
 678             if (curStaticInst && (!curStaticInst->isMicroop() ||
 679                         curStaticInst->isFirstMicroop()))
 680                 instCnt++;
 681             advanceInst(fault);
 682         }
 683     } else if (curStaticInst) {
 684         // non-memory instruction: execute completely now
 685         Fault fault = curStaticInst->execute(this, traceData);
 686
 687         // keep an instruction count
 688         if (fault == NoFault)
 689             countInst();
 690         else if (traceData && !DTRACE(ExecFaulting)) {
 691             delete traceData;
 692             traceData = NULL;
 693         }
 694
 695         postExecute();
 696         // @todo remove me after debugging with legion done
 697         if (curStaticInst && (!curStaticInst->isMicroop() ||
 698                     curStaticInst->isFirstMicroop()))
 699             instCnt++;
 700         advanceInst(fault);
 701     } else {
 702         advanceInst(NoFault);
 703     }
 704
 705     if (pkt) {
 706         delete pkt->req;
 707         delete pkt;
 708     }
 709 }
 710
 711 void
 712 TimingSimpleCPU::IcachePort::ITickEvent::process()
 713 {
 714     cpu->completeIfetch(pkt);
 715 }
 716
 717 bool
 718 TimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt)
 719 {
 720     if (!pkt->wasNacked()) {
 721         DPRINTF(SimpleCPU, "Received timing response %#x\n", pkt->getAddr());
 722         // delay processing of returned data until next CPU clock edge
 723         Tick next_tick = cpu->nextCycle(curTick());
 724
 725         if (next_tick == curTick())
 726             cpu->completeIfetch(pkt);
 727         else
 728             tickEvent.schedule(pkt, next_tick);
 729
 730         return true;
 731     } else {
 732         assert(cpu->_status == IcacheWaitResponse);
 733         pkt->reinitNacked();
 734         if (!sendTimingReq(pkt)) {
 735             cpu->_status = IcacheRetry;
 736             cpu->ifetch_pkt = pkt;
 737         }
 738     }
 739
 740     return true;
 741 }
 742
 743 void
 744 TimingSimpleCPU::IcachePort::recvRetry()
 745 {
 746     // we shouldn't get a retry unless we have a packet that we're
 747     // waiting to transmit
 748     assert(cpu->ifetch_pkt != NULL);
 749     assert(cpu->_status == IcacheRetry);
 750     PacketPtr tmp = cpu->ifetch_pkt;
 751     if (sendTimingReq(tmp)) {
 752         cpu->_status = IcacheWaitResponse;
 753         cpu->ifetch_pkt = NULL;
 754     }
 755 }
 756
 757 void
 758 TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
 759 {
 760     // received a response from the dcache: complete the load or store
 761     // instruction
 762     assert(!pkt->isError());
 763     assert(_status == DcacheWaitResponse || _status == DTBWaitResponse ||
 764            pkt->req->getFlags().isSet(Request::NO_ACCESS));
 765
 766     numCycles += tickToCycles(curTick() - previousTick);
 767     previousTick = curTick();
 768
 769     if (pkt->senderState) {
 770         SplitFragmentSenderState * send_state =
 771             dynamic_cast<SplitFragmentSenderState *>(pkt->senderState);
 772         assert(send_state);
 773         delete pkt->req;
 774         delete pkt;
 775         PacketPtr big_pkt = send_state->bigPkt;
 776         delete send_state;
 777
 778         SplitMainSenderState * main_send_state =
 779             dynamic_cast<SplitMainSenderState *>(big_pkt->senderState);
 780         assert(main_send_state);
 781         // Record the fact that this packet is no longer outstanding.
 782         assert(main_send_state->outstanding != 0);
 783         main_send_state->outstanding--;
 784
 785         if (main_send_state->outstanding) {
 786             return;
 787         } else {
 788             delete main_send_state;
 789             big_pkt->senderState = NULL;
 790             pkt = big_pkt;
 791         }
 792     }
 793
 794     _status = Running;
 795
 796     Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
 797
 798     // keep an instruction count
 799     if (fault == NoFault)
 800         countInst();
 801     else if (traceData) {
 802         // If there was a fault, we shouldn't trace this instruction.
 803         delete traceData;
 804         traceData = NULL;
 805     }
 806
 807     // the locked flag may be cleared on the response packet, so check
 808     // pkt->req and not pkt to see if it was a load-locked
 809     if (pkt->isRead() && pkt->req->isLLSC()) {
 810         TheISA::handleLockedRead(thread, pkt->req);
 811     }
 812
 813     delete pkt->req;
 814     delete pkt;
 815
 816     postExecute();
 817
 818     if (getState() == SimObject::Draining) {
 819         advancePC(fault);
 820         completeDrain();
 821
 822         return;
 823     }
 824
 825     advanceInst(fault);
 826 }
 827
 828
 829 void
 830 TimingSimpleCPU::completeDrain()
 831 {
 832     DPRINTF(Config, "Done draining\n");
 833     changeState(SimObject::Drained);
 834     drainEvent->process();
 835 }
 836
 837 bool
 838 TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt)
 839 {
 840     if (!pkt->wasNacked()) {
 841         // delay processing of returned data until next CPU clock edge
 842         Tick next_tick = cpu->nextCycle(curTick());
 843
 844         if (next_tick == curTick()) {
 845             cpu->completeDataAccess(pkt);
 846         } else {
 847             if (!tickEvent.scheduled()) {
 848                 tickEvent.schedule(pkt, next_tick);
 849             } else {
 850                 // In the case of a split transaction and a cache that is
 851                 // faster than a CPU we could get two responses before
 852                 // next_tick expires
 853                 if (!retryEvent.scheduled())
 854                     cpu->schedule(retryEvent, next_tick);
 855                 return false;
 856             }
 857         }
 858
 859         return true;
 860     } else  {
 861         assert(cpu->_status == DcacheWaitResponse);
 862         pkt->reinitNacked();
 863         if (!sendTimingReq(pkt)) {
 864             cpu->_status = DcacheRetry;
 865             cpu->dcache_pkt = pkt;
 866         }
 867     }
 868
 869     return true;
 870 }
 871
 872 void
 873 TimingSimpleCPU::DcachePort::DTickEvent::process()
 874 {
 875     cpu->completeDataAccess(pkt);
 876 }
 877
 878 void
 879 TimingSimpleCPU::DcachePort::recvRetry()
 880 {
 881     // we shouldn't get a retry unless we have a packet that we're
 882     // waiting to transmit
 883     assert(cpu->dcache_pkt != NULL);
 884     assert(cpu->_status == DcacheRetry);
 885     PacketPtr tmp = cpu->dcache_pkt;
 886     if (tmp->senderState) {
 887         // This is a packet from a split access.
 888         SplitFragmentSenderState * send_state =
 889             dynamic_cast<SplitFragmentSenderState *>(tmp->senderState);
 890         assert(send_state);
 891         PacketPtr big_pkt = send_state->bigPkt;
 892
 893         SplitMainSenderState * main_send_state =
 894             dynamic_cast<SplitMainSenderState *>(big_pkt->senderState);
 895         assert(main_send_state);
 896
 897         if (sendTimingReq(tmp)) {
 898             // If we were able to send without retrying, record that fact
 899             // and try sending the other fragment.
 900             send_state->clearFromParent();
 901             int other_index = main_send_state->getPendingFragment();
 902             if (other_index > 0) {
 903                 tmp = main_send_state->fragments[other_index];
 904                 cpu->dcache_pkt = tmp;
 905                 if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) ||
 906                         (big_pkt->isWrite() && cpu->handleWritePacket())) {
 907                     main_send_state->fragments[other_index] = NULL;
 908                 }
 909             } else {
 910                 cpu->_status = DcacheWaitResponse;
 911                 // memory system takes ownership of packet
 912                 cpu->dcache_pkt = NULL;
 913             }
 914         }
 915     } else if (sendTimingReq(tmp)) {
 916         cpu->_status = DcacheWaitResponse;
 917         // memory system takes ownership of packet
 918         cpu->dcache_pkt = NULL;
 919     }
 920 }
 921
 922 TimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu,
 923     Tick t)
 924     : pkt(_pkt), cpu(_cpu)
 925 {
 926     cpu->schedule(this, t);
 927 }
 928
 929 void
 930 TimingSimpleCPU::IprEvent::process()
 931 {
 932     cpu->completeDataAccess(pkt);
 933 }
 934
 935 const char *
 936 TimingSimpleCPU::IprEvent::description() const
 937 {
 938     return "Timing Simple CPU Delay IPR event";
 939 }
 940
 941
 942 void
 943 TimingSimpleCPU::printAddr(Addr a)
 944 {
 945     dcachePort.printAddr(a);
 946 }
 947
 948
 949 ////////////////////////////////////////////////////////////////////////
 950 //
 951 //  TimingSimpleCPU Simulation Object
 952 //
 953 TimingSimpleCPU *
 954 TimingSimpleCPUParams::create()
 955 {
 956     numThreads = 1;
 957     if (!FullSystem && workload.size() != 1)
 958         panic("only one workload allowed");
 959     return new TimingSimpleCPU(this);
 960 }