2 * Copyright (c) 2010 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Steve Reinhardt
43 #include "arch/locked_mem.hh"
44 #include "arch/mmapped_ipr.hh"
45 #include "arch/utility.hh"
46 #include "base/bigint.hh"
47 #include "config/the_isa.hh"
48 #include "cpu/simple/timing.hh"
49 #include "cpu/exetrace.hh"
50 #include "debug/Config.hh"
51 #include "debug/ExecFaulting.hh"
52 #include "debug/SimpleCPU.hh"
53 #include "mem/packet.hh"
54 #include "mem/packet_access.hh"
55 #include "params/TimingSimpleCPU.hh"
56 #include "sim/faults.hh"
57 #include "sim/full_system.hh"
58 #include "sim/system.hh"
61 using namespace TheISA
;
64 TimingSimpleCPU::getPort(const std::string
&if_name
, int idx
)
66 if (if_name
== "dcache_port")
68 else if (if_name
== "icache_port")
71 panic("No Such Port\n");
75 TimingSimpleCPU::init()
79 for (int i
= 0; i
< threadContexts
.size(); ++i
) {
81 ThreadContext
*tc
= threadContexts
[i
];
82 // initialize CPU, including PC
83 TheISA::initCPU(tc
, _cpuId
);
90 TimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt
)
92 panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
97 TimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt
)
99 //No internal storage to update, jusst return
104 TimingSimpleCPU::CpuPort::recvStatusChange(Status status
)
106 if (status
== RangeChange
) {
107 if (!snoopRangeSent
) {
108 snoopRangeSent
= true;
109 sendStatusChange(Port::RangeChange
);
114 panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
119 TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt
, Tick t
)
122 cpu
->schedule(this, t
);
125 TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams
*p
)
126 : BaseSimpleCPU(p
), fetchTranslation(this), icachePort(this, p
->clock
),
127 dcachePort(this, p
->clock
), fetchEvent(this)
131 icachePort
.snoopRangeSent
= false;
132 dcachePort
.snoopRangeSent
= false;
134 ifetch_pkt
= dcache_pkt
= NULL
;
137 changeState(SimObject::Running
);
138 system
->totalNumInsts
= 0;
142 TimingSimpleCPU::~TimingSimpleCPU()
147 TimingSimpleCPU::serialize(ostream
&os
)
149 SimObject::State so_state
= SimObject::getState();
150 SERIALIZE_ENUM(so_state
);
151 BaseSimpleCPU::serialize(os
);
155 TimingSimpleCPU::unserialize(Checkpoint
*cp
, const string
§ion
)
157 SimObject::State so_state
;
158 UNSERIALIZE_ENUM(so_state
);
159 BaseSimpleCPU::unserialize(cp
, section
);
163 TimingSimpleCPU::drain(Event
*drain_event
)
165 // TimingSimpleCPU is ready to drain if it's not waiting for
166 // an access to complete.
167 if (_status
== Idle
|| _status
== Running
|| _status
== SwitchedOut
) {
168 changeState(SimObject::Drained
);
171 changeState(SimObject::Draining
);
172 drainEvent
= drain_event
;
178 TimingSimpleCPU::resume()
180 DPRINTF(SimpleCPU
, "Resume\n");
181 if (_status
!= SwitchedOut
&& _status
!= Idle
) {
182 assert(system
->getMemoryMode() == Enums::timing
);
184 if (fetchEvent
.scheduled())
185 deschedule(fetchEvent
);
187 schedule(fetchEvent
, nextCycle());
190 changeState(SimObject::Running
);
194 TimingSimpleCPU::switchOut()
196 assert(_status
== Running
|| _status
== Idle
);
197 _status
= SwitchedOut
;
198 numCycles
+= tickToCycles(curTick() - previousTick
);
200 // If we've been scheduled to resume but are then told to switch out,
201 // we'll need to cancel it.
202 if (fetchEvent
.scheduled())
203 deschedule(fetchEvent
);
208 TimingSimpleCPU::takeOverFrom(BaseCPU
*oldCPU
)
210 BaseCPU::takeOverFrom(oldCPU
, &icachePort
, &dcachePort
);
212 // if any of this CPU's ThreadContexts are active, mark the CPU as
213 // running and schedule its tick event.
214 for (int i
= 0; i
< threadContexts
.size(); ++i
) {
215 ThreadContext
*tc
= threadContexts
[i
];
216 if (tc
->status() == ThreadContext::Active
&& _status
!= Running
) {
222 if (_status
!= Running
) {
225 assert(threadContexts
.size() == 1);
226 previousTick
= curTick();
231 TimingSimpleCPU::activateContext(int thread_num
, int delay
)
233 DPRINTF(SimpleCPU
, "ActivateContext %d (%d cycles)\n", thread_num
, delay
);
235 assert(thread_num
== 0);
238 assert(_status
== Idle
);
243 // kick things off by initiating the fetch of the next instruction
244 schedule(fetchEvent
, nextCycle(curTick() + ticks(delay
)));
249 TimingSimpleCPU::suspendContext(int thread_num
)
251 DPRINTF(SimpleCPU
, "SuspendContext %d\n", thread_num
);
253 assert(thread_num
== 0);
259 assert(_status
== Running
);
261 // just change status to Idle... if status != Running,
262 // completeInst() will not initiate fetch of next instruction.
269 TimingSimpleCPU::handleReadPacket(PacketPtr pkt
)
271 RequestPtr req
= pkt
->req
;
272 if (req
->isMmappedIpr()) {
274 delay
= TheISA::handleIprRead(thread
->getTC(), pkt
);
275 new IprEvent(pkt
, this, nextCycle(curTick() + delay
));
276 _status
= DcacheWaitResponse
;
278 } else if (!dcachePort
.sendTiming(pkt
)) {
279 _status
= DcacheRetry
;
282 _status
= DcacheWaitResponse
;
283 // memory system takes ownership of packet
286 return dcache_pkt
== NULL
;
290 TimingSimpleCPU::sendData(RequestPtr req
, uint8_t *data
, uint64_t *res
,
294 buildPacket(pkt
, req
, read
);
295 pkt
->dataDynamicArray
<uint8_t>(data
);
296 if (req
->getFlags().isSet(Request::NO_ACCESS
)) {
299 completeDataAccess(pkt
);
301 handleReadPacket(pkt
);
303 bool do_access
= true; // flag to suppress cache access
306 do_access
= TheISA::handleLockedWrite(thread
, req
);
307 } else if (req
->isCondSwap()) {
309 req
->setExtraData(*res
);
316 _status
= DcacheWaitResponse
;
317 completeDataAccess(pkt
);
323 TimingSimpleCPU::sendSplitData(RequestPtr req1
, RequestPtr req2
,
324 RequestPtr req
, uint8_t *data
, bool read
)
326 PacketPtr pkt1
, pkt2
;
327 buildSplitPacket(pkt1
, pkt2
, req1
, req2
, req
, data
, read
);
328 if (req
->getFlags().isSet(Request::NO_ACCESS
)) {
330 pkt1
->makeResponse();
331 completeDataAccess(pkt1
);
333 SplitFragmentSenderState
* send_state
=
334 dynamic_cast<SplitFragmentSenderState
*>(pkt1
->senderState
);
335 if (handleReadPacket(pkt1
)) {
336 send_state
->clearFromParent();
337 send_state
= dynamic_cast<SplitFragmentSenderState
*>(
339 if (handleReadPacket(pkt2
)) {
340 send_state
->clearFromParent();
345 SplitFragmentSenderState
* send_state
=
346 dynamic_cast<SplitFragmentSenderState
*>(pkt1
->senderState
);
347 if (handleWritePacket()) {
348 send_state
->clearFromParent();
350 send_state
= dynamic_cast<SplitFragmentSenderState
*>(
352 if (handleWritePacket()) {
353 send_state
->clearFromParent();
360 TimingSimpleCPU::translationFault(Fault fault
)
362 // fault may be NoFault in cases where a fault is suppressed,
363 // for instance prefetches.
364 numCycles
+= tickToCycles(curTick() - previousTick
);
365 previousTick
= curTick();
368 // Since there was a fault, we shouldn't trace this instruction.
375 if (getState() == SimObject::Draining
) {
384 TimingSimpleCPU::buildPacket(PacketPtr
&pkt
, RequestPtr req
, bool read
)
388 cmd
= MemCmd::ReadReq
;
390 cmd
= MemCmd::LoadLockedReq
;
392 cmd
= MemCmd::WriteReq
;
394 cmd
= MemCmd::StoreCondReq
;
395 } else if (req
->isSwap()) {
396 cmd
= MemCmd::SwapReq
;
399 pkt
= new Packet(req
, cmd
, Packet::Broadcast
);
403 TimingSimpleCPU::buildSplitPacket(PacketPtr
&pkt1
, PacketPtr
&pkt2
,
404 RequestPtr req1
, RequestPtr req2
, RequestPtr req
,
405 uint8_t *data
, bool read
)
409 assert(!req1
->isMmappedIpr() && !req2
->isMmappedIpr());
411 if (req
->getFlags().isSet(Request::NO_ACCESS
)) {
412 buildPacket(pkt1
, req
, read
);
416 buildPacket(pkt1
, req1
, read
);
417 buildPacket(pkt2
, req2
, read
);
419 req
->setPhys(req1
->getPaddr(), req
->getSize(), req1
->getFlags());
420 PacketPtr pkt
= new Packet(req
, pkt1
->cmd
.responseCommand(),
423 pkt
->dataDynamicArray
<uint8_t>(data
);
424 pkt1
->dataStatic
<uint8_t>(data
);
425 pkt2
->dataStatic
<uint8_t>(data
+ req1
->getSize());
427 SplitMainSenderState
* main_send_state
= new SplitMainSenderState
;
428 pkt
->senderState
= main_send_state
;
429 main_send_state
->fragments
[0] = pkt1
;
430 main_send_state
->fragments
[1] = pkt2
;
431 main_send_state
->outstanding
= 2;
432 pkt1
->senderState
= new SplitFragmentSenderState(pkt
, 0);
433 pkt2
->senderState
= new SplitFragmentSenderState(pkt
, 1);
437 TimingSimpleCPU::readMem(Addr addr
, uint8_t *data
,
438 unsigned size
, unsigned flags
)
442 const ThreadID tid
= 0;
443 const Addr pc
= thread
->instAddr();
444 unsigned block_size
= dcachePort
.peerBlockSize();
445 BaseTLB::Mode mode
= BaseTLB::Read
;
448 traceData
->setAddr(addr
);
451 RequestPtr req
= new Request(asid
, addr
, size
,
452 flags
, pc
, _cpuId
, tid
);
454 Addr split_addr
= roundDown(addr
+ size
- 1, block_size
);
455 assert(split_addr
<= addr
|| split_addr
- addr
< block_size
);
457 _status
= DTBWaitResponse
;
458 if (split_addr
> addr
) {
459 RequestPtr req1
, req2
;
460 assert(!req
->isLLSC() && !req
->isSwap());
461 req
->splitOnVaddr(split_addr
, req1
, req2
);
463 WholeTranslationState
*state
=
464 new WholeTranslationState(req
, req1
, req2
, new uint8_t[size
],
466 DataTranslation
<TimingSimpleCPU
*> *trans1
=
467 new DataTranslation
<TimingSimpleCPU
*>(this, state
, 0);
468 DataTranslation
<TimingSimpleCPU
*> *trans2
=
469 new DataTranslation
<TimingSimpleCPU
*>(this, state
, 1);
471 thread
->dtb
->translateTiming(req1
, tc
, trans1
, mode
);
472 thread
->dtb
->translateTiming(req2
, tc
, trans2
, mode
);
474 WholeTranslationState
*state
=
475 new WholeTranslationState(req
, new uint8_t[size
], NULL
, mode
);
476 DataTranslation
<TimingSimpleCPU
*> *translation
477 = new DataTranslation
<TimingSimpleCPU
*>(this, state
);
478 thread
->dtb
->translateTiming(req
, tc
, translation
, mode
);
485 TimingSimpleCPU::handleWritePacket()
487 RequestPtr req
= dcache_pkt
->req
;
488 if (req
->isMmappedIpr()) {
490 delay
= TheISA::handleIprWrite(thread
->getTC(), dcache_pkt
);
491 new IprEvent(dcache_pkt
, this, nextCycle(curTick() + delay
));
492 _status
= DcacheWaitResponse
;
494 } else if (!dcachePort
.sendTiming(dcache_pkt
)) {
495 _status
= DcacheRetry
;
497 _status
= DcacheWaitResponse
;
498 // memory system takes ownership of packet
501 return dcache_pkt
== NULL
;
505 TimingSimpleCPU::writeMem(uint8_t *data
, unsigned size
,
506 Addr addr
, unsigned flags
, uint64_t *res
)
508 uint8_t *newData
= new uint8_t[size
];
509 memcpy(newData
, data
, size
);
512 const ThreadID tid
= 0;
513 const Addr pc
= thread
->instAddr();
514 unsigned block_size
= dcachePort
.peerBlockSize();
515 BaseTLB::Mode mode
= BaseTLB::Write
;
518 traceData
->setAddr(addr
);
521 RequestPtr req
= new Request(asid
, addr
, size
,
522 flags
, pc
, _cpuId
, tid
);
524 Addr split_addr
= roundDown(addr
+ size
- 1, block_size
);
525 assert(split_addr
<= addr
|| split_addr
- addr
< block_size
);
527 _status
= DTBWaitResponse
;
528 if (split_addr
> addr
) {
529 RequestPtr req1
, req2
;
530 assert(!req
->isLLSC() && !req
->isSwap());
531 req
->splitOnVaddr(split_addr
, req1
, req2
);
533 WholeTranslationState
*state
=
534 new WholeTranslationState(req
, req1
, req2
, newData
, res
, mode
);
535 DataTranslation
<TimingSimpleCPU
*> *trans1
=
536 new DataTranslation
<TimingSimpleCPU
*>(this, state
, 0);
537 DataTranslation
<TimingSimpleCPU
*> *trans2
=
538 new DataTranslation
<TimingSimpleCPU
*>(this, state
, 1);
540 thread
->dtb
->translateTiming(req1
, tc
, trans1
, mode
);
541 thread
->dtb
->translateTiming(req2
, tc
, trans2
, mode
);
543 WholeTranslationState
*state
=
544 new WholeTranslationState(req
, newData
, res
, mode
);
545 DataTranslation
<TimingSimpleCPU
*> *translation
=
546 new DataTranslation
<TimingSimpleCPU
*>(this, state
);
547 thread
->dtb
->translateTiming(req
, tc
, translation
, mode
);
550 // Translation faults will be returned via finishTranslation()
556 TimingSimpleCPU::finishTranslation(WholeTranslationState
*state
)
560 if (state
->getFault() != NoFault
) {
561 if (state
->isPrefetch()) {
564 delete [] state
->data
;
566 translationFault(state
->getFault());
568 if (!state
->isSplit
) {
569 sendData(state
->mainReq
, state
->data
, state
->res
,
570 state
->mode
== BaseTLB::Read
);
572 sendSplitData(state
->sreqLow
, state
->sreqHigh
, state
->mainReq
,
573 state
->data
, state
->mode
== BaseTLB::Read
);
582 TimingSimpleCPU::fetch()
584 DPRINTF(SimpleCPU
, "Fetch\n");
586 if (!curStaticInst
|| !curStaticInst
->isDelayedCommit())
587 checkForInterrupts();
591 // We must have just got suspended by a PC event
595 TheISA::PCState pcState
= thread
->pcState();
596 bool needToFetch
= !isRomMicroPC(pcState
.microPC()) && !curMacroStaticInst
;
600 Request
*ifetch_req
= new Request();
601 ifetch_req
->setThreadContext(_cpuId
, /* thread ID */ 0);
602 setupFetchRequest(ifetch_req
);
603 DPRINTF(SimpleCPU
, "Translating address %#x\n", ifetch_req
->getVaddr());
604 thread
->itb
->translateTiming(ifetch_req
, tc
, &fetchTranslation
,
607 _status
= IcacheWaitResponse
;
608 completeIfetch(NULL
);
610 numCycles
+= tickToCycles(curTick() - previousTick
);
611 previousTick
= curTick();
617 TimingSimpleCPU::sendFetch(Fault fault
, RequestPtr req
, ThreadContext
*tc
)
619 if (fault
== NoFault
) {
620 DPRINTF(SimpleCPU
, "Sending fetch for addr %#x(pa: %#x)\n",
621 req
->getVaddr(), req
->getPaddr());
622 ifetch_pkt
= new Packet(req
, MemCmd::ReadReq
, Packet::Broadcast
);
623 ifetch_pkt
->dataStatic(&inst
);
624 DPRINTF(SimpleCPU
, " -- pkt addr: %#x\n", ifetch_pkt
->getAddr());
626 if (!icachePort
.sendTiming(ifetch_pkt
)) {
627 // Need to wait for retry
628 _status
= IcacheRetry
;
630 // Need to wait for cache to respond
631 _status
= IcacheWaitResponse
;
632 // ownership of packet transferred to memory system
636 DPRINTF(SimpleCPU
, "Translation of addr %#x faulted\n", req
->getVaddr());
638 // fetch fault: advance directly to next instruction (fault handler)
643 numCycles
+= tickToCycles(curTick() - previousTick
);
644 previousTick
= curTick();
649 TimingSimpleCPU::advanceInst(Fault fault
)
652 if (_status
== Faulting
)
655 if (fault
!= NoFault
) {
657 DPRINTF(SimpleCPU
, "Fault occured, scheduling fetch event\n");
658 reschedule(fetchEvent
, nextCycle(), true);
667 if (_status
== Running
) {
668 // kick off fetch of next instruction... callback from icache
669 // response will cause that instruction to be executed,
670 // keeping the CPU running.
677 TimingSimpleCPU::completeIfetch(PacketPtr pkt
)
679 DPRINTF(SimpleCPU
, "Complete ICache Fetch for addr %#x\n", pkt
?
682 // received a response from the icache: execute the received
685 assert(!pkt
|| !pkt
->isError());
686 assert(_status
== IcacheWaitResponse
);
690 numCycles
+= tickToCycles(curTick() - previousTick
);
691 previousTick
= curTick();
693 if (getState() == SimObject::Draining
) {
704 if (curStaticInst
&& curStaticInst
->isMemRef()) {
705 // load or store: just send to dcache
706 Fault fault
= curStaticInst
->initiateAcc(this, traceData
);
708 // If we're not running now the instruction will complete in a dcache
709 // response callback or the instruction faulted and has started an
711 if (_status
== Running
) {
712 if (fault
!= NoFault
&& traceData
) {
713 // If there was a fault, we shouldn't trace this instruction.
719 // @todo remove me after debugging with legion done
720 if (curStaticInst
&& (!curStaticInst
->isMicroop() ||
721 curStaticInst
->isFirstMicroop()))
725 } else if (curStaticInst
) {
726 // non-memory instruction: execute completely now
727 Fault fault
= curStaticInst
->execute(this, traceData
);
729 // keep an instruction count
730 if (fault
== NoFault
)
732 else if (traceData
&& !DTRACE(ExecFaulting
)) {
738 // @todo remove me after debugging with legion done
739 if (curStaticInst
&& (!curStaticInst
->isMicroop() ||
740 curStaticInst
->isFirstMicroop()))
744 advanceInst(NoFault
);
754 TimingSimpleCPU::IcachePort::ITickEvent::process()
756 cpu
->completeIfetch(pkt
);
760 TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt
)
762 if (pkt
->isResponse() && !pkt
->wasNacked()) {
763 DPRINTF(SimpleCPU
, "Received timing response %#x\n", pkt
->getAddr());
764 // delay processing of returned data until next CPU clock edge
765 Tick next_tick
= cpu
->nextCycle(curTick());
767 if (next_tick
== curTick())
768 cpu
->completeIfetch(pkt
);
770 tickEvent
.schedule(pkt
, next_tick
);
773 } else if (pkt
->wasNacked()) {
774 assert(cpu
->_status
== IcacheWaitResponse
);
776 if (!sendTiming(pkt
)) {
777 cpu
->_status
= IcacheRetry
;
778 cpu
->ifetch_pkt
= pkt
;
781 //Snooping a Coherence Request, do nothing
786 TimingSimpleCPU::IcachePort::recvRetry()
788 // we shouldn't get a retry unless we have a packet that we're
789 // waiting to transmit
790 assert(cpu
->ifetch_pkt
!= NULL
);
791 assert(cpu
->_status
== IcacheRetry
);
792 PacketPtr tmp
= cpu
->ifetch_pkt
;
793 if (sendTiming(tmp
)) {
794 cpu
->_status
= IcacheWaitResponse
;
795 cpu
->ifetch_pkt
= NULL
;
800 TimingSimpleCPU::completeDataAccess(PacketPtr pkt
)
802 // received a response from the dcache: complete the load or store
804 assert(!pkt
->isError());
805 assert(_status
== DcacheWaitResponse
|| _status
== DTBWaitResponse
||
806 pkt
->req
->getFlags().isSet(Request::NO_ACCESS
));
808 numCycles
+= tickToCycles(curTick() - previousTick
);
809 previousTick
= curTick();
811 if (pkt
->senderState
) {
812 SplitFragmentSenderState
* send_state
=
813 dynamic_cast<SplitFragmentSenderState
*>(pkt
->senderState
);
817 PacketPtr big_pkt
= send_state
->bigPkt
;
820 SplitMainSenderState
* main_send_state
=
821 dynamic_cast<SplitMainSenderState
*>(big_pkt
->senderState
);
822 assert(main_send_state
);
823 // Record the fact that this packet is no longer outstanding.
824 assert(main_send_state
->outstanding
!= 0);
825 main_send_state
->outstanding
--;
827 if (main_send_state
->outstanding
) {
830 delete main_send_state
;
831 big_pkt
->senderState
= NULL
;
838 Fault fault
= curStaticInst
->completeAcc(pkt
, this, traceData
);
840 // keep an instruction count
841 if (fault
== NoFault
)
843 else if (traceData
) {
844 // If there was a fault, we shouldn't trace this instruction.
849 // the locked flag may be cleared on the response packet, so check
850 // pkt->req and not pkt to see if it was a load-locked
851 if (pkt
->isRead() && pkt
->req
->isLLSC()) {
852 TheISA::handleLockedRead(thread
, pkt
->req
);
860 if (getState() == SimObject::Draining
) {
872 TimingSimpleCPU::completeDrain()
874 DPRINTF(Config
, "Done draining\n");
875 changeState(SimObject::Drained
);
876 drainEvent
->process();
880 TimingSimpleCPU::DcachePort::setPeer(Port
*port
)
885 // Update the ThreadContext's memory ports (Functional/Virtual
887 cpu
->tcBase()->connectMemPorts(cpu
->tcBase());
892 TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt
)
894 if (pkt
->isResponse() && !pkt
->wasNacked()) {
895 // delay processing of returned data until next CPU clock edge
896 Tick next_tick
= cpu
->nextCycle(curTick());
898 if (next_tick
== curTick()) {
899 cpu
->completeDataAccess(pkt
);
901 if (!tickEvent
.scheduled()) {
902 tickEvent
.schedule(pkt
, next_tick
);
904 // In the case of a split transaction and a cache that is
905 // faster than a CPU we could get two responses before
907 if (!retryEvent
.scheduled())
908 schedule(retryEvent
, next_tick
);
915 else if (pkt
->wasNacked()) {
916 assert(cpu
->_status
== DcacheWaitResponse
);
918 if (!sendTiming(pkt
)) {
919 cpu
->_status
= DcacheRetry
;
920 cpu
->dcache_pkt
= pkt
;
923 //Snooping a Coherence Request, do nothing
928 TimingSimpleCPU::DcachePort::DTickEvent::process()
930 cpu
->completeDataAccess(pkt
);
934 TimingSimpleCPU::DcachePort::recvRetry()
936 // we shouldn't get a retry unless we have a packet that we're
937 // waiting to transmit
938 assert(cpu
->dcache_pkt
!= NULL
);
939 assert(cpu
->_status
== DcacheRetry
);
940 PacketPtr tmp
= cpu
->dcache_pkt
;
941 if (tmp
->senderState
) {
942 // This is a packet from a split access.
943 SplitFragmentSenderState
* send_state
=
944 dynamic_cast<SplitFragmentSenderState
*>(tmp
->senderState
);
946 PacketPtr big_pkt
= send_state
->bigPkt
;
948 SplitMainSenderState
* main_send_state
=
949 dynamic_cast<SplitMainSenderState
*>(big_pkt
->senderState
);
950 assert(main_send_state
);
952 if (sendTiming(tmp
)) {
953 // If we were able to send without retrying, record that fact
954 // and try sending the other fragment.
955 send_state
->clearFromParent();
956 int other_index
= main_send_state
->getPendingFragment();
957 if (other_index
> 0) {
958 tmp
= main_send_state
->fragments
[other_index
];
959 cpu
->dcache_pkt
= tmp
;
960 if ((big_pkt
->isRead() && cpu
->handleReadPacket(tmp
)) ||
961 (big_pkt
->isWrite() && cpu
->handleWritePacket())) {
962 main_send_state
->fragments
[other_index
] = NULL
;
965 cpu
->_status
= DcacheWaitResponse
;
966 // memory system takes ownership of packet
967 cpu
->dcache_pkt
= NULL
;
970 } else if (sendTiming(tmp
)) {
971 cpu
->_status
= DcacheWaitResponse
;
972 // memory system takes ownership of packet
973 cpu
->dcache_pkt
= NULL
;
977 TimingSimpleCPU::IprEvent::IprEvent(Packet
*_pkt
, TimingSimpleCPU
*_cpu
,
979 : pkt(_pkt
), cpu(_cpu
)
981 cpu
->schedule(this, t
);
985 TimingSimpleCPU::IprEvent::process()
987 cpu
->completeDataAccess(pkt
);
991 TimingSimpleCPU::IprEvent::description() const
993 return "Timing Simple CPU Delay IPR event";
998 TimingSimpleCPU::printAddr(Addr a
)
1000 dcachePort
.printAddr(a
);
1004 ////////////////////////////////////////////////////////////////////////
1006 // TimingSimpleCPU Simulation Object
1009 TimingSimpleCPUParams::create()
1013 if (!FullSystem
&& workload
.size() != 1)
1014 panic("only one workload allowed");
1016 return new TimingSimpleCPU(this);