d52003f19fc9e0677401f1bbc1345d54a3a5a0f3
2 * Copyright (c) 2010-2012 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Steve Reinhardt
43 #include "arch/locked_mem.hh"
44 #include "arch/mmapped_ipr.hh"
45 #include "arch/utility.hh"
46 #include "base/bigint.hh"
47 #include "config/the_isa.hh"
48 #include "cpu/simple/timing.hh"
49 #include "cpu/exetrace.hh"
50 #include "debug/Config.hh"
51 #include "debug/ExecFaulting.hh"
52 #include "debug/SimpleCPU.hh"
53 #include "mem/packet.hh"
54 #include "mem/packet_access.hh"
55 #include "params/TimingSimpleCPU.hh"
56 #include "sim/faults.hh"
57 #include "sim/full_system.hh"
58 #include "sim/system.hh"
61 using namespace TheISA
;
64 TimingSimpleCPU::init()
68 // Initialise the ThreadContext's memory proxies
69 tcBase()->initMemProxies(tcBase());
72 for (int i
= 0; i
< threadContexts
.size(); ++i
) {
73 ThreadContext
*tc
= threadContexts
[i
];
74 // initialize CPU, including PC
75 TheISA::initCPU(tc
, _cpuId
);
81 TimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt
, Tick t
)
84 cpu
->schedule(this, t
);
87 TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams
*p
)
88 : BaseSimpleCPU(p
), fetchTranslation(this), icachePort(this),
89 dcachePort(this), fetchEvent(this)
93 ifetch_pkt
= dcache_pkt
= NULL
;
96 changeState(SimObject::Running
);
97 system
->totalNumInsts
= 0;
101 TimingSimpleCPU::~TimingSimpleCPU()
106 TimingSimpleCPU::serialize(ostream
&os
)
108 SimObject::State so_state
= SimObject::getState();
109 SERIALIZE_ENUM(so_state
);
110 BaseSimpleCPU::serialize(os
);
114 TimingSimpleCPU::unserialize(Checkpoint
*cp
, const string
§ion
)
116 SimObject::State so_state
;
117 UNSERIALIZE_ENUM(so_state
);
118 BaseSimpleCPU::unserialize(cp
, section
);
122 TimingSimpleCPU::drain(Event
*drain_event
)
124 // TimingSimpleCPU is ready to drain if it's not waiting for
125 // an access to complete.
126 if (_status
== Idle
|| _status
== Running
|| _status
== SwitchedOut
) {
127 changeState(SimObject::Drained
);
130 changeState(SimObject::Draining
);
131 drainEvent
= drain_event
;
137 TimingSimpleCPU::resume()
139 DPRINTF(SimpleCPU
, "Resume\n");
140 if (_status
!= SwitchedOut
&& _status
!= Idle
) {
141 assert(system
->getMemoryMode() == Enums::timing
);
143 if (fetchEvent
.scheduled())
144 deschedule(fetchEvent
);
146 schedule(fetchEvent
, nextCycle());
149 changeState(SimObject::Running
);
153 TimingSimpleCPU::switchOut()
155 assert(_status
== Running
|| _status
== Idle
);
156 _status
= SwitchedOut
;
157 numCycles
+= tickToCycles(curTick() - previousTick
);
159 // If we've been scheduled to resume but are then told to switch out,
160 // we'll need to cancel it.
161 if (fetchEvent
.scheduled())
162 deschedule(fetchEvent
);
167 TimingSimpleCPU::takeOverFrom(BaseCPU
*oldCPU
)
169 BaseCPU::takeOverFrom(oldCPU
);
171 // if any of this CPU's ThreadContexts are active, mark the CPU as
172 // running and schedule its tick event.
173 for (int i
= 0; i
< threadContexts
.size(); ++i
) {
174 ThreadContext
*tc
= threadContexts
[i
];
175 if (tc
->status() == ThreadContext::Active
&& _status
!= Running
) {
181 if (_status
!= Running
) {
184 assert(threadContexts
.size() == 1);
185 previousTick
= curTick();
190 TimingSimpleCPU::activateContext(ThreadID thread_num
, int delay
)
192 DPRINTF(SimpleCPU
, "ActivateContext %d (%d cycles)\n", thread_num
, delay
);
194 assert(thread_num
== 0);
197 assert(_status
== Idle
);
202 // kick things off by initiating the fetch of the next instruction
203 schedule(fetchEvent
, nextCycle(curTick() + ticks(delay
)));
208 TimingSimpleCPU::suspendContext(ThreadID thread_num
)
210 DPRINTF(SimpleCPU
, "SuspendContext %d\n", thread_num
);
212 assert(thread_num
== 0);
218 assert(_status
== Running
);
220 // just change status to Idle... if status != Running,
221 // completeInst() will not initiate fetch of next instruction.
228 TimingSimpleCPU::handleReadPacket(PacketPtr pkt
)
230 RequestPtr req
= pkt
->req
;
231 if (req
->isMmappedIpr()) {
233 delay
= TheISA::handleIprRead(thread
->getTC(), pkt
);
234 new IprEvent(pkt
, this, nextCycle(curTick() + delay
));
235 _status
= DcacheWaitResponse
;
237 } else if (!dcachePort
.sendTiming(pkt
)) {
238 _status
= DcacheRetry
;
241 _status
= DcacheWaitResponse
;
242 // memory system takes ownership of packet
245 return dcache_pkt
== NULL
;
249 TimingSimpleCPU::sendData(RequestPtr req
, uint8_t *data
, uint64_t *res
,
253 buildPacket(pkt
, req
, read
);
254 pkt
->dataDynamicArray
<uint8_t>(data
);
255 if (req
->getFlags().isSet(Request::NO_ACCESS
)) {
258 completeDataAccess(pkt
);
260 handleReadPacket(pkt
);
262 bool do_access
= true; // flag to suppress cache access
265 do_access
= TheISA::handleLockedWrite(thread
, req
);
266 } else if (req
->isCondSwap()) {
268 req
->setExtraData(*res
);
275 _status
= DcacheWaitResponse
;
276 completeDataAccess(pkt
);
282 TimingSimpleCPU::sendSplitData(RequestPtr req1
, RequestPtr req2
,
283 RequestPtr req
, uint8_t *data
, bool read
)
285 PacketPtr pkt1
, pkt2
;
286 buildSplitPacket(pkt1
, pkt2
, req1
, req2
, req
, data
, read
);
287 if (req
->getFlags().isSet(Request::NO_ACCESS
)) {
289 pkt1
->makeResponse();
290 completeDataAccess(pkt1
);
292 SplitFragmentSenderState
* send_state
=
293 dynamic_cast<SplitFragmentSenderState
*>(pkt1
->senderState
);
294 if (handleReadPacket(pkt1
)) {
295 send_state
->clearFromParent();
296 send_state
= dynamic_cast<SplitFragmentSenderState
*>(
298 if (handleReadPacket(pkt2
)) {
299 send_state
->clearFromParent();
304 SplitFragmentSenderState
* send_state
=
305 dynamic_cast<SplitFragmentSenderState
*>(pkt1
->senderState
);
306 if (handleWritePacket()) {
307 send_state
->clearFromParent();
309 send_state
= dynamic_cast<SplitFragmentSenderState
*>(
311 if (handleWritePacket()) {
312 send_state
->clearFromParent();
319 TimingSimpleCPU::translationFault(Fault fault
)
321 // fault may be NoFault in cases where a fault is suppressed,
322 // for instance prefetches.
323 numCycles
+= tickToCycles(curTick() - previousTick
);
324 previousTick
= curTick();
327 // Since there was a fault, we shouldn't trace this instruction.
334 if (getState() == SimObject::Draining
) {
343 TimingSimpleCPU::buildPacket(PacketPtr
&pkt
, RequestPtr req
, bool read
)
347 cmd
= MemCmd::ReadReq
;
349 cmd
= MemCmd::LoadLockedReq
;
351 cmd
= MemCmd::WriteReq
;
353 cmd
= MemCmd::StoreCondReq
;
354 } else if (req
->isSwap()) {
355 cmd
= MemCmd::SwapReq
;
358 pkt
= new Packet(req
, cmd
, Packet::Broadcast
);
362 TimingSimpleCPU::buildSplitPacket(PacketPtr
&pkt1
, PacketPtr
&pkt2
,
363 RequestPtr req1
, RequestPtr req2
, RequestPtr req
,
364 uint8_t *data
, bool read
)
368 assert(!req1
->isMmappedIpr() && !req2
->isMmappedIpr());
370 if (req
->getFlags().isSet(Request::NO_ACCESS
)) {
371 buildPacket(pkt1
, req
, read
);
375 buildPacket(pkt1
, req1
, read
);
376 buildPacket(pkt2
, req2
, read
);
378 req
->setPhys(req1
->getPaddr(), req
->getSize(), req1
->getFlags(), dataMasterId());
379 PacketPtr pkt
= new Packet(req
, pkt1
->cmd
.responseCommand(),
382 pkt
->dataDynamicArray
<uint8_t>(data
);
383 pkt1
->dataStatic
<uint8_t>(data
);
384 pkt2
->dataStatic
<uint8_t>(data
+ req1
->getSize());
386 SplitMainSenderState
* main_send_state
= new SplitMainSenderState
;
387 pkt
->senderState
= main_send_state
;
388 main_send_state
->fragments
[0] = pkt1
;
389 main_send_state
->fragments
[1] = pkt2
;
390 main_send_state
->outstanding
= 2;
391 pkt1
->senderState
= new SplitFragmentSenderState(pkt
, 0);
392 pkt2
->senderState
= new SplitFragmentSenderState(pkt
, 1);
396 TimingSimpleCPU::readMem(Addr addr
, uint8_t *data
,
397 unsigned size
, unsigned flags
)
401 const ThreadID tid
= 0;
402 const Addr pc
= thread
->instAddr();
403 unsigned block_size
= dcachePort
.peerBlockSize();
404 BaseTLB::Mode mode
= BaseTLB::Read
;
407 traceData
->setAddr(addr
);
410 RequestPtr req
= new Request(asid
, addr
, size
,
411 flags
, dataMasterId(), pc
, _cpuId
, tid
);
413 Addr split_addr
= roundDown(addr
+ size
- 1, block_size
);
414 assert(split_addr
<= addr
|| split_addr
- addr
< block_size
);
416 _status
= DTBWaitResponse
;
417 if (split_addr
> addr
) {
418 RequestPtr req1
, req2
;
419 assert(!req
->isLLSC() && !req
->isSwap());
420 req
->splitOnVaddr(split_addr
, req1
, req2
);
422 WholeTranslationState
*state
=
423 new WholeTranslationState(req
, req1
, req2
, new uint8_t[size
],
425 DataTranslation
<TimingSimpleCPU
*> *trans1
=
426 new DataTranslation
<TimingSimpleCPU
*>(this, state
, 0);
427 DataTranslation
<TimingSimpleCPU
*> *trans2
=
428 new DataTranslation
<TimingSimpleCPU
*>(this, state
, 1);
430 thread
->dtb
->translateTiming(req1
, tc
, trans1
, mode
);
431 thread
->dtb
->translateTiming(req2
, tc
, trans2
, mode
);
433 WholeTranslationState
*state
=
434 new WholeTranslationState(req
, new uint8_t[size
], NULL
, mode
);
435 DataTranslation
<TimingSimpleCPU
*> *translation
436 = new DataTranslation
<TimingSimpleCPU
*>(this, state
);
437 thread
->dtb
->translateTiming(req
, tc
, translation
, mode
);
444 TimingSimpleCPU::handleWritePacket()
446 RequestPtr req
= dcache_pkt
->req
;
447 if (req
->isMmappedIpr()) {
449 delay
= TheISA::handleIprWrite(thread
->getTC(), dcache_pkt
);
450 new IprEvent(dcache_pkt
, this, nextCycle(curTick() + delay
));
451 _status
= DcacheWaitResponse
;
453 } else if (!dcachePort
.sendTiming(dcache_pkt
)) {
454 _status
= DcacheRetry
;
456 _status
= DcacheWaitResponse
;
457 // memory system takes ownership of packet
460 return dcache_pkt
== NULL
;
464 TimingSimpleCPU::writeMem(uint8_t *data
, unsigned size
,
465 Addr addr
, unsigned flags
, uint64_t *res
)
467 uint8_t *newData
= new uint8_t[size
];
468 memcpy(newData
, data
, size
);
471 const ThreadID tid
= 0;
472 const Addr pc
= thread
->instAddr();
473 unsigned block_size
= dcachePort
.peerBlockSize();
474 BaseTLB::Mode mode
= BaseTLB::Write
;
477 traceData
->setAddr(addr
);
480 RequestPtr req
= new Request(asid
, addr
, size
,
481 flags
, dataMasterId(), pc
, _cpuId
, tid
);
483 Addr split_addr
= roundDown(addr
+ size
- 1, block_size
);
484 assert(split_addr
<= addr
|| split_addr
- addr
< block_size
);
486 _status
= DTBWaitResponse
;
487 if (split_addr
> addr
) {
488 RequestPtr req1
, req2
;
489 assert(!req
->isLLSC() && !req
->isSwap());
490 req
->splitOnVaddr(split_addr
, req1
, req2
);
492 WholeTranslationState
*state
=
493 new WholeTranslationState(req
, req1
, req2
, newData
, res
, mode
);
494 DataTranslation
<TimingSimpleCPU
*> *trans1
=
495 new DataTranslation
<TimingSimpleCPU
*>(this, state
, 0);
496 DataTranslation
<TimingSimpleCPU
*> *trans2
=
497 new DataTranslation
<TimingSimpleCPU
*>(this, state
, 1);
499 thread
->dtb
->translateTiming(req1
, tc
, trans1
, mode
);
500 thread
->dtb
->translateTiming(req2
, tc
, trans2
, mode
);
502 WholeTranslationState
*state
=
503 new WholeTranslationState(req
, newData
, res
, mode
);
504 DataTranslation
<TimingSimpleCPU
*> *translation
=
505 new DataTranslation
<TimingSimpleCPU
*>(this, state
);
506 thread
->dtb
->translateTiming(req
, tc
, translation
, mode
);
509 // Translation faults will be returned via finishTranslation()
515 TimingSimpleCPU::finishTranslation(WholeTranslationState
*state
)
519 if (state
->getFault() != NoFault
) {
520 if (state
->isPrefetch()) {
523 delete [] state
->data
;
525 translationFault(state
->getFault());
527 if (!state
->isSplit
) {
528 sendData(state
->mainReq
, state
->data
, state
->res
,
529 state
->mode
== BaseTLB::Read
);
531 sendSplitData(state
->sreqLow
, state
->sreqHigh
, state
->mainReq
,
532 state
->data
, state
->mode
== BaseTLB::Read
);
541 TimingSimpleCPU::fetch()
543 DPRINTF(SimpleCPU
, "Fetch\n");
545 if (!curStaticInst
|| !curStaticInst
->isDelayedCommit())
546 checkForInterrupts();
550 // We must have just got suspended by a PC event
554 TheISA::PCState pcState
= thread
->pcState();
555 bool needToFetch
= !isRomMicroPC(pcState
.microPC()) && !curMacroStaticInst
;
559 Request
*ifetch_req
= new Request();
560 ifetch_req
->setThreadContext(_cpuId
, /* thread ID */ 0);
561 setupFetchRequest(ifetch_req
);
562 DPRINTF(SimpleCPU
, "Translating address %#x\n", ifetch_req
->getVaddr());
563 thread
->itb
->translateTiming(ifetch_req
, tc
, &fetchTranslation
,
566 _status
= IcacheWaitResponse
;
567 completeIfetch(NULL
);
569 numCycles
+= tickToCycles(curTick() - previousTick
);
570 previousTick
= curTick();
576 TimingSimpleCPU::sendFetch(Fault fault
, RequestPtr req
, ThreadContext
*tc
)
578 if (fault
== NoFault
) {
579 DPRINTF(SimpleCPU
, "Sending fetch for addr %#x(pa: %#x)\n",
580 req
->getVaddr(), req
->getPaddr());
581 ifetch_pkt
= new Packet(req
, MemCmd::ReadReq
, Packet::Broadcast
);
582 ifetch_pkt
->dataStatic(&inst
);
583 DPRINTF(SimpleCPU
, " -- pkt addr: %#x\n", ifetch_pkt
->getAddr());
585 if (!icachePort
.sendTiming(ifetch_pkt
)) {
586 // Need to wait for retry
587 _status
= IcacheRetry
;
589 // Need to wait for cache to respond
590 _status
= IcacheWaitResponse
;
591 // ownership of packet transferred to memory system
595 DPRINTF(SimpleCPU
, "Translation of addr %#x faulted\n", req
->getVaddr());
597 // fetch fault: advance directly to next instruction (fault handler)
602 numCycles
+= tickToCycles(curTick() - previousTick
);
603 previousTick
= curTick();
608 TimingSimpleCPU::advanceInst(Fault fault
)
611 if (_status
== Faulting
)
614 if (fault
!= NoFault
) {
616 DPRINTF(SimpleCPU
, "Fault occured, scheduling fetch event\n");
617 reschedule(fetchEvent
, nextCycle(), true);
626 if (_status
== Running
) {
627 // kick off fetch of next instruction... callback from icache
628 // response will cause that instruction to be executed,
629 // keeping the CPU running.
636 TimingSimpleCPU::completeIfetch(PacketPtr pkt
)
638 DPRINTF(SimpleCPU
, "Complete ICache Fetch for addr %#x\n", pkt
?
641 // received a response from the icache: execute the received
644 assert(!pkt
|| !pkt
->isError());
645 assert(_status
== IcacheWaitResponse
);
649 numCycles
+= tickToCycles(curTick() - previousTick
);
650 previousTick
= curTick();
652 if (getState() == SimObject::Draining
) {
663 if (curStaticInst
&& curStaticInst
->isMemRef()) {
664 // load or store: just send to dcache
665 Fault fault
= curStaticInst
->initiateAcc(this, traceData
);
667 // If we're not running now the instruction will complete in a dcache
668 // response callback or the instruction faulted and has started an
670 if (_status
== Running
) {
671 if (fault
!= NoFault
&& traceData
) {
672 // If there was a fault, we shouldn't trace this instruction.
678 // @todo remove me after debugging with legion done
679 if (curStaticInst
&& (!curStaticInst
->isMicroop() ||
680 curStaticInst
->isFirstMicroop()))
684 } else if (curStaticInst
) {
685 // non-memory instruction: execute completely now
686 Fault fault
= curStaticInst
->execute(this, traceData
);
688 // keep an instruction count
689 if (fault
== NoFault
)
691 else if (traceData
&& !DTRACE(ExecFaulting
)) {
697 // @todo remove me after debugging with legion done
698 if (curStaticInst
&& (!curStaticInst
->isMicroop() ||
699 curStaticInst
->isFirstMicroop()))
703 advanceInst(NoFault
);
713 TimingSimpleCPU::IcachePort::ITickEvent::process()
715 cpu
->completeIfetch(pkt
);
719 TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt
)
721 assert(pkt
->isResponse());
722 if (!pkt
->wasNacked()) {
723 DPRINTF(SimpleCPU
, "Received timing response %#x\n", pkt
->getAddr());
724 // delay processing of returned data until next CPU clock edge
725 Tick next_tick
= cpu
->nextCycle(curTick());
727 if (next_tick
== curTick())
728 cpu
->completeIfetch(pkt
);
730 tickEvent
.schedule(pkt
, next_tick
);
734 assert(cpu
->_status
== IcacheWaitResponse
);
736 if (!sendTiming(pkt
)) {
737 cpu
->_status
= IcacheRetry
;
738 cpu
->ifetch_pkt
= pkt
;
746 TimingSimpleCPU::IcachePort::recvRetry()
748 // we shouldn't get a retry unless we have a packet that we're
749 // waiting to transmit
750 assert(cpu
->ifetch_pkt
!= NULL
);
751 assert(cpu
->_status
== IcacheRetry
);
752 PacketPtr tmp
= cpu
->ifetch_pkt
;
753 if (sendTiming(tmp
)) {
754 cpu
->_status
= IcacheWaitResponse
;
755 cpu
->ifetch_pkt
= NULL
;
760 TimingSimpleCPU::completeDataAccess(PacketPtr pkt
)
762 // received a response from the dcache: complete the load or store
764 assert(!pkt
->isError());
765 assert(_status
== DcacheWaitResponse
|| _status
== DTBWaitResponse
||
766 pkt
->req
->getFlags().isSet(Request::NO_ACCESS
));
768 numCycles
+= tickToCycles(curTick() - previousTick
);
769 previousTick
= curTick();
771 if (pkt
->senderState
) {
772 SplitFragmentSenderState
* send_state
=
773 dynamic_cast<SplitFragmentSenderState
*>(pkt
->senderState
);
777 PacketPtr big_pkt
= send_state
->bigPkt
;
780 SplitMainSenderState
* main_send_state
=
781 dynamic_cast<SplitMainSenderState
*>(big_pkt
->senderState
);
782 assert(main_send_state
);
783 // Record the fact that this packet is no longer outstanding.
784 assert(main_send_state
->outstanding
!= 0);
785 main_send_state
->outstanding
--;
787 if (main_send_state
->outstanding
) {
790 delete main_send_state
;
791 big_pkt
->senderState
= NULL
;
798 Fault fault
= curStaticInst
->completeAcc(pkt
, this, traceData
);
800 // keep an instruction count
801 if (fault
== NoFault
)
803 else if (traceData
) {
804 // If there was a fault, we shouldn't trace this instruction.
809 // the locked flag may be cleared on the response packet, so check
810 // pkt->req and not pkt to see if it was a load-locked
811 if (pkt
->isRead() && pkt
->req
->isLLSC()) {
812 TheISA::handleLockedRead(thread
, pkt
->req
);
820 if (getState() == SimObject::Draining
) {
832 TimingSimpleCPU::completeDrain()
834 DPRINTF(Config
, "Done draining\n");
835 changeState(SimObject::Drained
);
836 drainEvent
->process();
840 TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt
)
842 assert(pkt
->isResponse());
843 if (!pkt
->wasNacked()) {
844 // delay processing of returned data until next CPU clock edge
845 Tick next_tick
= cpu
->nextCycle(curTick());
847 if (next_tick
== curTick()) {
848 cpu
->completeDataAccess(pkt
);
850 if (!tickEvent
.scheduled()) {
851 tickEvent
.schedule(pkt
, next_tick
);
853 // In the case of a split transaction and a cache that is
854 // faster than a CPU we could get two responses before
856 if (!retryEvent
.scheduled())
857 cpu
->schedule(retryEvent
, next_tick
);
864 assert(cpu
->_status
== DcacheWaitResponse
);
866 if (!sendTiming(pkt
)) {
867 cpu
->_status
= DcacheRetry
;
868 cpu
->dcache_pkt
= pkt
;
876 TimingSimpleCPU::DcachePort::DTickEvent::process()
878 cpu
->completeDataAccess(pkt
);
882 TimingSimpleCPU::DcachePort::recvRetry()
884 // we shouldn't get a retry unless we have a packet that we're
885 // waiting to transmit
886 assert(cpu
->dcache_pkt
!= NULL
);
887 assert(cpu
->_status
== DcacheRetry
);
888 PacketPtr tmp
= cpu
->dcache_pkt
;
889 if (tmp
->senderState
) {
890 // This is a packet from a split access.
891 SplitFragmentSenderState
* send_state
=
892 dynamic_cast<SplitFragmentSenderState
*>(tmp
->senderState
);
894 PacketPtr big_pkt
= send_state
->bigPkt
;
896 SplitMainSenderState
* main_send_state
=
897 dynamic_cast<SplitMainSenderState
*>(big_pkt
->senderState
);
898 assert(main_send_state
);
900 if (sendTiming(tmp
)) {
901 // If we were able to send without retrying, record that fact
902 // and try sending the other fragment.
903 send_state
->clearFromParent();
904 int other_index
= main_send_state
->getPendingFragment();
905 if (other_index
> 0) {
906 tmp
= main_send_state
->fragments
[other_index
];
907 cpu
->dcache_pkt
= tmp
;
908 if ((big_pkt
->isRead() && cpu
->handleReadPacket(tmp
)) ||
909 (big_pkt
->isWrite() && cpu
->handleWritePacket())) {
910 main_send_state
->fragments
[other_index
] = NULL
;
913 cpu
->_status
= DcacheWaitResponse
;
914 // memory system takes ownership of packet
915 cpu
->dcache_pkt
= NULL
;
918 } else if (sendTiming(tmp
)) {
919 cpu
->_status
= DcacheWaitResponse
;
920 // memory system takes ownership of packet
921 cpu
->dcache_pkt
= NULL
;
925 TimingSimpleCPU::IprEvent::IprEvent(Packet
*_pkt
, TimingSimpleCPU
*_cpu
,
927 : pkt(_pkt
), cpu(_cpu
)
929 cpu
->schedule(this, t
);
933 TimingSimpleCPU::IprEvent::process()
935 cpu
->completeDataAccess(pkt
);
939 TimingSimpleCPU::IprEvent::description() const
941 return "Timing Simple CPU Delay IPR event";
946 TimingSimpleCPU::printAddr(Addr a
)
948 dcachePort
.printAddr(a
);
952 ////////////////////////////////////////////////////////////////////////
954 // TimingSimpleCPU Simulation Object
957 TimingSimpleCPUParams::create()
960 if (!FullSystem
&& workload
.size() != 1)
961 panic("only one workload allowed");
962 return new TimingSimpleCPU(this);