2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
31 #include "arch/locked_mem.hh"
32 #include "arch/mmaped_ipr.hh"
33 #include "arch/utility.hh"
34 #include "base/bigint.hh"
35 #include "cpu/exetrace.hh"
36 #include "cpu/simple/timing.hh"
37 #include "mem/packet.hh"
38 #include "mem/packet_access.hh"
39 #include "params/TimingSimpleCPU.hh"
40 #include "sim/system.hh"
43 using namespace TheISA
;
46 TimingSimpleCPU::getPort(const std::string
&if_name
, int idx
)
48 if (if_name
== "dcache_port")
50 else if (if_name
== "icache_port")
53 panic("No Such Port\n");
57 TimingSimpleCPU::init()
60 cpuId
= tc
->readCpuId();
62 for (int i
= 0; i
< threadContexts
.size(); ++i
) {
63 ThreadContext
*tc
= threadContexts
[i
];
65 // initialize CPU, including PC
66 TheISA::initCPU(tc
, cpuId
);
72 TimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt
)
74 panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
79 TimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt
)
81 //No internal storage to update, jusst return
86 TimingSimpleCPU::CpuPort::recvStatusChange(Status status
)
88 if (status
== RangeChange
) {
89 if (!snoopRangeSent
) {
90 snoopRangeSent
= true;
91 sendStatusChange(Port::RangeChange
);
96 panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
101 TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt
, Tick t
)
104 cpu
->schedule(this, t
);
107 TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams
*p
)
108 : BaseSimpleCPU(p
), icachePort(this, p
->clock
), dcachePort(this, p
->clock
)
112 icachePort
.snoopRangeSent
= false;
113 dcachePort
.snoopRangeSent
= false;
115 ifetch_pkt
= dcache_pkt
= NULL
;
119 changeState(SimObject::Running
);
123 TimingSimpleCPU::~TimingSimpleCPU()
128 TimingSimpleCPU::serialize(ostream
&os
)
130 SimObject::State so_state
= SimObject::getState();
131 SERIALIZE_ENUM(so_state
);
132 BaseSimpleCPU::serialize(os
);
136 TimingSimpleCPU::unserialize(Checkpoint
*cp
, const string
§ion
)
138 SimObject::State so_state
;
139 UNSERIALIZE_ENUM(so_state
);
140 BaseSimpleCPU::unserialize(cp
, section
);
144 TimingSimpleCPU::drain(Event
*drain_event
)
146 // TimingSimpleCPU is ready to drain if it's not waiting for
147 // an access to complete.
148 if (_status
== Idle
|| _status
== Running
|| _status
== SwitchedOut
) {
149 changeState(SimObject::Drained
);
152 changeState(SimObject::Draining
);
153 drainEvent
= drain_event
;
159 TimingSimpleCPU::resume()
161 DPRINTF(SimpleCPU
, "Resume\n");
162 if (_status
!= SwitchedOut
&& _status
!= Idle
) {
163 assert(system
->getMemoryMode() == Enums::timing
);
165 // Delete the old event if it existed.
167 if (fetchEvent
->scheduled())
168 deschedule(fetchEvent
);
173 fetchEvent
= new FetchEvent(this, nextCycle());
176 changeState(SimObject::Running
);
180 TimingSimpleCPU::switchOut()
182 assert(_status
== Running
|| _status
== Idle
);
183 _status
= SwitchedOut
;
184 numCycles
+= tickToCycles(curTick
- previousTick
);
186 // If we've been scheduled to resume but are then told to switch out,
187 // we'll need to cancel it.
188 if (fetchEvent
&& fetchEvent
->scheduled())
189 deschedule(fetchEvent
);
194 TimingSimpleCPU::takeOverFrom(BaseCPU
*oldCPU
)
196 BaseCPU::takeOverFrom(oldCPU
, &icachePort
, &dcachePort
);
198 // if any of this CPU's ThreadContexts are active, mark the CPU as
199 // running and schedule its tick event.
200 for (int i
= 0; i
< threadContexts
.size(); ++i
) {
201 ThreadContext
*tc
= threadContexts
[i
];
202 if (tc
->status() == ThreadContext::Active
&& _status
!= Running
) {
208 if (_status
!= Running
) {
211 assert(threadContexts
.size() == 1);
212 cpuId
= tc
->readCpuId();
213 previousTick
= curTick
;
218 TimingSimpleCPU::activateContext(int thread_num
, int delay
)
220 DPRINTF(SimpleCPU
, "ActivateContext %d (%d cycles)\n", thread_num
, delay
);
222 assert(thread_num
== 0);
225 assert(_status
== Idle
);
230 // kick things off by initiating the fetch of the next instruction
231 fetchEvent
= new FetchEvent(this);
232 schedule(fetchEvent
, nextCycle(curTick
+ ticks(delay
)));
237 TimingSimpleCPU::suspendContext(int thread_num
)
239 DPRINTF(SimpleCPU
, "SuspendContext %d\n", thread_num
);
241 assert(thread_num
== 0);
244 assert(_status
== Running
);
246 // just change status to Idle... if status != Running,
247 // completeInst() will not initiate fetch of next instruction.
256 TimingSimpleCPU::read(Addr addr
, T
&data
, unsigned flags
)
259 new Request(/* asid */ 0, addr
, sizeof(T
), flags
, thread
->readPC(),
260 cpuId
, /* thread ID */ 0);
263 traceData
->setAddr(req
->getVaddr());
266 // translate to physical address
267 Fault fault
= thread
->translateDataReadReq(req
);
269 // Now do the access.
270 if (fault
== NoFault
) {
274 MemCmd::LoadLockedReq
: MemCmd::ReadReq
),
276 pkt
->dataDynamic
<T
>(new T
);
278 if (req
->isMmapedIpr()) {
280 delay
= TheISA::handleIprRead(thread
->getTC(), pkt
);
281 new IprEvent(pkt
, this, nextCycle(curTick
+ delay
));
282 _status
= DcacheWaitResponse
;
284 } else if (!dcachePort
.sendTiming(pkt
)) {
285 _status
= DcacheRetry
;
288 _status
= DcacheWaitResponse
;
289 // memory system takes ownership of packet
293 // This will need a new way to tell if it has a dcache attached.
294 if (req
->isUncacheable())
295 recordEvent("Uncached Read");
301 traceData
->setData(data
);
307 TimingSimpleCPU::translateDataReadAddr(Addr vaddr
, Addr
&paddr
,
308 int size
, unsigned flags
)
311 new Request(0, vaddr
, size
, flags
, thread
->readPC(), cpuId
, 0);
314 traceData
->setAddr(vaddr
);
317 Fault fault
= thread
->translateDataWriteReq(req
);
319 if (fault
== NoFault
)
320 paddr
= req
->getPaddr();
326 #ifndef DOXYGEN_SHOULD_SKIP_THIS
330 TimingSimpleCPU::read(Addr addr
, Twin64_t
&data
, unsigned flags
);
334 TimingSimpleCPU::read(Addr addr
, Twin32_t
&data
, unsigned flags
);
338 TimingSimpleCPU::read(Addr addr
, uint64_t &data
, unsigned flags
);
342 TimingSimpleCPU::read(Addr addr
, uint32_t &data
, unsigned flags
);
346 TimingSimpleCPU::read(Addr addr
, uint16_t &data
, unsigned flags
);
350 TimingSimpleCPU::read(Addr addr
, uint8_t &data
, unsigned flags
);
352 #endif //DOXYGEN_SHOULD_SKIP_THIS
356 TimingSimpleCPU::read(Addr addr
, double &data
, unsigned flags
)
358 return read(addr
, *(uint64_t*)&data
, flags
);
363 TimingSimpleCPU::read(Addr addr
, float &data
, unsigned flags
)
365 return read(addr
, *(uint32_t*)&data
, flags
);
371 TimingSimpleCPU::read(Addr addr
, int32_t &data
, unsigned flags
)
373 return read(addr
, (uint32_t&)data
, flags
);
379 TimingSimpleCPU::write(T data
, Addr addr
, unsigned flags
, uint64_t *res
)
382 new Request(/* asid */ 0, addr
, sizeof(T
), flags
, thread
->readPC(),
383 cpuId
, /* thread ID */ 0);
386 traceData
->setAddr(req
->getVaddr());
389 // translate to physical address
390 Fault fault
= thread
->translateDataWriteReq(req
);
392 // Now do the access.
393 if (fault
== NoFault
) {
394 MemCmd cmd
= MemCmd::WriteReq
; // default
395 bool do_access
= true; // flag to suppress cache access
397 if (req
->isLocked()) {
398 cmd
= MemCmd::StoreCondReq
;
399 do_access
= TheISA::handleLockedWrite(thread
, req
);
400 } else if (req
->isSwap()) {
401 cmd
= MemCmd::SwapReq
;
402 if (req
->isCondSwap()) {
404 req
->setExtraData(*res
);
408 // Note: need to allocate dcache_pkt even if do_access is
409 // false, as it's used unconditionally to call completeAcc().
410 assert(dcache_pkt
== NULL
);
411 dcache_pkt
= new Packet(req
, cmd
, Packet::Broadcast
);
412 dcache_pkt
->allocate();
413 dcache_pkt
->set(data
);
416 if (req
->isMmapedIpr()) {
418 dcache_pkt
->set(htog(data
));
419 delay
= TheISA::handleIprWrite(thread
->getTC(), dcache_pkt
);
420 new IprEvent(dcache_pkt
, this, nextCycle(curTick
+ delay
));
421 _status
= DcacheWaitResponse
;
423 } else if (!dcachePort
.sendTiming(dcache_pkt
)) {
424 _status
= DcacheRetry
;
426 _status
= DcacheWaitResponse
;
427 // memory system takes ownership of packet
431 // This will need a new way to tell if it's hooked up to a cache or not.
432 if (req
->isUncacheable())
433 recordEvent("Uncached Write");
439 traceData
->setData(data
);
442 // If the write needs to have a fault on the access, consider calling
443 // changeStatus() and changing it to "bad addr write" or something.
448 TimingSimpleCPU::translateDataWriteAddr(Addr vaddr
, Addr
&paddr
,
449 int size
, unsigned flags
)
452 new Request(0, vaddr
, size
, flags
, thread
->readPC(), cpuId
, 0);
455 traceData
->setAddr(vaddr
);
458 Fault fault
= thread
->translateDataWriteReq(req
);
460 if (fault
== NoFault
)
461 paddr
= req
->getPaddr();
468 #ifndef DOXYGEN_SHOULD_SKIP_THIS
471 TimingSimpleCPU::write(Twin32_t data
, Addr addr
,
472 unsigned flags
, uint64_t *res
);
476 TimingSimpleCPU::write(Twin64_t data
, Addr addr
,
477 unsigned flags
, uint64_t *res
);
481 TimingSimpleCPU::write(uint64_t data
, Addr addr
,
482 unsigned flags
, uint64_t *res
);
486 TimingSimpleCPU::write(uint32_t data
, Addr addr
,
487 unsigned flags
, uint64_t *res
);
491 TimingSimpleCPU::write(uint16_t data
, Addr addr
,
492 unsigned flags
, uint64_t *res
);
496 TimingSimpleCPU::write(uint8_t data
, Addr addr
,
497 unsigned flags
, uint64_t *res
);
499 #endif //DOXYGEN_SHOULD_SKIP_THIS
503 TimingSimpleCPU::write(double data
, Addr addr
, unsigned flags
, uint64_t *res
)
505 return write(*(uint64_t*)&data
, addr
, flags
, res
);
510 TimingSimpleCPU::write(float data
, Addr addr
, unsigned flags
, uint64_t *res
)
512 return write(*(uint32_t*)&data
, addr
, flags
, res
);
518 TimingSimpleCPU::write(int32_t data
, Addr addr
, unsigned flags
, uint64_t *res
)
520 return write((uint32_t)data
, addr
, flags
, res
);
525 TimingSimpleCPU::fetch()
527 DPRINTF(SimpleCPU
, "Fetch\n");
529 if (!curStaticInst
|| !curStaticInst
->isDelayedCommit())
530 checkForInterrupts();
534 bool fromRom
= isRomMicroPC(thread
->readMicroPC());
537 Request
*ifetch_req
= new Request();
538 ifetch_req
->setThreadContext(cpuId
, /* thread ID */ 0);
539 Fault fault
= setupFetchRequest(ifetch_req
);
541 ifetch_pkt
= new Packet(ifetch_req
, MemCmd::ReadReq
, Packet::Broadcast
);
542 ifetch_pkt
->dataStatic(&inst
);
544 if (fault
== NoFault
) {
545 if (!icachePort
.sendTiming(ifetch_pkt
)) {
546 // Need to wait for retry
547 _status
= IcacheRetry
;
549 // Need to wait for cache to respond
550 _status
= IcacheWaitResponse
;
551 // ownership of packet transferred to memory system
557 // fetch fault: advance directly to next instruction (fault handler)
561 _status
= IcacheWaitResponse
;
562 completeIfetch(NULL
);
565 numCycles
+= tickToCycles(curTick
- previousTick
);
566 previousTick
= curTick
;
571 TimingSimpleCPU::advanceInst(Fault fault
)
575 if (_status
== Running
) {
576 // kick off fetch of next instruction... callback from icache
577 // response will cause that instruction to be executed,
578 // keeping the CPU running.
585 TimingSimpleCPU::completeIfetch(PacketPtr pkt
)
587 DPRINTF(SimpleCPU
, "Complete ICache Fetch\n");
589 // received a response from the icache: execute the received
592 assert(!pkt
|| !pkt
->isError());
593 assert(_status
== IcacheWaitResponse
);
597 numCycles
+= tickToCycles(curTick
- previousTick
);
598 previousTick
= curTick
;
600 if (getState() == SimObject::Draining
) {
611 if (curStaticInst
->isMemRef() && !curStaticInst
->isDataPrefetch()) {
612 // load or store: just send to dcache
613 Fault fault
= curStaticInst
->initiateAcc(this, traceData
);
614 if (_status
!= Running
) {
615 // instruction will complete in dcache response callback
616 assert(_status
== DcacheWaitResponse
|| _status
== DcacheRetry
);
617 assert(fault
== NoFault
);
619 if (fault
== NoFault
) {
620 // Note that ARM can have NULL packets if the instruction gets
621 // squashed due to predication
622 // early fail on store conditional: complete now
623 assert(dcache_pkt
!= NULL
|| THE_ISA
== ARM_ISA
);
625 fault
= curStaticInst
->completeAcc(dcache_pkt
, this,
627 if (dcache_pkt
!= NULL
)
629 delete dcache_pkt
->req
;
634 // keep an instruction count
635 if (fault
== NoFault
)
637 } else if (traceData
) {
638 // If there was a fault, we shouldn't trace this instruction.
644 // @todo remove me after debugging with legion done
645 if (curStaticInst
&& (!curStaticInst
->isMicroop() ||
646 curStaticInst
->isFirstMicroop()))
651 // non-memory instruction: execute completely now
652 Fault fault
= curStaticInst
->execute(this, traceData
);
654 // keep an instruction count
655 if (fault
== NoFault
)
657 else if (traceData
) {
658 // If there was a fault, we shouldn't trace this instruction.
664 // @todo remove me after debugging with legion done
665 if (curStaticInst
&& (!curStaticInst
->isMicroop() ||
666 curStaticInst
->isFirstMicroop()))
678 TimingSimpleCPU::IcachePort::ITickEvent::process()
680 cpu
->completeIfetch(pkt
);
684 TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt
)
686 if (pkt
->isResponse() && !pkt
->wasNacked()) {
687 // delay processing of returned data until next CPU clock edge
688 Tick next_tick
= cpu
->nextCycle(curTick
);
690 if (next_tick
== curTick
)
691 cpu
->completeIfetch(pkt
);
693 tickEvent
.schedule(pkt
, next_tick
);
697 else if (pkt
->wasNacked()) {
698 assert(cpu
->_status
== IcacheWaitResponse
);
700 if (!sendTiming(pkt
)) {
701 cpu
->_status
= IcacheRetry
;
702 cpu
->ifetch_pkt
= pkt
;
705 //Snooping a Coherence Request, do nothing
710 TimingSimpleCPU::IcachePort::recvRetry()
712 // we shouldn't get a retry unless we have a packet that we're
713 // waiting to transmit
714 assert(cpu
->ifetch_pkt
!= NULL
);
715 assert(cpu
->_status
== IcacheRetry
);
716 PacketPtr tmp
= cpu
->ifetch_pkt
;
717 if (sendTiming(tmp
)) {
718 cpu
->_status
= IcacheWaitResponse
;
719 cpu
->ifetch_pkt
= NULL
;
724 TimingSimpleCPU::completeDataAccess(PacketPtr pkt
)
726 // received a response from the dcache: complete the load or store
728 assert(!pkt
->isError());
729 assert(_status
== DcacheWaitResponse
);
732 numCycles
+= tickToCycles(curTick
- previousTick
);
733 previousTick
= curTick
;
735 Fault fault
= curStaticInst
->completeAcc(pkt
, this, traceData
);
737 // keep an instruction count
738 if (fault
== NoFault
)
740 else if (traceData
) {
741 // If there was a fault, we shouldn't trace this instruction.
746 // the locked flag may be cleared on the response packet, so check
747 // pkt->req and not pkt to see if it was a load-locked
748 if (pkt
->isRead() && pkt
->req
->isLocked()) {
749 TheISA::handleLockedRead(thread
, pkt
->req
);
757 if (getState() == SimObject::Draining
) {
769 TimingSimpleCPU::completeDrain()
771 DPRINTF(Config
, "Done draining\n");
772 changeState(SimObject::Drained
);
773 drainEvent
->process();
777 TimingSimpleCPU::DcachePort::setPeer(Port
*port
)
782 // Update the ThreadContext's memory ports (Functional/Virtual
784 cpu
->tcBase()->connectMemPorts(cpu
->tcBase());
789 TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt
)
791 if (pkt
->isResponse() && !pkt
->wasNacked()) {
792 // delay processing of returned data until next CPU clock edge
793 Tick next_tick
= cpu
->nextCycle(curTick
);
795 if (next_tick
== curTick
)
796 cpu
->completeDataAccess(pkt
);
798 tickEvent
.schedule(pkt
, next_tick
);
802 else if (pkt
->wasNacked()) {
803 assert(cpu
->_status
== DcacheWaitResponse
);
805 if (!sendTiming(pkt
)) {
806 cpu
->_status
= DcacheRetry
;
807 cpu
->dcache_pkt
= pkt
;
810 //Snooping a Coherence Request, do nothing
815 TimingSimpleCPU::DcachePort::DTickEvent::process()
817 cpu
->completeDataAccess(pkt
);
821 TimingSimpleCPU::DcachePort::recvRetry()
823 // we shouldn't get a retry unless we have a packet that we're
824 // waiting to transmit
825 assert(cpu
->dcache_pkt
!= NULL
);
826 assert(cpu
->_status
== DcacheRetry
);
827 PacketPtr tmp
= cpu
->dcache_pkt
;
828 if (sendTiming(tmp
)) {
829 cpu
->_status
= DcacheWaitResponse
;
830 // memory system takes ownership of packet
831 cpu
->dcache_pkt
= NULL
;
835 TimingSimpleCPU::IprEvent::IprEvent(Packet
*_pkt
, TimingSimpleCPU
*_cpu
,
837 : pkt(_pkt
), cpu(_cpu
)
839 cpu
->schedule(this, t
);
843 TimingSimpleCPU::IprEvent::process()
845 cpu
->completeDataAccess(pkt
);
849 TimingSimpleCPU::IprEvent::description() const
851 return "Timing Simple CPU Delay IPR event";
856 TimingSimpleCPU::printAddr(Addr a
)
858 dcachePort
.printAddr(a
);
862 ////////////////////////////////////////////////////////////////////////
864 // TimingSimpleCPU Simulation Object
867 TimingSimpleCPUParams::create()
871 if (workload
.size() != 1)
872 panic("only one workload allowed");
874 return new TimingSimpleCPU(this);