2 * Copyright (c) 2010 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Steve Reinhardt
43 #include "arch/locked_mem.hh"
44 #include "arch/mmapped_ipr.hh"
45 #include "arch/utility.hh"
46 #include "base/bigint.hh"
47 #include "config/the_isa.hh"
48 #include "cpu/simple/timing.hh"
49 #include "cpu/exetrace.hh"
50 #include "debug/Config.hh"
51 #include "debug/ExecFaulting.hh"
52 #include "debug/SimpleCPU.hh"
53 #include "mem/packet.hh"
54 #include "mem/packet_access.hh"
55 #include "params/TimingSimpleCPU.hh"
56 #include "sim/faults.hh"
57 #include "sim/full_system.hh"
58 #include "sim/system.hh"
61 using namespace TheISA
;
64 TimingSimpleCPU::getPort(const std::string
&if_name
, int idx
)
66 if (if_name
== "dcache_port")
68 else if (if_name
== "icache_port")
71 panic("No Such Port\n");
75 TimingSimpleCPU::init()
79 for (int i
= 0; i
< threadContexts
.size(); ++i
) {
80 ThreadContext
*tc
= threadContexts
[i
];
81 // initialize CPU, including PC
82 TheISA::initCPU(tc
, _cpuId
);
86 // Initialise the ThreadContext's memory proxies
87 tcBase()->initMemProxies(tcBase());
91 TimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt
, Tick t
)
94 cpu
->schedule(this, t
);
97 TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams
*p
)
98 : BaseSimpleCPU(p
), fetchTranslation(this), icachePort(this),
99 dcachePort(this), fetchEvent(this)
103 ifetch_pkt
= dcache_pkt
= NULL
;
106 changeState(SimObject::Running
);
107 system
->totalNumInsts
= 0;
111 TimingSimpleCPU::~TimingSimpleCPU()
116 TimingSimpleCPU::serialize(ostream
&os
)
118 SimObject::State so_state
= SimObject::getState();
119 SERIALIZE_ENUM(so_state
);
120 BaseSimpleCPU::serialize(os
);
124 TimingSimpleCPU::unserialize(Checkpoint
*cp
, const string
§ion
)
126 SimObject::State so_state
;
127 UNSERIALIZE_ENUM(so_state
);
128 BaseSimpleCPU::unserialize(cp
, section
);
132 TimingSimpleCPU::drain(Event
*drain_event
)
134 // TimingSimpleCPU is ready to drain if it's not waiting for
135 // an access to complete.
136 if (_status
== Idle
|| _status
== Running
|| _status
== SwitchedOut
) {
137 changeState(SimObject::Drained
);
140 changeState(SimObject::Draining
);
141 drainEvent
= drain_event
;
147 TimingSimpleCPU::resume()
149 DPRINTF(SimpleCPU
, "Resume\n");
150 if (_status
!= SwitchedOut
&& _status
!= Idle
) {
151 assert(system
->getMemoryMode() == Enums::timing
);
153 if (fetchEvent
.scheduled())
154 deschedule(fetchEvent
);
156 schedule(fetchEvent
, nextCycle());
159 changeState(SimObject::Running
);
163 TimingSimpleCPU::switchOut()
165 assert(_status
== Running
|| _status
== Idle
);
166 _status
= SwitchedOut
;
167 numCycles
+= tickToCycles(curTick() - previousTick
);
169 // If we've been scheduled to resume but are then told to switch out,
170 // we'll need to cancel it.
171 if (fetchEvent
.scheduled())
172 deschedule(fetchEvent
);
177 TimingSimpleCPU::takeOverFrom(BaseCPU
*oldCPU
)
179 BaseCPU::takeOverFrom(oldCPU
, &icachePort
, &dcachePort
);
181 // if any of this CPU's ThreadContexts are active, mark the CPU as
182 // running and schedule its tick event.
183 for (int i
= 0; i
< threadContexts
.size(); ++i
) {
184 ThreadContext
*tc
= threadContexts
[i
];
185 if (tc
->status() == ThreadContext::Active
&& _status
!= Running
) {
191 if (_status
!= Running
) {
194 assert(threadContexts
.size() == 1);
195 previousTick
= curTick();
200 TimingSimpleCPU::activateContext(int thread_num
, int delay
)
202 DPRINTF(SimpleCPU
, "ActivateContext %d (%d cycles)\n", thread_num
, delay
);
204 assert(thread_num
== 0);
207 assert(_status
== Idle
);
212 // kick things off by initiating the fetch of the next instruction
213 schedule(fetchEvent
, nextCycle(curTick() + ticks(delay
)));
218 TimingSimpleCPU::suspendContext(int thread_num
)
220 DPRINTF(SimpleCPU
, "SuspendContext %d\n", thread_num
);
222 assert(thread_num
== 0);
228 assert(_status
== Running
);
230 // just change status to Idle... if status != Running,
231 // completeInst() will not initiate fetch of next instruction.
238 TimingSimpleCPU::handleReadPacket(PacketPtr pkt
)
240 RequestPtr req
= pkt
->req
;
241 if (req
->isMmappedIpr()) {
243 delay
= TheISA::handleIprRead(thread
->getTC(), pkt
);
244 new IprEvent(pkt
, this, nextCycle(curTick() + delay
));
245 _status
= DcacheWaitResponse
;
247 } else if (!dcachePort
.sendTiming(pkt
)) {
248 _status
= DcacheRetry
;
251 _status
= DcacheWaitResponse
;
252 // memory system takes ownership of packet
255 return dcache_pkt
== NULL
;
259 TimingSimpleCPU::sendData(RequestPtr req
, uint8_t *data
, uint64_t *res
,
263 buildPacket(pkt
, req
, read
);
264 pkt
->dataDynamicArray
<uint8_t>(data
);
265 if (req
->getFlags().isSet(Request::NO_ACCESS
)) {
268 completeDataAccess(pkt
);
270 handleReadPacket(pkt
);
272 bool do_access
= true; // flag to suppress cache access
275 do_access
= TheISA::handleLockedWrite(thread
, req
);
276 } else if (req
->isCondSwap()) {
278 req
->setExtraData(*res
);
285 _status
= DcacheWaitResponse
;
286 completeDataAccess(pkt
);
292 TimingSimpleCPU::sendSplitData(RequestPtr req1
, RequestPtr req2
,
293 RequestPtr req
, uint8_t *data
, bool read
)
295 PacketPtr pkt1
, pkt2
;
296 buildSplitPacket(pkt1
, pkt2
, req1
, req2
, req
, data
, read
);
297 if (req
->getFlags().isSet(Request::NO_ACCESS
)) {
299 pkt1
->makeResponse();
300 completeDataAccess(pkt1
);
302 SplitFragmentSenderState
* send_state
=
303 dynamic_cast<SplitFragmentSenderState
*>(pkt1
->senderState
);
304 if (handleReadPacket(pkt1
)) {
305 send_state
->clearFromParent();
306 send_state
= dynamic_cast<SplitFragmentSenderState
*>(
308 if (handleReadPacket(pkt2
)) {
309 send_state
->clearFromParent();
314 SplitFragmentSenderState
* send_state
=
315 dynamic_cast<SplitFragmentSenderState
*>(pkt1
->senderState
);
316 if (handleWritePacket()) {
317 send_state
->clearFromParent();
319 send_state
= dynamic_cast<SplitFragmentSenderState
*>(
321 if (handleWritePacket()) {
322 send_state
->clearFromParent();
329 TimingSimpleCPU::translationFault(Fault fault
)
331 // fault may be NoFault in cases where a fault is suppressed,
332 // for instance prefetches.
333 numCycles
+= tickToCycles(curTick() - previousTick
);
334 previousTick
= curTick();
337 // Since there was a fault, we shouldn't trace this instruction.
344 if (getState() == SimObject::Draining
) {
353 TimingSimpleCPU::buildPacket(PacketPtr
&pkt
, RequestPtr req
, bool read
)
357 cmd
= MemCmd::ReadReq
;
359 cmd
= MemCmd::LoadLockedReq
;
361 cmd
= MemCmd::WriteReq
;
363 cmd
= MemCmd::StoreCondReq
;
364 } else if (req
->isSwap()) {
365 cmd
= MemCmd::SwapReq
;
368 pkt
= new Packet(req
, cmd
, Packet::Broadcast
);
372 TimingSimpleCPU::buildSplitPacket(PacketPtr
&pkt1
, PacketPtr
&pkt2
,
373 RequestPtr req1
, RequestPtr req2
, RequestPtr req
,
374 uint8_t *data
, bool read
)
378 assert(!req1
->isMmappedIpr() && !req2
->isMmappedIpr());
380 if (req
->getFlags().isSet(Request::NO_ACCESS
)) {
381 buildPacket(pkt1
, req
, read
);
385 buildPacket(pkt1
, req1
, read
);
386 buildPacket(pkt2
, req2
, read
);
388 req
->setPhys(req1
->getPaddr(), req
->getSize(), req1
->getFlags());
389 PacketPtr pkt
= new Packet(req
, pkt1
->cmd
.responseCommand(),
392 pkt
->dataDynamicArray
<uint8_t>(data
);
393 pkt1
->dataStatic
<uint8_t>(data
);
394 pkt2
->dataStatic
<uint8_t>(data
+ req1
->getSize());
396 SplitMainSenderState
* main_send_state
= new SplitMainSenderState
;
397 pkt
->senderState
= main_send_state
;
398 main_send_state
->fragments
[0] = pkt1
;
399 main_send_state
->fragments
[1] = pkt2
;
400 main_send_state
->outstanding
= 2;
401 pkt1
->senderState
= new SplitFragmentSenderState(pkt
, 0);
402 pkt2
->senderState
= new SplitFragmentSenderState(pkt
, 1);
406 TimingSimpleCPU::readMem(Addr addr
, uint8_t *data
,
407 unsigned size
, unsigned flags
)
411 const ThreadID tid
= 0;
412 const Addr pc
= thread
->instAddr();
413 unsigned block_size
= dcachePort
.peerBlockSize();
414 BaseTLB::Mode mode
= BaseTLB::Read
;
417 traceData
->setAddr(addr
);
420 RequestPtr req
= new Request(asid
, addr
, size
,
421 flags
, pc
, _cpuId
, tid
);
423 Addr split_addr
= roundDown(addr
+ size
- 1, block_size
);
424 assert(split_addr
<= addr
|| split_addr
- addr
< block_size
);
426 _status
= DTBWaitResponse
;
427 if (split_addr
> addr
) {
428 RequestPtr req1
, req2
;
429 assert(!req
->isLLSC() && !req
->isSwap());
430 req
->splitOnVaddr(split_addr
, req1
, req2
);
432 WholeTranslationState
*state
=
433 new WholeTranslationState(req
, req1
, req2
, new uint8_t[size
],
435 DataTranslation
<TimingSimpleCPU
*> *trans1
=
436 new DataTranslation
<TimingSimpleCPU
*>(this, state
, 0);
437 DataTranslation
<TimingSimpleCPU
*> *trans2
=
438 new DataTranslation
<TimingSimpleCPU
*>(this, state
, 1);
440 thread
->dtb
->translateTiming(req1
, tc
, trans1
, mode
);
441 thread
->dtb
->translateTiming(req2
, tc
, trans2
, mode
);
443 WholeTranslationState
*state
=
444 new WholeTranslationState(req
, new uint8_t[size
], NULL
, mode
);
445 DataTranslation
<TimingSimpleCPU
*> *translation
446 = new DataTranslation
<TimingSimpleCPU
*>(this, state
);
447 thread
->dtb
->translateTiming(req
, tc
, translation
, mode
);
454 TimingSimpleCPU::handleWritePacket()
456 RequestPtr req
= dcache_pkt
->req
;
457 if (req
->isMmappedIpr()) {
459 delay
= TheISA::handleIprWrite(thread
->getTC(), dcache_pkt
);
460 new IprEvent(dcache_pkt
, this, nextCycle(curTick() + delay
));
461 _status
= DcacheWaitResponse
;
463 } else if (!dcachePort
.sendTiming(dcache_pkt
)) {
464 _status
= DcacheRetry
;
466 _status
= DcacheWaitResponse
;
467 // memory system takes ownership of packet
470 return dcache_pkt
== NULL
;
474 TimingSimpleCPU::writeMem(uint8_t *data
, unsigned size
,
475 Addr addr
, unsigned flags
, uint64_t *res
)
477 uint8_t *newData
= new uint8_t[size
];
478 memcpy(newData
, data
, size
);
481 const ThreadID tid
= 0;
482 const Addr pc
= thread
->instAddr();
483 unsigned block_size
= dcachePort
.peerBlockSize();
484 BaseTLB::Mode mode
= BaseTLB::Write
;
487 traceData
->setAddr(addr
);
490 RequestPtr req
= new Request(asid
, addr
, size
,
491 flags
, pc
, _cpuId
, tid
);
493 Addr split_addr
= roundDown(addr
+ size
- 1, block_size
);
494 assert(split_addr
<= addr
|| split_addr
- addr
< block_size
);
496 _status
= DTBWaitResponse
;
497 if (split_addr
> addr
) {
498 RequestPtr req1
, req2
;
499 assert(!req
->isLLSC() && !req
->isSwap());
500 req
->splitOnVaddr(split_addr
, req1
, req2
);
502 WholeTranslationState
*state
=
503 new WholeTranslationState(req
, req1
, req2
, newData
, res
, mode
);
504 DataTranslation
<TimingSimpleCPU
*> *trans1
=
505 new DataTranslation
<TimingSimpleCPU
*>(this, state
, 0);
506 DataTranslation
<TimingSimpleCPU
*> *trans2
=
507 new DataTranslation
<TimingSimpleCPU
*>(this, state
, 1);
509 thread
->dtb
->translateTiming(req1
, tc
, trans1
, mode
);
510 thread
->dtb
->translateTiming(req2
, tc
, trans2
, mode
);
512 WholeTranslationState
*state
=
513 new WholeTranslationState(req
, newData
, res
, mode
);
514 DataTranslation
<TimingSimpleCPU
*> *translation
=
515 new DataTranslation
<TimingSimpleCPU
*>(this, state
);
516 thread
->dtb
->translateTiming(req
, tc
, translation
, mode
);
519 // Translation faults will be returned via finishTranslation()
525 TimingSimpleCPU::finishTranslation(WholeTranslationState
*state
)
529 if (state
->getFault() != NoFault
) {
530 if (state
->isPrefetch()) {
533 delete [] state
->data
;
535 translationFault(state
->getFault());
537 if (!state
->isSplit
) {
538 sendData(state
->mainReq
, state
->data
, state
->res
,
539 state
->mode
== BaseTLB::Read
);
541 sendSplitData(state
->sreqLow
, state
->sreqHigh
, state
->mainReq
,
542 state
->data
, state
->mode
== BaseTLB::Read
);
551 TimingSimpleCPU::fetch()
553 DPRINTF(SimpleCPU
, "Fetch\n");
555 if (!curStaticInst
|| !curStaticInst
->isDelayedCommit())
556 checkForInterrupts();
560 // We must have just got suspended by a PC event
564 TheISA::PCState pcState
= thread
->pcState();
565 bool needToFetch
= !isRomMicroPC(pcState
.microPC()) && !curMacroStaticInst
;
569 Request
*ifetch_req
= new Request();
570 ifetch_req
->setThreadContext(_cpuId
, /* thread ID */ 0);
571 setupFetchRequest(ifetch_req
);
572 DPRINTF(SimpleCPU
, "Translating address %#x\n", ifetch_req
->getVaddr());
573 thread
->itb
->translateTiming(ifetch_req
, tc
, &fetchTranslation
,
576 _status
= IcacheWaitResponse
;
577 completeIfetch(NULL
);
579 numCycles
+= tickToCycles(curTick() - previousTick
);
580 previousTick
= curTick();
586 TimingSimpleCPU::sendFetch(Fault fault
, RequestPtr req
, ThreadContext
*tc
)
588 if (fault
== NoFault
) {
589 DPRINTF(SimpleCPU
, "Sending fetch for addr %#x(pa: %#x)\n",
590 req
->getVaddr(), req
->getPaddr());
591 ifetch_pkt
= new Packet(req
, MemCmd::ReadReq
, Packet::Broadcast
);
592 ifetch_pkt
->dataStatic(&inst
);
593 DPRINTF(SimpleCPU
, " -- pkt addr: %#x\n", ifetch_pkt
->getAddr());
595 if (!icachePort
.sendTiming(ifetch_pkt
)) {
596 // Need to wait for retry
597 _status
= IcacheRetry
;
599 // Need to wait for cache to respond
600 _status
= IcacheWaitResponse
;
601 // ownership of packet transferred to memory system
605 DPRINTF(SimpleCPU
, "Translation of addr %#x faulted\n", req
->getVaddr());
607 // fetch fault: advance directly to next instruction (fault handler)
612 numCycles
+= tickToCycles(curTick() - previousTick
);
613 previousTick
= curTick();
618 TimingSimpleCPU::advanceInst(Fault fault
)
621 if (_status
== Faulting
)
624 if (fault
!= NoFault
) {
626 DPRINTF(SimpleCPU
, "Fault occured, scheduling fetch event\n");
627 reschedule(fetchEvent
, nextCycle(), true);
636 if (_status
== Running
) {
637 // kick off fetch of next instruction... callback from icache
638 // response will cause that instruction to be executed,
639 // keeping the CPU running.
646 TimingSimpleCPU::completeIfetch(PacketPtr pkt
)
648 DPRINTF(SimpleCPU
, "Complete ICache Fetch for addr %#x\n", pkt
?
651 // received a response from the icache: execute the received
654 assert(!pkt
|| !pkt
->isError());
655 assert(_status
== IcacheWaitResponse
);
659 numCycles
+= tickToCycles(curTick() - previousTick
);
660 previousTick
= curTick();
662 if (getState() == SimObject::Draining
) {
673 if (curStaticInst
&& curStaticInst
->isMemRef()) {
674 // load or store: just send to dcache
675 Fault fault
= curStaticInst
->initiateAcc(this, traceData
);
677 // If we're not running now the instruction will complete in a dcache
678 // response callback or the instruction faulted and has started an
680 if (_status
== Running
) {
681 if (fault
!= NoFault
&& traceData
) {
682 // If there was a fault, we shouldn't trace this instruction.
688 // @todo remove me after debugging with legion done
689 if (curStaticInst
&& (!curStaticInst
->isMicroop() ||
690 curStaticInst
->isFirstMicroop()))
694 } else if (curStaticInst
) {
695 // non-memory instruction: execute completely now
696 Fault fault
= curStaticInst
->execute(this, traceData
);
698 // keep an instruction count
699 if (fault
== NoFault
)
701 else if (traceData
&& !DTRACE(ExecFaulting
)) {
707 // @todo remove me after debugging with legion done
708 if (curStaticInst
&& (!curStaticInst
->isMicroop() ||
709 curStaticInst
->isFirstMicroop()))
713 advanceInst(NoFault
);
723 TimingSimpleCPU::IcachePort::ITickEvent::process()
725 cpu
->completeIfetch(pkt
);
729 TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt
)
731 if (pkt
->isResponse() && !pkt
->wasNacked()) {
732 DPRINTF(SimpleCPU
, "Received timing response %#x\n", pkt
->getAddr());
733 // delay processing of returned data until next CPU clock edge
734 Tick next_tick
= cpu
->nextCycle(curTick());
736 if (next_tick
== curTick())
737 cpu
->completeIfetch(pkt
);
739 tickEvent
.schedule(pkt
, next_tick
);
742 } else if (pkt
->wasNacked()) {
743 assert(cpu
->_status
== IcacheWaitResponse
);
745 if (!sendTiming(pkt
)) {
746 cpu
->_status
= IcacheRetry
;
747 cpu
->ifetch_pkt
= pkt
;
750 //Snooping a Coherence Request, do nothing
755 TimingSimpleCPU::IcachePort::recvRetry()
757 // we shouldn't get a retry unless we have a packet that we're
758 // waiting to transmit
759 assert(cpu
->ifetch_pkt
!= NULL
);
760 assert(cpu
->_status
== IcacheRetry
);
761 PacketPtr tmp
= cpu
->ifetch_pkt
;
762 if (sendTiming(tmp
)) {
763 cpu
->_status
= IcacheWaitResponse
;
764 cpu
->ifetch_pkt
= NULL
;
769 TimingSimpleCPU::completeDataAccess(PacketPtr pkt
)
771 // received a response from the dcache: complete the load or store
773 assert(!pkt
->isError());
774 assert(_status
== DcacheWaitResponse
|| _status
== DTBWaitResponse
||
775 pkt
->req
->getFlags().isSet(Request::NO_ACCESS
));
777 numCycles
+= tickToCycles(curTick() - previousTick
);
778 previousTick
= curTick();
780 if (pkt
->senderState
) {
781 SplitFragmentSenderState
* send_state
=
782 dynamic_cast<SplitFragmentSenderState
*>(pkt
->senderState
);
786 PacketPtr big_pkt
= send_state
->bigPkt
;
789 SplitMainSenderState
* main_send_state
=
790 dynamic_cast<SplitMainSenderState
*>(big_pkt
->senderState
);
791 assert(main_send_state
);
792 // Record the fact that this packet is no longer outstanding.
793 assert(main_send_state
->outstanding
!= 0);
794 main_send_state
->outstanding
--;
796 if (main_send_state
->outstanding
) {
799 delete main_send_state
;
800 big_pkt
->senderState
= NULL
;
807 Fault fault
= curStaticInst
->completeAcc(pkt
, this, traceData
);
809 // keep an instruction count
810 if (fault
== NoFault
)
812 else if (traceData
) {
813 // If there was a fault, we shouldn't trace this instruction.
818 // the locked flag may be cleared on the response packet, so check
819 // pkt->req and not pkt to see if it was a load-locked
820 if (pkt
->isRead() && pkt
->req
->isLLSC()) {
821 TheISA::handleLockedRead(thread
, pkt
->req
);
829 if (getState() == SimObject::Draining
) {
841 TimingSimpleCPU::completeDrain()
843 DPRINTF(Config
, "Done draining\n");
844 changeState(SimObject::Drained
);
845 drainEvent
->process();
849 TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt
)
851 if (pkt
->isResponse() && !pkt
->wasNacked()) {
852 // delay processing of returned data until next CPU clock edge
853 Tick next_tick
= cpu
->nextCycle(curTick());
855 if (next_tick
== curTick()) {
856 cpu
->completeDataAccess(pkt
);
858 if (!tickEvent
.scheduled()) {
859 tickEvent
.schedule(pkt
, next_tick
);
861 // In the case of a split transaction and a cache that is
862 // faster than a CPU we could get two responses before
864 if (!retryEvent
.scheduled())
865 cpu
->schedule(retryEvent
, next_tick
);
872 else if (pkt
->wasNacked()) {
873 assert(cpu
->_status
== DcacheWaitResponse
);
875 if (!sendTiming(pkt
)) {
876 cpu
->_status
= DcacheRetry
;
877 cpu
->dcache_pkt
= pkt
;
880 //Snooping a Coherence Request, do nothing
885 TimingSimpleCPU::DcachePort::DTickEvent::process()
887 cpu
->completeDataAccess(pkt
);
891 TimingSimpleCPU::DcachePort::recvRetry()
893 // we shouldn't get a retry unless we have a packet that we're
894 // waiting to transmit
895 assert(cpu
->dcache_pkt
!= NULL
);
896 assert(cpu
->_status
== DcacheRetry
);
897 PacketPtr tmp
= cpu
->dcache_pkt
;
898 if (tmp
->senderState
) {
899 // This is a packet from a split access.
900 SplitFragmentSenderState
* send_state
=
901 dynamic_cast<SplitFragmentSenderState
*>(tmp
->senderState
);
903 PacketPtr big_pkt
= send_state
->bigPkt
;
905 SplitMainSenderState
* main_send_state
=
906 dynamic_cast<SplitMainSenderState
*>(big_pkt
->senderState
);
907 assert(main_send_state
);
909 if (sendTiming(tmp
)) {
910 // If we were able to send without retrying, record that fact
911 // and try sending the other fragment.
912 send_state
->clearFromParent();
913 int other_index
= main_send_state
->getPendingFragment();
914 if (other_index
> 0) {
915 tmp
= main_send_state
->fragments
[other_index
];
916 cpu
->dcache_pkt
= tmp
;
917 if ((big_pkt
->isRead() && cpu
->handleReadPacket(tmp
)) ||
918 (big_pkt
->isWrite() && cpu
->handleWritePacket())) {
919 main_send_state
->fragments
[other_index
] = NULL
;
922 cpu
->_status
= DcacheWaitResponse
;
923 // memory system takes ownership of packet
924 cpu
->dcache_pkt
= NULL
;
927 } else if (sendTiming(tmp
)) {
928 cpu
->_status
= DcacheWaitResponse
;
929 // memory system takes ownership of packet
930 cpu
->dcache_pkt
= NULL
;
934 TimingSimpleCPU::IprEvent::IprEvent(Packet
*_pkt
, TimingSimpleCPU
*_cpu
,
936 : pkt(_pkt
), cpu(_cpu
)
938 cpu
->schedule(this, t
);
942 TimingSimpleCPU::IprEvent::process()
944 cpu
->completeDataAccess(pkt
);
948 TimingSimpleCPU::IprEvent::description() const
950 return "Timing Simple CPU Delay IPR event";
955 TimingSimpleCPU::printAddr(Addr a
)
957 dcachePort
.printAddr(a
);
961 ////////////////////////////////////////////////////////////////////////
963 // TimingSimpleCPU Simulation Object
966 TimingSimpleCPUParams::create()
969 if (!FullSystem
&& workload
.size() != 1)
970 panic("only one workload allowed");
971 return new TimingSimpleCPU(this);