src/cpu/simple/timing.cc

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #include "arch/utility.hh"
  30 #include "cpu/exetrace.hh"
  31 #include "cpu/simple/timing.hh"
  32 #include "mem/packet_impl.hh"
  33 #include "sim/builder.hh"
  34
  35 using namespace std;
  36 using namespace TheISA;
  37
  38
  39 void
  40 TimingSimpleCPU::init()
  41 {
  42     //Create Memory Ports (conect them up)
  43     Port *mem_dport = mem->getPort("");
  44     dcachePort.setPeer(mem_dport);
  45     mem_dport->setPeer(&dcachePort);
  46
  47     Port *mem_iport = mem->getPort("");
  48     icachePort.setPeer(mem_iport);
  49     mem_iport->setPeer(&icachePort);
  50
  51     BaseCPU::init();
  52 #if FULL_SYSTEM
  53     for (int i = 0; i < execContexts.size(); ++i) {
  54         ExecContext *xc = execContexts[i];
  55
  56         // initialize CPU, including PC
  57         TheISA::initCPU(xc, xc->readCpuId());
  58     }
  59 #endif
  60 }
  61
  62 Tick
  63 TimingSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
  64 {
  65     panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
  66     return curTick;
  67 }
  68
  69 void
  70 TimingSimpleCPU::CpuPort::recvFunctional(Packet *pkt)
  71 {
  72     panic("TimingSimpleCPU doesn't expect recvFunctional callback!");
  73 }
  74
  75 void
  76 TimingSimpleCPU::CpuPort::recvStatusChange(Status status)
  77 {
  78     if (status == RangeChange)
  79         return;
  80
  81     panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
  82 }
  83
  84 TimingSimpleCPU::TimingSimpleCPU(Params *p)
  85     : BaseSimpleCPU(p), icachePort(this), dcachePort(this)
  86 {
  87     _status = Idle;
  88     ifetch_pkt = dcache_pkt = NULL;
  89 }
  90
  91
  92 TimingSimpleCPU::~TimingSimpleCPU()
  93 {
  94 }
  95
  96 void
  97 TimingSimpleCPU::serialize(ostream &os)
  98 {
  99     BaseSimpleCPU::serialize(os);
 100     SERIALIZE_ENUM(_status);
 101 }
 102
 103 void
 104 TimingSimpleCPU::unserialize(Checkpoint *cp, const string &section)
 105 {
 106     BaseSimpleCPU::unserialize(cp, section);
 107     UNSERIALIZE_ENUM(_status);
 108 }
 109
 110 void
 111 TimingSimpleCPU::switchOut(Sampler *s)
 112 {
 113     sampler = s;
 114     if (status() == Running) {
 115         _status = SwitchedOut;
 116     }
 117     sampler->signalSwitched();
 118 }
 119
 120
 121 void
 122 TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
 123 {
 124     BaseCPU::takeOverFrom(oldCPU);
 125
 126     // if any of this CPU's ExecContexts are active, mark the CPU as
 127     // running and schedule its tick event.
 128     for (int i = 0; i < execContexts.size(); ++i) {
 129         ExecContext *xc = execContexts[i];
 130         if (xc->status() == ExecContext::Active && _status != Running) {
 131             _status = Running;
 132             break;
 133         }
 134     }
 135 }
 136
 137
 138 void
 139 TimingSimpleCPU::activateContext(int thread_num, int delay)
 140 {
 141     assert(thread_num == 0);
 142     assert(cpuXC);
 143
 144     assert(_status == Idle);
 145
 146     notIdleFraction++;
 147     _status = Running;
 148     // kick things off by initiating the fetch of the next instruction
 149     Event *e =
 150         new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, true);
 151     e->schedule(curTick + cycles(delay));
 152 }
 153
 154
 155 void
 156 TimingSimpleCPU::suspendContext(int thread_num)
 157 {
 158     assert(thread_num == 0);
 159     assert(cpuXC);
 160
 161     assert(_status == Running);
 162
 163     // just change status to Idle... if status != Running,
 164     // completeInst() will not initiate fetch of next instruction.
 165
 166     notIdleFraction--;
 167     _status = Idle;
 168 }
 169
 170
 171 template <class T>
 172 Fault
 173 TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
 174 {
 175     Request *data_read_req = new Request(true);
 176
 177     data_read_req->setVaddr(addr);
 178     data_read_req->setSize(sizeof(T));
 179     data_read_req->setFlags(flags);
 180     data_read_req->setTime(curTick);
 181
 182     if (traceData) {
 183         traceData->setAddr(data_read_req->getVaddr());
 184     }
 185
 186    // translate to physical address
 187     Fault fault = cpuXC->translateDataReadReq(data_read_req);
 188
 189     // Now do the access.
 190     if (fault == NoFault) {
 191         Packet *data_read_pkt =
 192             new Packet(data_read_req, Packet::ReadReq, Packet::Broadcast);
 193         data_read_pkt->dataDynamic<T>(new T);
 194
 195         if (!dcachePort.sendTiming(data_read_pkt)) {
 196             _status = DcacheRetry;
 197             dcache_pkt = data_read_pkt;
 198         } else {
 199             _status = DcacheWaitResponse;
 200             dcache_pkt = NULL;
 201         }
 202     }
 203
 204     // This will need a new way to tell if it has a dcache attached.
 205     if (data_read_req->getFlags() & UNCACHEABLE)
 206         recordEvent("Uncached Read");
 207
 208     return fault;
 209 }
 210
 211 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 212
 213 template
 214 Fault
 215 TimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
 216
 217 template
 218 Fault
 219 TimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
 220
 221 template
 222 Fault
 223 TimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
 224
 225 template
 226 Fault
 227 TimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
 228
 229 #endif //DOXYGEN_SHOULD_SKIP_THIS
 230
 231 template<>
 232 Fault
 233 TimingSimpleCPU::read(Addr addr, double &data, unsigned flags)
 234 {
 235     return read(addr, *(uint64_t*)&data, flags);
 236 }
 237
 238 template<>
 239 Fault
 240 TimingSimpleCPU::read(Addr addr, float &data, unsigned flags)
 241 {
 242     return read(addr, *(uint32_t*)&data, flags);
 243 }
 244
 245
 246 template<>
 247 Fault
 248 TimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
 249 {
 250     return read(addr, (uint32_t&)data, flags);
 251 }
 252
 253
 254 template <class T>
 255 Fault
 256 TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
 257 {
 258     Request *data_write_req = new Request(true);
 259     data_write_req->setVaddr(addr);
 260     data_write_req->setTime(curTick);
 261     data_write_req->setSize(sizeof(T));
 262     data_write_req->setFlags(flags);
 263
 264     // translate to physical address
 265     Fault fault = cpuXC->translateDataWriteReq(data_write_req);
 266     // Now do the access.
 267     if (fault == NoFault) {
 268         Packet *data_write_pkt =
 269             new Packet(data_write_req, Packet::WriteReq, Packet::Broadcast);
 270         data_write_pkt->allocate();
 271         data_write_pkt->set(data);
 272
 273         if (!dcachePort.sendTiming(data_write_pkt)) {
 274             _status = DcacheRetry;
 275             dcache_pkt = data_write_pkt;
 276         } else {
 277             _status = DcacheWaitResponse;
 278             dcache_pkt = NULL;
 279         }
 280     }
 281
 282     // This will need a new way to tell if it's hooked up to a cache or not.
 283     if (data_write_req->getFlags() & UNCACHEABLE)
 284         recordEvent("Uncached Write");
 285
 286     // If the write needs to have a fault on the access, consider calling
 287     // changeStatus() and changing it to "bad addr write" or something.
 288     return fault;
 289 }
 290
 291
 292 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 293 template
 294 Fault
 295 TimingSimpleCPU::write(uint64_t data, Addr addr,
 296                        unsigned flags, uint64_t *res);
 297
 298 template
 299 Fault
 300 TimingSimpleCPU::write(uint32_t data, Addr addr,
 301                        unsigned flags, uint64_t *res);
 302
 303 template
 304 Fault
 305 TimingSimpleCPU::write(uint16_t data, Addr addr,
 306                        unsigned flags, uint64_t *res);
 307
 308 template
 309 Fault
 310 TimingSimpleCPU::write(uint8_t data, Addr addr,
 311                        unsigned flags, uint64_t *res);
 312
 313 #endif //DOXYGEN_SHOULD_SKIP_THIS
 314
 315 template<>
 316 Fault
 317 TimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
 318 {
 319     return write(*(uint64_t*)&data, addr, flags, res);
 320 }
 321
 322 template<>
 323 Fault
 324 TimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
 325 {
 326     return write(*(uint32_t*)&data, addr, flags, res);
 327 }
 328
 329
 330 template<>
 331 Fault
 332 TimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
 333 {
 334     return write((uint32_t)data, addr, flags, res);
 335 }
 336
 337
 338 void
 339 TimingSimpleCPU::fetch()
 340 {
 341     checkForInterrupts();
 342
 343     Request *ifetch_req = new Request(true);
 344     ifetch_req->setSize(sizeof(MachInst));
 345
 346     ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
 347     ifetch_pkt->dataStatic(&inst);
 348
 349     Fault fault = setupFetchPacket(ifetch_pkt);
 350     if (fault == NoFault) {
 351         if (!icachePort.sendTiming(ifetch_pkt)) {
 352             // Need to wait for retry
 353             _status = IcacheRetry;
 354         } else {
 355             // Need to wait for cache to respond
 356             _status = IcacheWaitResponse;
 357             // ownership of packet transferred to memory system
 358             ifetch_pkt = NULL;
 359         }
 360     } else {
 361         // fetch fault: advance directly to next instruction (fault handler)
 362         advanceInst(fault);
 363     }
 364 }
 365
 366
 367 void
 368 TimingSimpleCPU::advanceInst(Fault fault)
 369 {
 370     advancePC(fault);
 371
 372     if (_status == Running) {
 373         // kick off fetch of next instruction... callback from icache
 374         // response will cause that instruction to be executed,
 375         // keeping the CPU running.
 376         fetch();
 377     }
 378 }
 379
 380
 381 void
 382 TimingSimpleCPU::completeIfetch(Packet *pkt)
 383 {
 384     // received a response from the icache: execute the received
 385     // instruction
 386     assert(pkt->result == Packet::Success);
 387     assert(_status == IcacheWaitResponse);
 388     _status = Running;
 389
 390     delete pkt->req;
 391     delete pkt;
 392
 393     preExecute();
 394     if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) {
 395         // load or store: just send to dcache
 396         Fault fault = curStaticInst->initiateAcc(this, traceData);
 397         if (fault == NoFault) {
 398             // successfully initiated access: instruction will
 399             // complete in dcache response callback
 400             assert(_status == DcacheWaitResponse);
 401         } else {
 402             // fault: complete now to invoke fault handler
 403             postExecute();
 404             advanceInst(fault);
 405         }
 406     } else {
 407         // non-memory instruction: execute completely now
 408         Fault fault = curStaticInst->execute(this, traceData);
 409         postExecute();
 410         advanceInst(fault);
 411     }
 412 }
 413
 414
 415 bool
 416 TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
 417 {
 418     cpu->completeIfetch(pkt);
 419     return true;
 420 }
 421
 422 Packet *
 423 TimingSimpleCPU::IcachePort::recvRetry()
 424 {
 425     // we shouldn't get a retry unless we have a packet that we're
 426     // waiting to transmit
 427     assert(cpu->ifetch_pkt != NULL);
 428     assert(cpu->_status == IcacheRetry);
 429     cpu->_status = IcacheWaitResponse;
 430     Packet *tmp = cpu->ifetch_pkt;
 431     cpu->ifetch_pkt = NULL;
 432     return tmp;
 433 }
 434
 435 void
 436 TimingSimpleCPU::completeDataAccess(Packet *pkt)
 437 {
 438     // received a response from the dcache: complete the load or store
 439     // instruction
 440     assert(pkt->result == Packet::Success);
 441     assert(_status == DcacheWaitResponse);
 442     _status = Running;
 443
 444     Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
 445
 446     delete pkt->req;
 447     delete pkt;
 448
 449     postExecute();
 450     advanceInst(fault);
 451 }
 452
 453
 454
 455 bool
 456 TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt)
 457 {
 458     cpu->completeDataAccess(pkt);
 459     return true;
 460 }
 461
 462 Packet *
 463 TimingSimpleCPU::DcachePort::recvRetry()
 464 {
 465     // we shouldn't get a retry unless we have a packet that we're
 466     // waiting to transmit
 467     assert(cpu->dcache_pkt != NULL);
 468     assert(cpu->_status == DcacheRetry);
 469     cpu->_status = DcacheWaitResponse;
 470     Packet *tmp = cpu->dcache_pkt;
 471     cpu->dcache_pkt = NULL;
 472     return tmp;
 473 }
 474
 475
 476 ////////////////////////////////////////////////////////////////////////
 477 //
 478 //  TimingSimpleCPU Simulation Object
 479 //
 480 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU)
 481
 482     Param<Counter> max_insts_any_thread;
 483     Param<Counter> max_insts_all_threads;
 484     Param<Counter> max_loads_any_thread;
 485     Param<Counter> max_loads_all_threads;
 486     SimObjectParam<MemObject *> mem;
 487
 488 #if FULL_SYSTEM
 489     SimObjectParam<AlphaITB *> itb;
 490     SimObjectParam<AlphaDTB *> dtb;
 491     SimObjectParam<System *> system;
 492     Param<int> cpu_id;
 493     Param<Tick> profile;
 494 #else
 495     SimObjectParam<Process *> workload;
 496 #endif // FULL_SYSTEM
 497
 498     Param<int> clock;
 499
 500     Param<bool> defer_registration;
 501     Param<int> width;
 502     Param<bool> function_trace;
 503     Param<Tick> function_trace_start;
 504     Param<bool> simulate_stalls;
 505
 506 END_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU)
 507
 508 BEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU)
 509
 510     INIT_PARAM(max_insts_any_thread,
 511                "terminate when any thread reaches this inst count"),
 512     INIT_PARAM(max_insts_all_threads,
 513                "terminate when all threads have reached this inst count"),
 514     INIT_PARAM(max_loads_any_thread,
 515                "terminate when any thread reaches this load count"),
 516     INIT_PARAM(max_loads_all_threads,
 517                "terminate when all threads have reached this load count"),
 518     INIT_PARAM(mem, "memory"),
 519
 520 #if FULL_SYSTEM
 521     INIT_PARAM(itb, "Instruction TLB"),
 522     INIT_PARAM(dtb, "Data TLB"),
 523     INIT_PARAM(system, "system object"),
 524     INIT_PARAM(cpu_id, "processor ID"),
 525     INIT_PARAM(profile, ""),
 526 #else
 527     INIT_PARAM(workload, "processes to run"),
 528 #endif // FULL_SYSTEM
 529
 530     INIT_PARAM(clock, "clock speed"),
 531     INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
 532     INIT_PARAM(width, "cpu width"),
 533     INIT_PARAM(function_trace, "Enable function trace"),
 534     INIT_PARAM(function_trace_start, "Cycle to start function trace"),
 535     INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
 536
 537 END_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU)
 538
 539
 540 CREATE_SIM_OBJECT(TimingSimpleCPU)
 541 {
 542     TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params();
 543     params->name = getInstanceName();
 544     params->numberOfThreads = 1;
 545     params->max_insts_any_thread = max_insts_any_thread;
 546     params->max_insts_all_threads = max_insts_all_threads;
 547     params->max_loads_any_thread = max_loads_any_thread;
 548     params->max_loads_all_threads = max_loads_all_threads;
 549     params->deferRegistration = defer_registration;
 550     params->clock = clock;
 551     params->functionTrace = function_trace;
 552     params->functionTraceStart = function_trace_start;
 553     params->mem = mem;
 554
 555 #if FULL_SYSTEM
 556     params->itb = itb;
 557     params->dtb = dtb;
 558     params->system = system;
 559     params->cpu_id = cpu_id;
 560     params->profile = profile;
 561 #else
 562     params->process = workload;
 563 #endif
 564
 565     TimingSimpleCPU *cpu = new TimingSimpleCPU(params);
 566     return cpu;
 567 }
 568
 569 REGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU)
 570