2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
31 #include "arch/locked_mem.hh"
32 #include "arch/mmaped_ipr.hh"
33 #include "arch/utility.hh"
34 #include "base/bigint.hh"
35 #include "cpu/exetrace.hh"
36 #include "cpu/simple/timing.hh"
37 #include "mem/packet.hh"
38 #include "mem/packet_access.hh"
39 #include "params/TimingSimpleCPU.hh"
40 #include "sim/system.hh"
43 using namespace TheISA
;
46 TimingSimpleCPU::getPort(const std::string
&if_name
, int idx
)
48 if (if_name
== "dcache_port")
50 else if (if_name
== "icache_port")
53 panic("No Such Port\n");
57 TimingSimpleCPU::init()
60 cpuId
= tc
->readCpuId();
62 for (int i
= 0; i
< threadContexts
.size(); ++i
) {
63 ThreadContext
*tc
= threadContexts
[i
];
65 // initialize CPU, including PC
66 TheISA::initCPU(tc
, cpuId
);
72 TimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt
)
74 panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
79 TimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt
)
81 //No internal storage to update, jusst return
86 TimingSimpleCPU::CpuPort::recvStatusChange(Status status
)
88 if (status
== RangeChange
) {
89 if (!snoopRangeSent
) {
90 snoopRangeSent
= true;
91 sendStatusChange(Port::RangeChange
);
96 panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
101 TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt
, Tick t
)
107 TimingSimpleCPU::TimingSimpleCPU(Params
*p
)
108 : BaseSimpleCPU(p
), icachePort(this, p
->clock
), dcachePort(this, p
->clock
)
112 icachePort
.snoopRangeSent
= false;
113 dcachePort
.snoopRangeSent
= false;
115 ifetch_pkt
= dcache_pkt
= NULL
;
119 changeState(SimObject::Running
);
123 TimingSimpleCPU::~TimingSimpleCPU()
128 TimingSimpleCPU::serialize(ostream
&os
)
130 SimObject::State so_state
= SimObject::getState();
131 SERIALIZE_ENUM(so_state
);
132 BaseSimpleCPU::serialize(os
);
136 TimingSimpleCPU::unserialize(Checkpoint
*cp
, const string
§ion
)
138 SimObject::State so_state
;
139 UNSERIALIZE_ENUM(so_state
);
140 BaseSimpleCPU::unserialize(cp
, section
);
144 TimingSimpleCPU::drain(Event
*drain_event
)
146 // TimingSimpleCPU is ready to drain if it's not waiting for
147 // an access to complete.
148 if (_status
== Idle
|| _status
== Running
|| _status
== SwitchedOut
) {
149 changeState(SimObject::Drained
);
152 changeState(SimObject::Draining
);
153 drainEvent
= drain_event
;
159 TimingSimpleCPU::resume()
161 DPRINTF(SimpleCPU
, "Resume\n");
162 if (_status
!= SwitchedOut
&& _status
!= Idle
) {
163 assert(system
->getMemoryMode() == Enums::timing
);
165 // Delete the old event if it existed.
167 if (fetchEvent
->scheduled())
168 fetchEvent
->deschedule();
173 fetchEvent
= new FetchEvent(this, nextCycle());
176 changeState(SimObject::Running
);
180 TimingSimpleCPU::switchOut()
182 assert(_status
== Running
|| _status
== Idle
);
183 _status
= SwitchedOut
;
184 numCycles
+= tickToCycles(curTick
- previousTick
);
186 // If we've been scheduled to resume but are then told to switch out,
187 // we'll need to cancel it.
188 if (fetchEvent
&& fetchEvent
->scheduled())
189 fetchEvent
->deschedule();
194 TimingSimpleCPU::takeOverFrom(BaseCPU
*oldCPU
)
196 BaseCPU::takeOverFrom(oldCPU
, &icachePort
, &dcachePort
);
198 // if any of this CPU's ThreadContexts are active, mark the CPU as
199 // running and schedule its tick event.
200 for (int i
= 0; i
< threadContexts
.size(); ++i
) {
201 ThreadContext
*tc
= threadContexts
[i
];
202 if (tc
->status() == ThreadContext::Active
&& _status
!= Running
) {
208 if (_status
!= Running
) {
211 assert(threadContexts
.size() == 1);
212 cpuId
= tc
->readCpuId();
213 previousTick
= curTick
;
218 TimingSimpleCPU::activateContext(int thread_num
, int delay
)
220 DPRINTF(SimpleCPU
, "ActivateContext %d (%d cycles)\n", thread_num
, delay
);
222 assert(thread_num
== 0);
225 assert(_status
== Idle
);
230 // kick things off by initiating the fetch of the next instruction
231 fetchEvent
= new FetchEvent(this, nextCycle(curTick
+ ticks(delay
)));
236 TimingSimpleCPU::suspendContext(int thread_num
)
238 DPRINTF(SimpleCPU
, "SuspendContext %d\n", thread_num
);
240 assert(thread_num
== 0);
243 assert(_status
== Running
);
245 // just change status to Idle... if status != Running,
246 // completeInst() will not initiate fetch of next instruction.
255 TimingSimpleCPU::read(Addr addr
, T
&data
, unsigned flags
)
258 new Request(/* asid */ 0, addr
, sizeof(T
), flags
, thread
->readPC(),
259 cpuId
, /* thread ID */ 0);
262 traceData
->setAddr(req
->getVaddr());
265 // translate to physical address
266 Fault fault
= thread
->translateDataReadReq(req
);
268 // Now do the access.
269 if (fault
== NoFault
) {
273 MemCmd::LoadLockedReq
: MemCmd::ReadReq
),
275 pkt
->dataDynamic
<T
>(new T
);
277 if (req
->isMmapedIpr()) {
279 delay
= TheISA::handleIprRead(thread
->getTC(), pkt
);
280 new IprEvent(pkt
, this, nextCycle(curTick
+ delay
));
281 _status
= DcacheWaitResponse
;
283 } else if (!dcachePort
.sendTiming(pkt
)) {
284 _status
= DcacheRetry
;
287 _status
= DcacheWaitResponse
;
288 // memory system takes ownership of packet
292 // This will need a new way to tell if it has a dcache attached.
293 if (req
->isUncacheable())
294 recordEvent("Uncached Read");
300 traceData
->setData(data
);
306 TimingSimpleCPU::translateDataReadAddr(Addr vaddr
, Addr
&paddr
,
307 int size
, unsigned flags
)
310 new Request(0, vaddr
, size
, flags
, thread
->readPC(), cpuId
, 0);
313 traceData
->setAddr(vaddr
);
316 Fault fault
= thread
->translateDataWriteReq(req
);
318 if (fault
== NoFault
)
319 paddr
= req
->getPaddr();
325 #ifndef DOXYGEN_SHOULD_SKIP_THIS
329 TimingSimpleCPU::read(Addr addr
, Twin64_t
&data
, unsigned flags
);
333 TimingSimpleCPU::read(Addr addr
, Twin32_t
&data
, unsigned flags
);
337 TimingSimpleCPU::read(Addr addr
, uint64_t &data
, unsigned flags
);
341 TimingSimpleCPU::read(Addr addr
, uint32_t &data
, unsigned flags
);
345 TimingSimpleCPU::read(Addr addr
, uint16_t &data
, unsigned flags
);
349 TimingSimpleCPU::read(Addr addr
, uint8_t &data
, unsigned flags
);
351 #endif //DOXYGEN_SHOULD_SKIP_THIS
355 TimingSimpleCPU::read(Addr addr
, double &data
, unsigned flags
)
357 return read(addr
, *(uint64_t*)&data
, flags
);
362 TimingSimpleCPU::read(Addr addr
, float &data
, unsigned flags
)
364 return read(addr
, *(uint32_t*)&data
, flags
);
370 TimingSimpleCPU::read(Addr addr
, int32_t &data
, unsigned flags
)
372 return read(addr
, (uint32_t&)data
, flags
);
378 TimingSimpleCPU::write(T data
, Addr addr
, unsigned flags
, uint64_t *res
)
381 new Request(/* asid */ 0, addr
, sizeof(T
), flags
, thread
->readPC(),
382 cpuId
, /* thread ID */ 0);
385 traceData
->setAddr(req
->getVaddr());
388 // translate to physical address
389 Fault fault
= thread
->translateDataWriteReq(req
);
391 // Now do the access.
392 if (fault
== NoFault
) {
393 MemCmd cmd
= MemCmd::WriteReq
; // default
394 bool do_access
= true; // flag to suppress cache access
396 if (req
->isLocked()) {
397 cmd
= MemCmd::StoreCondReq
;
398 do_access
= TheISA::handleLockedWrite(thread
, req
);
399 } else if (req
->isSwap()) {
400 cmd
= MemCmd::SwapReq
;
401 if (req
->isCondSwap()) {
403 req
->setExtraData(*res
);
407 // Note: need to allocate dcache_pkt even if do_access is
408 // false, as it's used unconditionally to call completeAcc().
409 assert(dcache_pkt
== NULL
);
410 dcache_pkt
= new Packet(req
, cmd
, Packet::Broadcast
);
411 dcache_pkt
->allocate();
412 dcache_pkt
->set(data
);
415 if (req
->isMmapedIpr()) {
417 dcache_pkt
->set(htog(data
));
418 delay
= TheISA::handleIprWrite(thread
->getTC(), dcache_pkt
);
419 new IprEvent(dcache_pkt
, this, nextCycle(curTick
+ delay
));
420 _status
= DcacheWaitResponse
;
422 } else if (!dcachePort
.sendTiming(dcache_pkt
)) {
423 _status
= DcacheRetry
;
425 _status
= DcacheWaitResponse
;
426 // memory system takes ownership of packet
430 // This will need a new way to tell if it's hooked up to a cache or not.
431 if (req
->isUncacheable())
432 recordEvent("Uncached Write");
438 traceData
->setData(data
);
441 // If the write needs to have a fault on the access, consider calling
442 // changeStatus() and changing it to "bad addr write" or something.
447 TimingSimpleCPU::translateDataWriteAddr(Addr vaddr
, Addr
&paddr
,
448 int size
, unsigned flags
)
451 new Request(0, vaddr
, size
, flags
, thread
->readPC(), cpuId
, 0);
454 traceData
->setAddr(vaddr
);
457 Fault fault
= thread
->translateDataWriteReq(req
);
459 if (fault
== NoFault
)
460 paddr
= req
->getPaddr();
467 #ifndef DOXYGEN_SHOULD_SKIP_THIS
470 TimingSimpleCPU::write(Twin32_t data
, Addr addr
,
471 unsigned flags
, uint64_t *res
);
475 TimingSimpleCPU::write(Twin64_t data
, Addr addr
,
476 unsigned flags
, uint64_t *res
);
480 TimingSimpleCPU::write(uint64_t data
, Addr addr
,
481 unsigned flags
, uint64_t *res
);
485 TimingSimpleCPU::write(uint32_t data
, Addr addr
,
486 unsigned flags
, uint64_t *res
);
490 TimingSimpleCPU::write(uint16_t data
, Addr addr
,
491 unsigned flags
, uint64_t *res
);
495 TimingSimpleCPU::write(uint8_t data
, Addr addr
,
496 unsigned flags
, uint64_t *res
);
498 #endif //DOXYGEN_SHOULD_SKIP_THIS
502 TimingSimpleCPU::write(double data
, Addr addr
, unsigned flags
, uint64_t *res
)
504 return write(*(uint64_t*)&data
, addr
, flags
, res
);
509 TimingSimpleCPU::write(float data
, Addr addr
, unsigned flags
, uint64_t *res
)
511 return write(*(uint32_t*)&data
, addr
, flags
, res
);
517 TimingSimpleCPU::write(int32_t data
, Addr addr
, unsigned flags
, uint64_t *res
)
519 return write((uint32_t)data
, addr
, flags
, res
);
524 TimingSimpleCPU::fetch()
526 DPRINTF(SimpleCPU
, "Fetch\n");
528 if (!curStaticInst
|| !curStaticInst
->isDelayedCommit())
529 checkForInterrupts();
533 Request
*ifetch_req
= new Request();
534 ifetch_req
->setThreadContext(cpuId
, /* thread ID */ 0);
535 Fault fault
= setupFetchRequest(ifetch_req
);
537 ifetch_pkt
= new Packet(ifetch_req
, MemCmd::ReadReq
, Packet::Broadcast
);
538 ifetch_pkt
->dataStatic(&inst
);
540 if (fault
== NoFault
) {
541 if (!icachePort
.sendTiming(ifetch_pkt
)) {
542 // Need to wait for retry
543 _status
= IcacheRetry
;
545 // Need to wait for cache to respond
546 _status
= IcacheWaitResponse
;
547 // ownership of packet transferred to memory system
553 // fetch fault: advance directly to next instruction (fault handler)
557 numCycles
+= tickToCycles(curTick
- previousTick
);
558 previousTick
= curTick
;
563 TimingSimpleCPU::advanceInst(Fault fault
)
567 if (_status
== Running
) {
568 // kick off fetch of next instruction... callback from icache
569 // response will cause that instruction to be executed,
570 // keeping the CPU running.
577 TimingSimpleCPU::completeIfetch(PacketPtr pkt
)
579 DPRINTF(SimpleCPU
, "Complete ICache Fetch\n");
581 // received a response from the icache: execute the received
583 assert(!pkt
->isError());
584 assert(_status
== IcacheWaitResponse
);
588 numCycles
+= tickToCycles(curTick
- previousTick
);
589 previousTick
= curTick
;
591 if (getState() == SimObject::Draining
) {
600 if (curStaticInst
->isMemRef() && !curStaticInst
->isDataPrefetch()) {
601 // load or store: just send to dcache
602 Fault fault
= curStaticInst
->initiateAcc(this, traceData
);
603 if (_status
!= Running
) {
604 // instruction will complete in dcache response callback
605 assert(_status
== DcacheWaitResponse
|| _status
== DcacheRetry
);
606 assert(fault
== NoFault
);
608 if (fault
== NoFault
) {
609 // Note that ARM can have NULL packets if the instruction gets
610 // squashed due to predication
611 // early fail on store conditional: complete now
612 assert(dcache_pkt
!= NULL
|| THE_ISA
== ARM_ISA
);
614 fault
= curStaticInst
->completeAcc(dcache_pkt
, this,
616 if (dcache_pkt
!= NULL
)
618 delete dcache_pkt
->req
;
623 // keep an instruction count
624 if (fault
== NoFault
)
626 } else if (traceData
) {
627 // If there was a fault, we shouldn't trace this instruction.
633 // @todo remove me after debugging with legion done
634 if (curStaticInst
&& (!curStaticInst
->isMicroop() ||
635 curStaticInst
->isFirstMicroop()))
640 // non-memory instruction: execute completely now
641 Fault fault
= curStaticInst
->execute(this, traceData
);
643 // keep an instruction count
644 if (fault
== NoFault
)
646 else if (traceData
) {
647 // If there was a fault, we shouldn't trace this instruction.
653 // @todo remove me after debugging with legion done
654 if (curStaticInst
&& (!curStaticInst
->isMicroop() ||
655 curStaticInst
->isFirstMicroop()))
665 TimingSimpleCPU::IcachePort::ITickEvent::process()
667 cpu
->completeIfetch(pkt
);
671 TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt
)
673 if (pkt
->isResponse() && !pkt
->wasNacked()) {
674 // delay processing of returned data until next CPU clock edge
675 Tick next_tick
= cpu
->nextCycle(curTick
);
677 if (next_tick
== curTick
)
678 cpu
->completeIfetch(pkt
);
680 tickEvent
.schedule(pkt
, next_tick
);
684 else if (pkt
->wasNacked()) {
685 assert(cpu
->_status
== IcacheWaitResponse
);
687 if (!sendTiming(pkt
)) {
688 cpu
->_status
= IcacheRetry
;
689 cpu
->ifetch_pkt
= pkt
;
692 //Snooping a Coherence Request, do nothing
697 TimingSimpleCPU::IcachePort::recvRetry()
699 // we shouldn't get a retry unless we have a packet that we're
700 // waiting to transmit
701 assert(cpu
->ifetch_pkt
!= NULL
);
702 assert(cpu
->_status
== IcacheRetry
);
703 PacketPtr tmp
= cpu
->ifetch_pkt
;
704 if (sendTiming(tmp
)) {
705 cpu
->_status
= IcacheWaitResponse
;
706 cpu
->ifetch_pkt
= NULL
;
711 TimingSimpleCPU::completeDataAccess(PacketPtr pkt
)
713 // received a response from the dcache: complete the load or store
715 assert(!pkt
->isError());
716 assert(_status
== DcacheWaitResponse
);
719 numCycles
+= tickToCycles(curTick
- previousTick
);
720 previousTick
= curTick
;
722 Fault fault
= curStaticInst
->completeAcc(pkt
, this, traceData
);
724 // keep an instruction count
725 if (fault
== NoFault
)
727 else if (traceData
) {
728 // If there was a fault, we shouldn't trace this instruction.
733 if (pkt
->isRead() && pkt
->isLocked()) {
734 TheISA::handleLockedRead(thread
, pkt
->req
);
742 if (getState() == SimObject::Draining
) {
754 TimingSimpleCPU::completeDrain()
756 DPRINTF(Config
, "Done draining\n");
757 changeState(SimObject::Drained
);
758 drainEvent
->process();
762 TimingSimpleCPU::DcachePort::setPeer(Port
*port
)
767 // Update the ThreadContext's memory ports (Functional/Virtual
769 cpu
->tcBase()->connectMemPorts(cpu
->tcBase());
774 TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt
)
776 if (pkt
->isResponse() && !pkt
->wasNacked()) {
777 // delay processing of returned data until next CPU clock edge
778 Tick next_tick
= cpu
->nextCycle(curTick
);
780 if (next_tick
== curTick
)
781 cpu
->completeDataAccess(pkt
);
783 tickEvent
.schedule(pkt
, next_tick
);
787 else if (pkt
->wasNacked()) {
788 assert(cpu
->_status
== DcacheWaitResponse
);
790 if (!sendTiming(pkt
)) {
791 cpu
->_status
= DcacheRetry
;
792 cpu
->dcache_pkt
= pkt
;
795 //Snooping a Coherence Request, do nothing
800 TimingSimpleCPU::DcachePort::DTickEvent::process()
802 cpu
->completeDataAccess(pkt
);
806 TimingSimpleCPU::DcachePort::recvRetry()
808 // we shouldn't get a retry unless we have a packet that we're
809 // waiting to transmit
810 assert(cpu
->dcache_pkt
!= NULL
);
811 assert(cpu
->_status
== DcacheRetry
);
812 PacketPtr tmp
= cpu
->dcache_pkt
;
813 if (sendTiming(tmp
)) {
814 cpu
->_status
= DcacheWaitResponse
;
815 // memory system takes ownership of packet
816 cpu
->dcache_pkt
= NULL
;
820 TimingSimpleCPU::IprEvent::IprEvent(Packet
*_pkt
, TimingSimpleCPU
*_cpu
, Tick t
)
821 : Event(&mainEventQueue
), pkt(_pkt
), cpu(_cpu
)
827 TimingSimpleCPU::IprEvent::process()
829 cpu
->completeDataAccess(pkt
);
833 TimingSimpleCPU::IprEvent::description() const
835 return "Timing Simple CPU Delay IPR event";
840 TimingSimpleCPU::printAddr(Addr a
)
842 dcachePort
.printAddr(a
);
846 ////////////////////////////////////////////////////////////////////////
848 // TimingSimpleCPU Simulation Object
851 TimingSimpleCPUParams::create()
853 TimingSimpleCPU::Params
*params
= new TimingSimpleCPU::Params();
855 params
->numberOfThreads
= 1;
856 params
->max_insts_any_thread
= max_insts_any_thread
;
857 params
->max_insts_all_threads
= max_insts_all_threads
;
858 params
->max_loads_any_thread
= max_loads_any_thread
;
859 params
->max_loads_all_threads
= max_loads_all_threads
;
860 params
->progress_interval
= progress_interval
;
861 params
->deferRegistration
= defer_registration
;
862 params
->clock
= clock
;
863 params
->phase
= phase
;
864 params
->functionTrace
= function_trace
;
865 params
->functionTraceStart
= function_trace_start
;
866 params
->system
= system
;
867 params
->cpu_id
= cpu_id
;
868 params
->tracer
= tracer
;
873 params
->profile
= profile
;
874 params
->do_quiesce
= do_quiesce
;
875 params
->do_checkpoint_insts
= do_checkpoint_insts
;
876 params
->do_statistics_insts
= do_statistics_insts
;
878 if (workload
.size() != 1)
879 panic("only one workload allowed");
880 params
->process
= workload
[0];
883 TimingSimpleCPU
*cpu
= new TimingSimpleCPU(params
);