2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
31 #include "arch/locked_mem.hh"
32 #include "arch/mmaped_ipr.hh"
33 #include "arch/utility.hh"
34 #include "base/bigint.hh"
35 #include "cpu/exetrace.hh"
36 #include "cpu/simple/timing.hh"
37 #include "mem/packet.hh"
38 #include "mem/packet_access.hh"
39 #include "params/TimingSimpleCPU.hh"
40 #include "sim/system.hh"
43 using namespace TheISA
;
46 TimingSimpleCPU::getPort(const std::string
&if_name
, int idx
)
48 if (if_name
== "dcache_port")
50 else if (if_name
== "icache_port")
53 panic("No Such Port\n");
57 TimingSimpleCPU::init()
61 for (int i
= 0; i
< threadContexts
.size(); ++i
) {
62 ThreadContext
*tc
= threadContexts
[i
];
64 // initialize CPU, including PC
65 TheISA::initCPU(tc
, _cpuId
);
71 TimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt
)
73 panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
78 TimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt
)
80 //No internal storage to update, jusst return
85 TimingSimpleCPU::CpuPort::recvStatusChange(Status status
)
87 if (status
== RangeChange
) {
88 if (!snoopRangeSent
) {
89 snoopRangeSent
= true;
90 sendStatusChange(Port::RangeChange
);
95 panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
100 TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt
, Tick t
)
103 cpu
->schedule(this, t
);
106 TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams
*p
)
107 : BaseSimpleCPU(p
), fetchTranslation(this), icachePort(this, p
->clock
),
108 dcachePort(this, p
->clock
), fetchEvent(this)
112 icachePort
.snoopRangeSent
= false;
113 dcachePort
.snoopRangeSent
= false;
115 ifetch_pkt
= dcache_pkt
= NULL
;
118 changeState(SimObject::Running
);
122 TimingSimpleCPU::~TimingSimpleCPU()
127 TimingSimpleCPU::serialize(ostream
&os
)
129 SimObject::State so_state
= SimObject::getState();
130 SERIALIZE_ENUM(so_state
);
131 BaseSimpleCPU::serialize(os
);
135 TimingSimpleCPU::unserialize(Checkpoint
*cp
, const string
§ion
)
137 SimObject::State so_state
;
138 UNSERIALIZE_ENUM(so_state
);
139 BaseSimpleCPU::unserialize(cp
, section
);
143 TimingSimpleCPU::drain(Event
*drain_event
)
145 // TimingSimpleCPU is ready to drain if it's not waiting for
146 // an access to complete.
147 if (_status
== Idle
|| _status
== Running
|| _status
== SwitchedOut
) {
148 changeState(SimObject::Drained
);
151 changeState(SimObject::Draining
);
152 drainEvent
= drain_event
;
158 TimingSimpleCPU::resume()
160 DPRINTF(SimpleCPU
, "Resume\n");
161 if (_status
!= SwitchedOut
&& _status
!= Idle
) {
162 assert(system
->getMemoryMode() == Enums::timing
);
164 if (fetchEvent
.scheduled())
165 deschedule(fetchEvent
);
167 schedule(fetchEvent
, nextCycle());
170 changeState(SimObject::Running
);
174 TimingSimpleCPU::switchOut()
176 assert(_status
== Running
|| _status
== Idle
);
177 _status
= SwitchedOut
;
178 numCycles
+= tickToCycles(curTick
- previousTick
);
180 // If we've been scheduled to resume but are then told to switch out,
181 // we'll need to cancel it.
182 if (fetchEvent
.scheduled())
183 deschedule(fetchEvent
);
188 TimingSimpleCPU::takeOverFrom(BaseCPU
*oldCPU
)
190 BaseCPU::takeOverFrom(oldCPU
, &icachePort
, &dcachePort
);
192 // if any of this CPU's ThreadContexts are active, mark the CPU as
193 // running and schedule its tick event.
194 for (int i
= 0; i
< threadContexts
.size(); ++i
) {
195 ThreadContext
*tc
= threadContexts
[i
];
196 if (tc
->status() == ThreadContext::Active
&& _status
!= Running
) {
202 if (_status
!= Running
) {
205 assert(threadContexts
.size() == 1);
206 previousTick
= curTick
;
211 TimingSimpleCPU::activateContext(int thread_num
, int delay
)
213 DPRINTF(SimpleCPU
, "ActivateContext %d (%d cycles)\n", thread_num
, delay
);
215 assert(thread_num
== 0);
218 assert(_status
== Idle
);
223 // kick things off by initiating the fetch of the next instruction
224 schedule(fetchEvent
, nextCycle(curTick
+ ticks(delay
)));
229 TimingSimpleCPU::suspendContext(int thread_num
)
231 DPRINTF(SimpleCPU
, "SuspendContext %d\n", thread_num
);
233 assert(thread_num
== 0);
236 assert(_status
== Running
);
238 // just change status to Idle... if status != Running,
239 // completeInst() will not initiate fetch of next instruction.
246 TimingSimpleCPU::handleReadPacket(PacketPtr pkt
)
248 RequestPtr req
= pkt
->req
;
249 if (req
->isMmapedIpr()) {
251 delay
= TheISA::handleIprRead(thread
->getTC(), pkt
);
252 new IprEvent(pkt
, this, nextCycle(curTick
+ delay
));
253 _status
= DcacheWaitResponse
;
255 } else if (!dcachePort
.sendTiming(pkt
)) {
256 _status
= DcacheRetry
;
259 _status
= DcacheWaitResponse
;
260 // memory system takes ownership of packet
263 return dcache_pkt
== NULL
;
267 TimingSimpleCPU::sendData(Fault fault
, RequestPtr req
,
268 uint8_t *data
, uint64_t *res
, bool read
)
271 if (fault
!= NoFault
) {
275 translationFault(fault
);
279 buildPacket(pkt
, req
, read
);
280 pkt
->dataDynamic
<uint8_t>(data
);
281 if (req
->getFlags().isSet(Request::NO_ACCESS
)) {
284 completeDataAccess(pkt
);
286 handleReadPacket(pkt
);
288 bool do_access
= true; // flag to suppress cache access
290 if (req
->isLocked()) {
291 do_access
= TheISA::handleLockedWrite(thread
, req
);
292 } else if (req
->isCondSwap()) {
294 req
->setExtraData(*res
);
301 _status
= DcacheWaitResponse
;
302 completeDataAccess(pkt
);
308 TimingSimpleCPU::sendSplitData(Fault fault1
, Fault fault2
,
309 RequestPtr req1
, RequestPtr req2
, RequestPtr req
,
310 uint8_t *data
, bool read
)
313 if (fault1
!= NoFault
|| fault2
!= NoFault
) {
317 if (fault1
!= NoFault
)
318 translationFault(fault1
);
319 else if (fault2
!= NoFault
)
320 translationFault(fault2
);
323 PacketPtr pkt1
, pkt2
;
324 buildSplitPacket(pkt1
, pkt2
, req1
, req2
, req
, data
, read
);
325 if (req
->getFlags().isSet(Request::NO_ACCESS
)) {
327 pkt1
->makeResponse();
328 completeDataAccess(pkt1
);
330 if (handleReadPacket(pkt1
)) {
331 SplitFragmentSenderState
* send_state
=
332 dynamic_cast<SplitFragmentSenderState
*>(pkt1
->senderState
);
333 send_state
->clearFromParent();
334 if (handleReadPacket(pkt2
)) {
335 send_state
= dynamic_cast<SplitFragmentSenderState
*>(
337 send_state
->clearFromParent();
342 if (handleWritePacket()) {
343 SplitFragmentSenderState
* send_state
=
344 dynamic_cast<SplitFragmentSenderState
*>(pkt1
->senderState
);
345 send_state
->clearFromParent();
347 if (handleWritePacket()) {
348 send_state
= dynamic_cast<SplitFragmentSenderState
*>(
350 send_state
->clearFromParent();
357 TimingSimpleCPU::translationFault(Fault fault
)
359 numCycles
+= tickToCycles(curTick
- previousTick
);
360 previousTick
= curTick
;
363 // Since there was a fault, we shouldn't trace this instruction.
370 if (getState() == SimObject::Draining
) {
379 TimingSimpleCPU::buildPacket(PacketPtr
&pkt
, RequestPtr req
, bool read
)
383 cmd
= MemCmd::ReadReq
;
385 cmd
= MemCmd::LoadLockedReq
;
387 cmd
= MemCmd::WriteReq
;
388 if (req
->isLocked()) {
389 cmd
= MemCmd::StoreCondReq
;
390 } else if (req
->isSwap()) {
391 cmd
= MemCmd::SwapReq
;
394 pkt
= new Packet(req
, cmd
, Packet::Broadcast
);
398 TimingSimpleCPU::buildSplitPacket(PacketPtr
&pkt1
, PacketPtr
&pkt2
,
399 RequestPtr req1
, RequestPtr req2
, RequestPtr req
,
400 uint8_t *data
, bool read
)
404 assert(!req1
->isMmapedIpr() && !req2
->isMmapedIpr());
406 if (req
->getFlags().isSet(Request::NO_ACCESS
)) {
407 buildPacket(pkt1
, req
, read
);
411 buildPacket(pkt1
, req1
, read
);
412 buildPacket(pkt2
, req2
, read
);
414 req
->setPhys(req1
->getPaddr(), req
->getSize(), req1
->getFlags());
415 PacketPtr pkt
= new Packet(req
, pkt1
->cmd
.responseCommand(),
418 pkt
->dataDynamic
<uint8_t>(data
);
419 pkt1
->dataStatic
<uint8_t>(data
);
420 pkt2
->dataStatic
<uint8_t>(data
+ req1
->getSize());
422 SplitMainSenderState
* main_send_state
= new SplitMainSenderState
;
423 pkt
->senderState
= main_send_state
;
424 main_send_state
->fragments
[0] = pkt1
;
425 main_send_state
->fragments
[1] = pkt2
;
426 main_send_state
->outstanding
= 2;
427 pkt1
->senderState
= new SplitFragmentSenderState(pkt
, 0);
428 pkt2
->senderState
= new SplitFragmentSenderState(pkt
, 1);
433 TimingSimpleCPU::read(Addr addr
, T
&data
, unsigned flags
)
437 const int thread_id
= 0;
438 const Addr pc
= thread
->readPC();
439 int block_size
= dcachePort
.peerBlockSize();
440 int data_size
= sizeof(T
);
442 RequestPtr req
= new Request(asid
, addr
, data_size
,
443 flags
, pc
, _cpuId
, thread_id
);
445 Addr split_addr
= roundDown(addr
+ data_size
- 1, block_size
);
446 assert(split_addr
<= addr
|| split_addr
- addr
< block_size
);
449 _status
= DTBWaitResponse
;
450 if (split_addr
> addr
) {
451 RequestPtr req1
, req2
;
452 assert(!req
->isLocked() && !req
->isSwap());
453 req
->splitOnVaddr(split_addr
, req1
, req2
);
455 typedef SplitDataTranslation::WholeTranslationState WholeState
;
456 WholeState
*state
= new WholeState(req1
, req2
, req
,
457 (uint8_t *)(new T
), true);
458 thread
->dtb
->translateTiming(req1
, tc
,
459 new SplitDataTranslation(this, 0, state
), false);
460 thread
->dtb
->translateTiming(req2
, tc
,
461 new SplitDataTranslation(this, 1, state
), false);
463 thread
->dtb
->translateTiming(req
, tc
,
464 new DataTranslation(this, (uint8_t *)(new T
), NULL
, true),
469 traceData
->setData(data
);
470 traceData
->setAddr(addr
);
473 // This will need a new way to tell if it has a dcache attached.
474 if (req
->isUncacheable())
475 recordEvent("Uncached Read");
480 #ifndef DOXYGEN_SHOULD_SKIP_THIS
484 TimingSimpleCPU::read(Addr addr
, Twin64_t
&data
, unsigned flags
);
488 TimingSimpleCPU::read(Addr addr
, Twin32_t
&data
, unsigned flags
);
492 TimingSimpleCPU::read(Addr addr
, uint64_t &data
, unsigned flags
);
496 TimingSimpleCPU::read(Addr addr
, uint32_t &data
, unsigned flags
);
500 TimingSimpleCPU::read(Addr addr
, uint16_t &data
, unsigned flags
);
504 TimingSimpleCPU::read(Addr addr
, uint8_t &data
, unsigned flags
);
506 #endif //DOXYGEN_SHOULD_SKIP_THIS
510 TimingSimpleCPU::read(Addr addr
, double &data
, unsigned flags
)
512 return read(addr
, *(uint64_t*)&data
, flags
);
517 TimingSimpleCPU::read(Addr addr
, float &data
, unsigned flags
)
519 return read(addr
, *(uint32_t*)&data
, flags
);
525 TimingSimpleCPU::read(Addr addr
, int32_t &data
, unsigned flags
)
527 return read(addr
, (uint32_t&)data
, flags
);
531 TimingSimpleCPU::handleWritePacket()
533 RequestPtr req
= dcache_pkt
->req
;
534 if (req
->isMmapedIpr()) {
536 delay
= TheISA::handleIprWrite(thread
->getTC(), dcache_pkt
);
537 new IprEvent(dcache_pkt
, this, nextCycle(curTick
+ delay
));
538 _status
= DcacheWaitResponse
;
540 } else if (!dcachePort
.sendTiming(dcache_pkt
)) {
541 _status
= DcacheRetry
;
543 _status
= DcacheWaitResponse
;
544 // memory system takes ownership of packet
547 return dcache_pkt
== NULL
;
552 TimingSimpleCPU::write(T data
, Addr addr
, unsigned flags
, uint64_t *res
)
555 const int thread_id
= 0;
556 const Addr pc
= thread
->readPC();
557 int block_size
= dcachePort
.peerBlockSize();
558 int data_size
= sizeof(T
);
560 RequestPtr req
= new Request(asid
, addr
, data_size
,
561 flags
, pc
, _cpuId
, thread_id
);
563 Addr split_addr
= roundDown(addr
+ data_size
- 1, block_size
);
564 assert(split_addr
<= addr
|| split_addr
- addr
< block_size
);
567 *dataP
= TheISA::htog(data
);
568 _status
= DTBWaitResponse
;
569 if (split_addr
> addr
) {
570 RequestPtr req1
, req2
;
571 assert(!req
->isLocked() && !req
->isSwap());
572 req
->splitOnVaddr(split_addr
, req1
, req2
);
574 typedef SplitDataTranslation::WholeTranslationState WholeState
;
575 WholeState
*state
= new WholeState(req1
, req2
, req
,
576 (uint8_t *)dataP
, false);
577 thread
->dtb
->translateTiming(req1
, tc
,
578 new SplitDataTranslation(this, 0, state
), true);
579 thread
->dtb
->translateTiming(req2
, tc
,
580 new SplitDataTranslation(this, 1, state
), true);
582 thread
->dtb
->translateTiming(req
, tc
,
583 new DataTranslation(this, (uint8_t *)dataP
, res
, false),
588 traceData
->setAddr(req
->getVaddr());
589 traceData
->setData(data
);
592 // This will need a new way to tell if it's hooked up to a cache or not.
593 if (req
->isUncacheable())
594 recordEvent("Uncached Write");
596 // If the write needs to have a fault on the access, consider calling
597 // changeStatus() and changing it to "bad addr write" or something.
602 #ifndef DOXYGEN_SHOULD_SKIP_THIS
605 TimingSimpleCPU::write(Twin32_t data
, Addr addr
,
606 unsigned flags
, uint64_t *res
);
610 TimingSimpleCPU::write(Twin64_t data
, Addr addr
,
611 unsigned flags
, uint64_t *res
);
615 TimingSimpleCPU::write(uint64_t data
, Addr addr
,
616 unsigned flags
, uint64_t *res
);
620 TimingSimpleCPU::write(uint32_t data
, Addr addr
,
621 unsigned flags
, uint64_t *res
);
625 TimingSimpleCPU::write(uint16_t data
, Addr addr
,
626 unsigned flags
, uint64_t *res
);
630 TimingSimpleCPU::write(uint8_t data
, Addr addr
,
631 unsigned flags
, uint64_t *res
);
633 #endif //DOXYGEN_SHOULD_SKIP_THIS
637 TimingSimpleCPU::write(double data
, Addr addr
, unsigned flags
, uint64_t *res
)
639 return write(*(uint64_t*)&data
, addr
, flags
, res
);
644 TimingSimpleCPU::write(float data
, Addr addr
, unsigned flags
, uint64_t *res
)
646 return write(*(uint32_t*)&data
, addr
, flags
, res
);
652 TimingSimpleCPU::write(int32_t data
, Addr addr
, unsigned flags
, uint64_t *res
)
654 return write((uint32_t)data
, addr
, flags
, res
);
659 TimingSimpleCPU::fetch()
661 DPRINTF(SimpleCPU
, "Fetch\n");
663 if (!curStaticInst
|| !curStaticInst
->isDelayedCommit())
664 checkForInterrupts();
668 bool fromRom
= isRomMicroPC(thread
->readMicroPC());
670 if (!fromRom
&& !curMacroStaticInst
) {
671 Request
*ifetch_req
= new Request();
672 ifetch_req
->setThreadContext(_cpuId
, /* thread ID */ 0);
673 setupFetchRequest(ifetch_req
);
674 thread
->itb
->translateTiming(ifetch_req
, tc
,
675 &fetchTranslation
, false, true);
677 _status
= IcacheWaitResponse
;
678 completeIfetch(NULL
);
680 numCycles
+= tickToCycles(curTick
- previousTick
);
681 previousTick
= curTick
;
687 TimingSimpleCPU::sendFetch(Fault fault
, RequestPtr req
, ThreadContext
*tc
)
689 if (fault
== NoFault
) {
690 ifetch_pkt
= new Packet(req
, MemCmd::ReadReq
, Packet::Broadcast
);
691 ifetch_pkt
->dataStatic(&inst
);
693 if (!icachePort
.sendTiming(ifetch_pkt
)) {
694 // Need to wait for retry
695 _status
= IcacheRetry
;
697 // Need to wait for cache to respond
698 _status
= IcacheWaitResponse
;
699 // ownership of packet transferred to memory system
704 // fetch fault: advance directly to next instruction (fault handler)
708 numCycles
+= tickToCycles(curTick
- previousTick
);
709 previousTick
= curTick
;
714 TimingSimpleCPU::advanceInst(Fault fault
)
716 if (fault
!= NoFault
|| !stayAtPC
)
719 if (_status
== Running
) {
720 // kick off fetch of next instruction... callback from icache
721 // response will cause that instruction to be executed,
722 // keeping the CPU running.
729 TimingSimpleCPU::completeIfetch(PacketPtr pkt
)
731 DPRINTF(SimpleCPU
, "Complete ICache Fetch\n");
733 // received a response from the icache: execute the received
736 assert(!pkt
|| !pkt
->isError());
737 assert(_status
== IcacheWaitResponse
);
741 numCycles
+= tickToCycles(curTick
- previousTick
);
742 previousTick
= curTick
;
744 if (getState() == SimObject::Draining
) {
756 curStaticInst
->isMemRef() && !curStaticInst
->isDataPrefetch()) {
757 // load or store: just send to dcache
758 Fault fault
= curStaticInst
->initiateAcc(this, traceData
);
759 if (_status
!= Running
) {
760 // instruction will complete in dcache response callback
761 assert(_status
== DcacheWaitResponse
||
762 _status
== DcacheRetry
|| DTBWaitResponse
);
763 assert(fault
== NoFault
);
765 if (fault
!= NoFault
&& traceData
) {
766 // If there was a fault, we shouldn't trace this instruction.
772 // @todo remove me after debugging with legion done
773 if (curStaticInst
&& (!curStaticInst
->isMicroop() ||
774 curStaticInst
->isFirstMicroop()))
778 } else if (curStaticInst
) {
779 // non-memory instruction: execute completely now
780 Fault fault
= curStaticInst
->execute(this, traceData
);
782 // keep an instruction count
783 if (fault
== NoFault
)
785 else if (traceData
) {
786 // If there was a fault, we shouldn't trace this instruction.
792 // @todo remove me after debugging with legion done
793 if (curStaticInst
&& (!curStaticInst
->isMicroop() ||
794 curStaticInst
->isFirstMicroop()))
798 advanceInst(NoFault
);
808 TimingSimpleCPU::IcachePort::ITickEvent::process()
810 cpu
->completeIfetch(pkt
);
814 TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt
)
816 if (pkt
->isResponse() && !pkt
->wasNacked()) {
817 // delay processing of returned data until next CPU clock edge
818 Tick next_tick
= cpu
->nextCycle(curTick
);
820 if (next_tick
== curTick
)
821 cpu
->completeIfetch(pkt
);
823 tickEvent
.schedule(pkt
, next_tick
);
827 else if (pkt
->wasNacked()) {
828 assert(cpu
->_status
== IcacheWaitResponse
);
830 if (!sendTiming(pkt
)) {
831 cpu
->_status
= IcacheRetry
;
832 cpu
->ifetch_pkt
= pkt
;
835 //Snooping a Coherence Request, do nothing
840 TimingSimpleCPU::IcachePort::recvRetry()
842 // we shouldn't get a retry unless we have a packet that we're
843 // waiting to transmit
844 assert(cpu
->ifetch_pkt
!= NULL
);
845 assert(cpu
->_status
== IcacheRetry
);
846 PacketPtr tmp
= cpu
->ifetch_pkt
;
847 if (sendTiming(tmp
)) {
848 cpu
->_status
= IcacheWaitResponse
;
849 cpu
->ifetch_pkt
= NULL
;
854 TimingSimpleCPU::completeDataAccess(PacketPtr pkt
)
856 // received a response from the dcache: complete the load or store
858 assert(!pkt
->isError());
860 numCycles
+= tickToCycles(curTick
- previousTick
);
861 previousTick
= curTick
;
863 if (pkt
->senderState
) {
864 SplitFragmentSenderState
* send_state
=
865 dynamic_cast<SplitFragmentSenderState
*>(pkt
->senderState
);
869 PacketPtr big_pkt
= send_state
->bigPkt
;
872 SplitMainSenderState
* main_send_state
=
873 dynamic_cast<SplitMainSenderState
*>(big_pkt
->senderState
);
874 assert(main_send_state
);
875 // Record the fact that this packet is no longer outstanding.
876 assert(main_send_state
->outstanding
!= 0);
877 main_send_state
->outstanding
--;
879 if (main_send_state
->outstanding
) {
882 delete main_send_state
;
883 big_pkt
->senderState
= NULL
;
888 assert(_status
== DcacheWaitResponse
|| _status
== DTBWaitResponse
);
891 Fault fault
= curStaticInst
->completeAcc(pkt
, this, traceData
);
893 // keep an instruction count
894 if (fault
== NoFault
)
896 else if (traceData
) {
897 // If there was a fault, we shouldn't trace this instruction.
902 // the locked flag may be cleared on the response packet, so check
903 // pkt->req and not pkt to see if it was a load-locked
904 if (pkt
->isRead() && pkt
->req
->isLocked()) {
905 TheISA::handleLockedRead(thread
, pkt
->req
);
913 if (getState() == SimObject::Draining
) {
925 TimingSimpleCPU::completeDrain()
927 DPRINTF(Config
, "Done draining\n");
928 changeState(SimObject::Drained
);
929 drainEvent
->process();
933 TimingSimpleCPU::DcachePort::setPeer(Port
*port
)
938 // Update the ThreadContext's memory ports (Functional/Virtual
940 cpu
->tcBase()->connectMemPorts(cpu
->tcBase());
945 TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt
)
947 if (pkt
->isResponse() && !pkt
->wasNacked()) {
948 // delay processing of returned data until next CPU clock edge
949 Tick next_tick
= cpu
->nextCycle(curTick
);
951 if (next_tick
== curTick
) {
952 cpu
->completeDataAccess(pkt
);
954 tickEvent
.schedule(pkt
, next_tick
);
959 else if (pkt
->wasNacked()) {
960 assert(cpu
->_status
== DcacheWaitResponse
);
962 if (!sendTiming(pkt
)) {
963 cpu
->_status
= DcacheRetry
;
964 cpu
->dcache_pkt
= pkt
;
967 //Snooping a Coherence Request, do nothing
972 TimingSimpleCPU::DcachePort::DTickEvent::process()
974 cpu
->completeDataAccess(pkt
);
978 TimingSimpleCPU::DcachePort::recvRetry()
980 // we shouldn't get a retry unless we have a packet that we're
981 // waiting to transmit
982 assert(cpu
->dcache_pkt
!= NULL
);
983 assert(cpu
->_status
== DcacheRetry
);
984 PacketPtr tmp
= cpu
->dcache_pkt
;
985 if (tmp
->senderState
) {
986 // This is a packet from a split access.
987 SplitFragmentSenderState
* send_state
=
988 dynamic_cast<SplitFragmentSenderState
*>(tmp
->senderState
);
990 PacketPtr big_pkt
= send_state
->bigPkt
;
992 SplitMainSenderState
* main_send_state
=
993 dynamic_cast<SplitMainSenderState
*>(big_pkt
->senderState
);
994 assert(main_send_state
);
996 if (sendTiming(tmp
)) {
997 // If we were able to send without retrying, record that fact
998 // and try sending the other fragment.
999 send_state
->clearFromParent();
1000 int other_index
= main_send_state
->getPendingFragment();
1001 if (other_index
> 0) {
1002 tmp
= main_send_state
->fragments
[other_index
];
1003 cpu
->dcache_pkt
= tmp
;
1004 if ((big_pkt
->isRead() && cpu
->handleReadPacket(tmp
)) ||
1005 (big_pkt
->isWrite() && cpu
->handleWritePacket())) {
1006 main_send_state
->fragments
[other_index
] = NULL
;
1009 cpu
->_status
= DcacheWaitResponse
;
1010 // memory system takes ownership of packet
1011 cpu
->dcache_pkt
= NULL
;
1014 } else if (sendTiming(tmp
)) {
1015 cpu
->_status
= DcacheWaitResponse
;
1016 // memory system takes ownership of packet
1017 cpu
->dcache_pkt
= NULL
;
1021 TimingSimpleCPU::IprEvent::IprEvent(Packet
*_pkt
, TimingSimpleCPU
*_cpu
,
1023 : pkt(_pkt
), cpu(_cpu
)
1025 cpu
->schedule(this, t
);
1029 TimingSimpleCPU::IprEvent::process()
1031 cpu
->completeDataAccess(pkt
);
1035 TimingSimpleCPU::IprEvent::description() const
1037 return "Timing Simple CPU Delay IPR event";
1042 TimingSimpleCPU::printAddr(Addr a
)
1044 dcachePort
.printAddr(a
);
1048 ////////////////////////////////////////////////////////////////////////
1050 // TimingSimpleCPU Simulation Object
1053 TimingSimpleCPUParams::create()
1057 if (workload
.size() != 1)
1058 panic("only one workload allowed");
1060 return new TimingSimpleCPU(this);