2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
31 #include "arch/locked_mem.hh"
32 #include "arch/mmaped_ipr.hh"
33 #include "arch/utility.hh"
34 #include "base/bigint.hh"
35 #include "cpu/exetrace.hh"
36 #include "cpu/simple/timing.hh"
37 #include "mem/packet.hh"
38 #include "mem/packet_access.hh"
39 #include "params/TimingSimpleCPU.hh"
40 #include "sim/system.hh"
43 using namespace TheISA
;
46 TimingSimpleCPU::getPort(const std::string
&if_name
, int idx
)
48 if (if_name
== "dcache_port")
50 else if (if_name
== "icache_port")
53 panic("No Such Port\n");
57 TimingSimpleCPU::init()
61 for (int i
= 0; i
< threadContexts
.size(); ++i
) {
62 ThreadContext
*tc
= threadContexts
[i
];
64 // initialize CPU, including PC
65 TheISA::initCPU(tc
, _cpuId
);
71 TimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt
)
73 panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
78 TimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt
)
80 //No internal storage to update, jusst return
85 TimingSimpleCPU::CpuPort::recvStatusChange(Status status
)
87 if (status
== RangeChange
) {
88 if (!snoopRangeSent
) {
89 snoopRangeSent
= true;
90 sendStatusChange(Port::RangeChange
);
95 panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
100 TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt
, Tick t
)
103 cpu
->schedule(this, t
);
106 TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams
*p
)
107 : BaseSimpleCPU(p
), icachePort(this, p
->clock
), dcachePort(this, p
->clock
), fetchEvent(this)
111 icachePort
.snoopRangeSent
= false;
112 dcachePort
.snoopRangeSent
= false;
114 ifetch_pkt
= dcache_pkt
= NULL
;
117 changeState(SimObject::Running
);
121 TimingSimpleCPU::~TimingSimpleCPU()
126 TimingSimpleCPU::serialize(ostream
&os
)
128 SimObject::State so_state
= SimObject::getState();
129 SERIALIZE_ENUM(so_state
);
130 BaseSimpleCPU::serialize(os
);
134 TimingSimpleCPU::unserialize(Checkpoint
*cp
, const string
§ion
)
136 SimObject::State so_state
;
137 UNSERIALIZE_ENUM(so_state
);
138 BaseSimpleCPU::unserialize(cp
, section
);
142 TimingSimpleCPU::drain(Event
*drain_event
)
144 // TimingSimpleCPU is ready to drain if it's not waiting for
145 // an access to complete.
146 if (_status
== Idle
|| _status
== Running
|| _status
== SwitchedOut
) {
147 changeState(SimObject::Drained
);
150 changeState(SimObject::Draining
);
151 drainEvent
= drain_event
;
157 TimingSimpleCPU::resume()
159 DPRINTF(SimpleCPU
, "Resume\n");
160 if (_status
!= SwitchedOut
&& _status
!= Idle
) {
161 assert(system
->getMemoryMode() == Enums::timing
);
163 if (fetchEvent
.scheduled())
164 deschedule(fetchEvent
);
166 schedule(fetchEvent
, nextCycle());
169 changeState(SimObject::Running
);
173 TimingSimpleCPU::switchOut()
175 assert(_status
== Running
|| _status
== Idle
);
176 _status
= SwitchedOut
;
177 numCycles
+= tickToCycles(curTick
- previousTick
);
179 // If we've been scheduled to resume but are then told to switch out,
180 // we'll need to cancel it.
181 if (fetchEvent
.scheduled())
182 deschedule(fetchEvent
);
187 TimingSimpleCPU::takeOverFrom(BaseCPU
*oldCPU
)
189 BaseCPU::takeOverFrom(oldCPU
, &icachePort
, &dcachePort
);
191 // if any of this CPU's ThreadContexts are active, mark the CPU as
192 // running and schedule its tick event.
193 for (int i
= 0; i
< threadContexts
.size(); ++i
) {
194 ThreadContext
*tc
= threadContexts
[i
];
195 if (tc
->status() == ThreadContext::Active
&& _status
!= Running
) {
201 if (_status
!= Running
) {
204 assert(threadContexts
.size() == 1);
205 previousTick
= curTick
;
210 TimingSimpleCPU::activateContext(int thread_num
, int delay
)
212 DPRINTF(SimpleCPU
, "ActivateContext %d (%d cycles)\n", thread_num
, delay
);
214 assert(thread_num
== 0);
217 assert(_status
== Idle
);
222 // kick things off by initiating the fetch of the next instruction
223 schedule(fetchEvent
, nextCycle(curTick
+ ticks(delay
)));
228 TimingSimpleCPU::suspendContext(int thread_num
)
230 DPRINTF(SimpleCPU
, "SuspendContext %d\n", thread_num
);
232 assert(thread_num
== 0);
235 assert(_status
== Running
);
237 // just change status to Idle... if status != Running,
238 // completeInst() will not initiate fetch of next instruction.
245 TimingSimpleCPU::handleReadPacket(PacketPtr pkt
)
247 RequestPtr req
= pkt
->req
;
248 if (req
->isMmapedIpr()) {
250 delay
= TheISA::handleIprRead(thread
->getTC(), pkt
);
251 new IprEvent(pkt
, this, nextCycle(curTick
+ delay
));
252 _status
= DcacheWaitResponse
;
254 } else if (!dcachePort
.sendTiming(pkt
)) {
255 _status
= DcacheRetry
;
258 _status
= DcacheWaitResponse
;
259 // memory system takes ownership of packet
262 return dcache_pkt
== NULL
;
267 TimingSimpleCPU::read(Addr addr
, T
&data
, unsigned flags
)
271 const int thread_id
= 0;
272 const Addr pc
= thread
->readPC();
277 int block_size
= dcachePort
.peerBlockSize();
278 int data_size
= sizeof(T
);
280 Addr second_addr
= roundDown(addr
+ data_size
- 1, block_size
);
282 if (second_addr
> addr
) {
283 Addr first_size
= second_addr
- addr
;
284 Addr second_size
= data_size
- first_size
;
285 // Make sure we'll only need two accesses.
286 assert(roundDown(second_addr
+ second_size
- 1, block_size
) ==
290 * Do the translations. If something isn't going to work, find out
291 * before we waste time setting up anything else.
293 req
= new Request(asid
, addr
, first_size
,
294 flags
, pc
, _cpuId
, thread_id
);
295 fault
= thread
->translateDataReadReq(req
);
296 if (fault
!= NoFault
) {
300 Request
*second_req
=
301 new Request(asid
, second_addr
, second_size
,
302 flags
, pc
, _cpuId
, thread_id
);
303 fault
= thread
->translateDataReadReq(second_req
);
304 if (fault
!= NoFault
) {
310 T
* data_ptr
= new T
;
313 * This is the big packet that will hold the data we've gotten so far,
314 * if any, and also act as the response we actually give to the
318 new Request(asid
, addr
, data_size
, flags
, pc
, _cpuId
, thread_id
);
319 orig_req
->setPhys(req
->getPaddr(), data_size
, flags
);
321 new Packet(orig_req
, MemCmd::ReadResp
, Packet::Broadcast
);
322 big_pkt
->dataDynamic
<T
>(data_ptr
);
323 SplitMainSenderState
* main_send_state
= new SplitMainSenderState
;
324 big_pkt
->senderState
= main_send_state
;
325 main_send_state
->outstanding
= 2;
327 // This is the packet we'll process now.
328 pkt
= new Packet(req
, MemCmd::ReadReq
, Packet::Broadcast
);
329 pkt
->dataStatic
<uint8_t>((uint8_t *)data_ptr
);
330 pkt
->senderState
= new SplitFragmentSenderState(big_pkt
, 0);
332 // This is the second half of the access we'll deal with later.
333 PacketPtr second_pkt
=
334 new Packet(second_req
, MemCmd::ReadReq
, Packet::Broadcast
);
335 second_pkt
->dataStatic
<uint8_t>((uint8_t *)data_ptr
+ first_size
);
336 second_pkt
->senderState
= new SplitFragmentSenderState(big_pkt
, 1);
337 if (!handleReadPacket(pkt
)) {
338 main_send_state
->fragments
[1] = second_pkt
;
340 handleReadPacket(second_pkt
);
343 req
= new Request(asid
, addr
, data_size
,
344 flags
, pc
, _cpuId
, thread_id
);
346 // translate to physical address
347 Fault fault
= thread
->translateDataReadReq(req
);
349 if (fault
!= NoFault
) {
354 pkt
= new Packet(req
,
356 MemCmd::LoadLockedReq
: MemCmd::ReadReq
),
358 pkt
->dataDynamic
<T
>(new T
);
360 handleReadPacket(pkt
);
364 traceData
->setData(data
);
365 traceData
->setAddr(addr
);
368 // This will need a new way to tell if it has a dcache attached.
369 if (req
->isUncacheable())
370 recordEvent("Uncached Read");
376 TimingSimpleCPU::translateDataReadAddr(Addr vaddr
, Addr
&paddr
,
377 int size
, unsigned flags
)
380 new Request(0, vaddr
, size
, flags
, thread
->readPC(), _cpuId
, 0);
383 traceData
->setAddr(vaddr
);
386 Fault fault
= thread
->translateDataWriteReq(req
);
388 if (fault
== NoFault
)
389 paddr
= req
->getPaddr();
395 #ifndef DOXYGEN_SHOULD_SKIP_THIS
399 TimingSimpleCPU::read(Addr addr
, Twin64_t
&data
, unsigned flags
);
403 TimingSimpleCPU::read(Addr addr
, Twin32_t
&data
, unsigned flags
);
407 TimingSimpleCPU::read(Addr addr
, uint64_t &data
, unsigned flags
);
411 TimingSimpleCPU::read(Addr addr
, uint32_t &data
, unsigned flags
);
415 TimingSimpleCPU::read(Addr addr
, uint16_t &data
, unsigned flags
);
419 TimingSimpleCPU::read(Addr addr
, uint8_t &data
, unsigned flags
);
421 #endif //DOXYGEN_SHOULD_SKIP_THIS
425 TimingSimpleCPU::read(Addr addr
, double &data
, unsigned flags
)
427 return read(addr
, *(uint64_t*)&data
, flags
);
432 TimingSimpleCPU::read(Addr addr
, float &data
, unsigned flags
)
434 return read(addr
, *(uint32_t*)&data
, flags
);
440 TimingSimpleCPU::read(Addr addr
, int32_t &data
, unsigned flags
)
442 return read(addr
, (uint32_t&)data
, flags
);
446 TimingSimpleCPU::handleWritePacket()
448 RequestPtr req
= dcache_pkt
->req
;
449 if (req
->isMmapedIpr()) {
451 delay
= TheISA::handleIprWrite(thread
->getTC(), dcache_pkt
);
452 new IprEvent(dcache_pkt
, this, nextCycle(curTick
+ delay
));
453 _status
= DcacheWaitResponse
;
455 } else if (!dcachePort
.sendTiming(dcache_pkt
)) {
456 _status
= DcacheRetry
;
458 _status
= DcacheWaitResponse
;
459 // memory system takes ownership of packet
462 return dcache_pkt
== NULL
;
467 TimingSimpleCPU::write(T data
, Addr addr
, unsigned flags
, uint64_t *res
)
470 const int thread_id
= 0;
471 bool do_access
= true; // flag to suppress cache access
472 const Addr pc
= thread
->readPC();
476 int block_size
= dcachePort
.peerBlockSize();
477 int data_size
= sizeof(T
);
479 Addr second_addr
= roundDown(addr
+ data_size
- 1, block_size
);
481 if (second_addr
> addr
) {
483 Addr first_size
= second_addr
- addr
;
484 Addr second_size
= data_size
- first_size
;
485 // Make sure we'll only need two accesses.
486 assert(roundDown(second_addr
+ second_size
- 1, block_size
) ==
489 req
= new Request(asid
, addr
, first_size
,
490 flags
, pc
, _cpuId
, thread_id
);
491 fault
= thread
->translateDataWriteReq(req
);
492 if (fault
!= NoFault
) {
496 RequestPtr second_req
= new Request(asid
, second_addr
, second_size
,
497 flags
, pc
, _cpuId
, thread_id
);
498 fault
= thread
->translateDataWriteReq(second_req
);
499 if (fault
!= NoFault
) {
505 if (req
->isLocked() || req
->isSwap() ||
506 second_req
->isLocked() || second_req
->isSwap()) {
507 panic("LL/SCs and swaps can't be split.");
510 T
* data_ptr
= new T
;
513 * This is the big packet that will hold the data we've gotten so far,
514 * if any, and also act as the response we actually give to the
517 RequestPtr orig_req
=
518 new Request(asid
, addr
, data_size
, flags
, pc
, _cpuId
, thread_id
);
519 orig_req
->setPhys(req
->getPaddr(), data_size
, flags
);
521 new Packet(orig_req
, MemCmd::WriteResp
, Packet::Broadcast
);
522 big_pkt
->dataDynamic
<T
>(data_ptr
);
524 SplitMainSenderState
* main_send_state
= new SplitMainSenderState
;
525 big_pkt
->senderState
= main_send_state
;
526 main_send_state
->outstanding
= 2;
528 assert(dcache_pkt
== NULL
);
529 // This is the packet we'll process now.
530 dcache_pkt
= new Packet(req
, MemCmd::WriteReq
, Packet::Broadcast
);
531 dcache_pkt
->dataStatic
<uint8_t>((uint8_t *)data_ptr
);
532 dcache_pkt
->senderState
= new SplitFragmentSenderState(big_pkt
, 0);
534 // This is the second half of the access we'll deal with later.
535 PacketPtr second_pkt
=
536 new Packet(second_req
, MemCmd::WriteReq
, Packet::Broadcast
);
537 second_pkt
->dataStatic
<uint8_t>((uint8_t *)data_ptr
+ first_size
);
538 second_pkt
->senderState
= new SplitFragmentSenderState(big_pkt
, 1);
539 if (!handleWritePacket()) {
540 main_send_state
->fragments
[1] = second_pkt
;
542 dcache_pkt
= second_pkt
;
546 req
= new Request(asid
, addr
, data_size
, flags
, pc
, _cpuId
, thread_id
);
548 // translate to physical address
549 Fault fault
= thread
->translateDataWriteReq(req
);
550 if (fault
!= NoFault
) {
555 MemCmd cmd
= MemCmd::WriteReq
; // default
557 if (req
->isLocked()) {
558 cmd
= MemCmd::StoreCondReq
;
559 do_access
= TheISA::handleLockedWrite(thread
, req
);
560 } else if (req
->isSwap()) {
561 cmd
= MemCmd::SwapReq
;
562 if (req
->isCondSwap()) {
564 req
->setExtraData(*res
);
568 // Note: need to allocate dcache_pkt even if do_access is
569 // false, as it's used unconditionally to call completeAcc().
570 assert(dcache_pkt
== NULL
);
571 dcache_pkt
= new Packet(req
, cmd
, Packet::Broadcast
);
572 dcache_pkt
->allocate();
573 if (req
->isMmapedIpr())
574 dcache_pkt
->set(htog(data
));
576 dcache_pkt
->set(data
);
583 traceData
->setAddr(req
->getVaddr());
584 traceData
->setData(data
);
587 // This will need a new way to tell if it's hooked up to a cache or not.
588 if (req
->isUncacheable())
589 recordEvent("Uncached Write");
591 // If the write needs to have a fault on the access, consider calling
592 // changeStatus() and changing it to "bad addr write" or something.
597 TimingSimpleCPU::translateDataWriteAddr(Addr vaddr
, Addr
&paddr
,
598 int size
, unsigned flags
)
601 new Request(0, vaddr
, size
, flags
, thread
->readPC(), _cpuId
, 0);
604 traceData
->setAddr(vaddr
);
607 Fault fault
= thread
->translateDataWriteReq(req
);
609 if (fault
== NoFault
)
610 paddr
= req
->getPaddr();
617 #ifndef DOXYGEN_SHOULD_SKIP_THIS
620 TimingSimpleCPU::write(Twin32_t data
, Addr addr
,
621 unsigned flags
, uint64_t *res
);
625 TimingSimpleCPU::write(Twin64_t data
, Addr addr
,
626 unsigned flags
, uint64_t *res
);
630 TimingSimpleCPU::write(uint64_t data
, Addr addr
,
631 unsigned flags
, uint64_t *res
);
635 TimingSimpleCPU::write(uint32_t data
, Addr addr
,
636 unsigned flags
, uint64_t *res
);
640 TimingSimpleCPU::write(uint16_t data
, Addr addr
,
641 unsigned flags
, uint64_t *res
);
645 TimingSimpleCPU::write(uint8_t data
, Addr addr
,
646 unsigned flags
, uint64_t *res
);
648 #endif //DOXYGEN_SHOULD_SKIP_THIS
652 TimingSimpleCPU::write(double data
, Addr addr
, unsigned flags
, uint64_t *res
)
654 return write(*(uint64_t*)&data
, addr
, flags
, res
);
659 TimingSimpleCPU::write(float data
, Addr addr
, unsigned flags
, uint64_t *res
)
661 return write(*(uint32_t*)&data
, addr
, flags
, res
);
667 TimingSimpleCPU::write(int32_t data
, Addr addr
, unsigned flags
, uint64_t *res
)
669 return write((uint32_t)data
, addr
, flags
, res
);
674 TimingSimpleCPU::fetch()
676 DPRINTF(SimpleCPU
, "Fetch\n");
678 if (!curStaticInst
|| !curStaticInst
->isDelayedCommit())
679 checkForInterrupts();
683 bool fromRom
= isRomMicroPC(thread
->readMicroPC());
686 Request
*ifetch_req
= new Request();
687 ifetch_req
->setThreadContext(_cpuId
, /* thread ID */ 0);
688 Fault fault
= setupFetchRequest(ifetch_req
);
690 ifetch_pkt
= new Packet(ifetch_req
, MemCmd::ReadReq
, Packet::Broadcast
);
691 ifetch_pkt
->dataStatic(&inst
);
693 if (fault
== NoFault
) {
694 if (!icachePort
.sendTiming(ifetch_pkt
)) {
695 // Need to wait for retry
696 _status
= IcacheRetry
;
698 // Need to wait for cache to respond
699 _status
= IcacheWaitResponse
;
700 // ownership of packet transferred to memory system
706 // fetch fault: advance directly to next instruction (fault handler)
710 _status
= IcacheWaitResponse
;
711 completeIfetch(NULL
);
714 numCycles
+= tickToCycles(curTick
- previousTick
);
715 previousTick
= curTick
;
720 TimingSimpleCPU::advanceInst(Fault fault
)
722 if (fault
!= NoFault
|| !stayAtPC
)
725 if (_status
== Running
) {
726 // kick off fetch of next instruction... callback from icache
727 // response will cause that instruction to be executed,
728 // keeping the CPU running.
735 TimingSimpleCPU::completeIfetch(PacketPtr pkt
)
737 DPRINTF(SimpleCPU
, "Complete ICache Fetch\n");
739 // received a response from the icache: execute the received
742 assert(!pkt
|| !pkt
->isError());
743 assert(_status
== IcacheWaitResponse
);
747 numCycles
+= tickToCycles(curTick
- previousTick
);
748 previousTick
= curTick
;
750 if (getState() == SimObject::Draining
) {
762 curStaticInst
->isMemRef() && !curStaticInst
->isDataPrefetch()) {
763 // load or store: just send to dcache
764 Fault fault
= curStaticInst
->initiateAcc(this, traceData
);
765 if (_status
!= Running
) {
766 // instruction will complete in dcache response callback
767 assert(_status
== DcacheWaitResponse
|| _status
== DcacheRetry
);
768 assert(fault
== NoFault
);
770 if (fault
== NoFault
) {
771 // Note that ARM can have NULL packets if the instruction gets
772 // squashed due to predication
773 // early fail on store conditional: complete now
774 assert(dcache_pkt
!= NULL
|| THE_ISA
== ARM_ISA
);
776 fault
= curStaticInst
->completeAcc(dcache_pkt
, this,
778 if (dcache_pkt
!= NULL
)
780 delete dcache_pkt
->req
;
785 // keep an instruction count
786 if (fault
== NoFault
)
788 } else if (traceData
) {
789 // If there was a fault, we shouldn't trace this instruction.
795 // @todo remove me after debugging with legion done
796 if (curStaticInst
&& (!curStaticInst
->isMicroop() ||
797 curStaticInst
->isFirstMicroop()))
801 } else if (curStaticInst
) {
802 // non-memory instruction: execute completely now
803 Fault fault
= curStaticInst
->execute(this, traceData
);
805 // keep an instruction count
806 if (fault
== NoFault
)
808 else if (traceData
) {
809 // If there was a fault, we shouldn't trace this instruction.
815 // @todo remove me after debugging with legion done
816 if (curStaticInst
&& (!curStaticInst
->isMicroop() ||
817 curStaticInst
->isFirstMicroop()))
821 advanceInst(NoFault
);
831 TimingSimpleCPU::IcachePort::ITickEvent::process()
833 cpu
->completeIfetch(pkt
);
837 TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt
)
839 if (pkt
->isResponse() && !pkt
->wasNacked()) {
840 // delay processing of returned data until next CPU clock edge
841 Tick next_tick
= cpu
->nextCycle(curTick
);
843 if (next_tick
== curTick
)
844 cpu
->completeIfetch(pkt
);
846 tickEvent
.schedule(pkt
, next_tick
);
850 else if (pkt
->wasNacked()) {
851 assert(cpu
->_status
== IcacheWaitResponse
);
853 if (!sendTiming(pkt
)) {
854 cpu
->_status
= IcacheRetry
;
855 cpu
->ifetch_pkt
= pkt
;
858 //Snooping a Coherence Request, do nothing
863 TimingSimpleCPU::IcachePort::recvRetry()
865 // we shouldn't get a retry unless we have a packet that we're
866 // waiting to transmit
867 assert(cpu
->ifetch_pkt
!= NULL
);
868 assert(cpu
->_status
== IcacheRetry
);
869 PacketPtr tmp
= cpu
->ifetch_pkt
;
870 if (sendTiming(tmp
)) {
871 cpu
->_status
= IcacheWaitResponse
;
872 cpu
->ifetch_pkt
= NULL
;
877 TimingSimpleCPU::completeDataAccess(PacketPtr pkt
)
879 // received a response from the dcache: complete the load or store
881 assert(!pkt
->isError());
883 numCycles
+= tickToCycles(curTick
- previousTick
);
884 previousTick
= curTick
;
886 if (pkt
->senderState
) {
887 SplitFragmentSenderState
* send_state
=
888 dynamic_cast<SplitFragmentSenderState
*>(pkt
->senderState
);
892 PacketPtr big_pkt
= send_state
->bigPkt
;
895 SplitMainSenderState
* main_send_state
=
896 dynamic_cast<SplitMainSenderState
*>(big_pkt
->senderState
);
897 assert(main_send_state
);
898 // Record the fact that this packet is no longer outstanding.
899 assert(main_send_state
->outstanding
!= 0);
900 main_send_state
->outstanding
--;
902 if (main_send_state
->outstanding
) {
905 delete main_send_state
;
906 big_pkt
->senderState
= NULL
;
911 assert(_status
== DcacheWaitResponse
);
914 Fault fault
= curStaticInst
->completeAcc(pkt
, this, traceData
);
916 // keep an instruction count
917 if (fault
== NoFault
)
919 else if (traceData
) {
920 // If there was a fault, we shouldn't trace this instruction.
925 // the locked flag may be cleared on the response packet, so check
926 // pkt->req and not pkt to see if it was a load-locked
927 if (pkt
->isRead() && pkt
->req
->isLocked()) {
928 TheISA::handleLockedRead(thread
, pkt
->req
);
936 if (getState() == SimObject::Draining
) {
948 TimingSimpleCPU::completeDrain()
950 DPRINTF(Config
, "Done draining\n");
951 changeState(SimObject::Drained
);
952 drainEvent
->process();
956 TimingSimpleCPU::DcachePort::setPeer(Port
*port
)
961 // Update the ThreadContext's memory ports (Functional/Virtual
963 cpu
->tcBase()->connectMemPorts(cpu
->tcBase());
968 TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt
)
970 if (pkt
->isResponse() && !pkt
->wasNacked()) {
971 // delay processing of returned data until next CPU clock edge
972 Tick next_tick
= cpu
->nextCycle(curTick
);
974 if (next_tick
== curTick
) {
975 cpu
->completeDataAccess(pkt
);
977 tickEvent
.schedule(pkt
, next_tick
);
982 else if (pkt
->wasNacked()) {
983 assert(cpu
->_status
== DcacheWaitResponse
);
985 if (!sendTiming(pkt
)) {
986 cpu
->_status
= DcacheRetry
;
987 cpu
->dcache_pkt
= pkt
;
990 //Snooping a Coherence Request, do nothing
995 TimingSimpleCPU::DcachePort::DTickEvent::process()
997 cpu
->completeDataAccess(pkt
);
1001 TimingSimpleCPU::DcachePort::recvRetry()
1003 // we shouldn't get a retry unless we have a packet that we're
1004 // waiting to transmit
1005 assert(cpu
->dcache_pkt
!= NULL
);
1006 assert(cpu
->_status
== DcacheRetry
);
1007 PacketPtr tmp
= cpu
->dcache_pkt
;
1008 if (tmp
->senderState
) {
1009 // This is a packet from a split access.
1010 SplitFragmentSenderState
* send_state
=
1011 dynamic_cast<SplitFragmentSenderState
*>(tmp
->senderState
);
1013 PacketPtr big_pkt
= send_state
->bigPkt
;
1015 SplitMainSenderState
* main_send_state
=
1016 dynamic_cast<SplitMainSenderState
*>(big_pkt
->senderState
);
1017 assert(main_send_state
);
1019 if (sendTiming(tmp
)) {
1020 // If we were able to send without retrying, record that fact
1021 // and try sending the other fragment.
1022 send_state
->clearFromParent();
1023 int other_index
= main_send_state
->getPendingFragment();
1024 if (other_index
> 0) {
1025 tmp
= main_send_state
->fragments
[other_index
];
1026 cpu
->dcache_pkt
= tmp
;
1027 if ((big_pkt
->isRead() && cpu
->handleReadPacket(tmp
)) ||
1028 (big_pkt
->isWrite() && cpu
->handleWritePacket())) {
1029 main_send_state
->fragments
[other_index
] = NULL
;
1032 cpu
->_status
= DcacheWaitResponse
;
1033 // memory system takes ownership of packet
1034 cpu
->dcache_pkt
= NULL
;
1037 } else if (sendTiming(tmp
)) {
1038 cpu
->_status
= DcacheWaitResponse
;
1039 // memory system takes ownership of packet
1040 cpu
->dcache_pkt
= NULL
;
1044 TimingSimpleCPU::IprEvent::IprEvent(Packet
*_pkt
, TimingSimpleCPU
*_cpu
,
1046 : pkt(_pkt
), cpu(_cpu
)
1048 cpu
->schedule(this, t
);
1052 TimingSimpleCPU::IprEvent::process()
1054 cpu
->completeDataAccess(pkt
);
1058 TimingSimpleCPU::IprEvent::description() const
1060 return "Timing Simple CPU Delay IPR event";
1065 TimingSimpleCPU::printAddr(Addr a
)
1067 dcachePort
.printAddr(a
);
1071 ////////////////////////////////////////////////////////////////////////
1073 // TimingSimpleCPU Simulation Object
1076 TimingSimpleCPUParams::create()
1080 if (workload
.size() != 1)
1081 panic("only one workload allowed");
1083 return new TimingSimpleCPU(this);