2 * Copyright 2014 Google, Inc.
3 * Copyright (c) 2010-2013,2015 ARM Limited
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
12 * unmodified and in its entirety in all distributions of the software,
13 * modified or unmodified, in source code or in binary form.
15 * Copyright (c) 2002-2005 The Regents of The University of Michigan
16 * All rights reserved.
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 * Authors: Steve Reinhardt
44 #include "arch/locked_mem.hh"
45 #include "arch/mmapped_ipr.hh"
46 #include "arch/utility.hh"
47 #include "base/bigint.hh"
48 #include "config/the_isa.hh"
49 #include "cpu/simple/timing.hh"
50 #include "cpu/exetrace.hh"
51 #include "debug/Config.hh"
52 #include "debug/Drain.hh"
53 #include "debug/ExecFaulting.hh"
54 #include "debug/SimpleCPU.hh"
55 #include "mem/packet.hh"
56 #include "mem/packet_access.hh"
57 #include "params/TimingSimpleCPU.hh"
58 #include "sim/faults.hh"
59 #include "sim/full_system.hh"
60 #include "sim/system.hh"
62 #include "debug/Mwait.hh"
65 using namespace TheISA
;
68 TimingSimpleCPU::init()
70 BaseSimpleCPU::init();
74 TimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt
, Tick t
)
77 cpu
->schedule(this, t
);
80 TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams
*p
)
81 : BaseSimpleCPU(p
), fetchTranslation(this), icachePort(this),
82 dcachePort(this), ifetch_pkt(NULL
), dcache_pkt(NULL
), previousCycle(0),
90 TimingSimpleCPU::~TimingSimpleCPU()
95 TimingSimpleCPU::drain()
98 return DrainState::Drained
;
100 if (_status
== Idle
||
101 (_status
== BaseSimpleCPU::Running
&& isDrained())) {
102 DPRINTF(Drain
, "No need to drain.\n");
103 activeThreads
.clear();
104 return DrainState::Drained
;
106 DPRINTF(Drain
, "Requesting drain.\n");
108 // The fetch event can become descheduled if a drain didn't
109 // succeed on the first attempt. We need to reschedule it if
110 // the CPU is waiting for a microcode routine to complete.
111 if (_status
== BaseSimpleCPU::Running
&& !fetchEvent
.scheduled())
112 schedule(fetchEvent
, clockEdge());
114 return DrainState::Draining
;
119 TimingSimpleCPU::drainResume()
121 assert(!fetchEvent
.scheduled());
125 DPRINTF(SimpleCPU
, "Resume\n");
128 assert(!threadContexts
.empty());
130 _status
= BaseSimpleCPU::Idle
;
132 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
133 if (threadInfo
[tid
]->thread
->status() == ThreadContext::Active
) {
134 threadInfo
[tid
]->notIdleFraction
= 1;
136 activeThreads
.push_back(tid
);
138 _status
= BaseSimpleCPU::Running
;
140 // Fetch if any threads active
141 if (!fetchEvent
.scheduled()) {
142 schedule(fetchEvent
, nextCycle());
145 threadInfo
[tid
]->notIdleFraction
= 0;
149 system
->totalNumInsts
= 0;
153 TimingSimpleCPU::tryCompleteDrain()
155 if (drainState() != DrainState::Draining
)
158 DPRINTF(Drain
, "tryCompleteDrain.\n");
162 DPRINTF(Drain
, "CPU done draining, processing drain event\n");
169 TimingSimpleCPU::switchOut()
171 SimpleExecContext
& t_info
= *threadInfo
[curThread
];
172 M5_VAR_USED SimpleThread
* thread
= t_info
.thread
;
174 BaseSimpleCPU::switchOut();
176 assert(!fetchEvent
.scheduled());
177 assert(_status
== BaseSimpleCPU::Running
|| _status
== Idle
);
178 assert(!t_info
.stayAtPC
);
179 assert(thread
->microPC() == 0);
186 TimingSimpleCPU::takeOverFrom(BaseCPU
*oldCPU
)
188 BaseSimpleCPU::takeOverFrom(oldCPU
);
190 previousCycle
= curCycle();
194 TimingSimpleCPU::verifyMemoryMode() const
196 if (!system
->isTimingMode()) {
197 fatal("The timing CPU requires the memory system to be in "
203 TimingSimpleCPU::activateContext(ThreadID thread_num
)
205 DPRINTF(SimpleCPU
, "ActivateContext %d\n", thread_num
);
207 assert(thread_num
< numThreads
);
209 threadInfo
[thread_num
]->notIdleFraction
= 1;
210 if (_status
== BaseSimpleCPU::Idle
)
211 _status
= BaseSimpleCPU::Running
;
213 // kick things off by initiating the fetch of the next instruction
214 if (!fetchEvent
.scheduled())
215 schedule(fetchEvent
, clockEdge(Cycles(0)));
217 if (std::find(activeThreads
.begin(), activeThreads
.end(), thread_num
)
218 == activeThreads
.end()) {
219 activeThreads
.push_back(thread_num
);
222 BaseCPU::activateContext(thread_num
);
227 TimingSimpleCPU::suspendContext(ThreadID thread_num
)
229 DPRINTF(SimpleCPU
, "SuspendContext %d\n", thread_num
);
231 assert(thread_num
< numThreads
);
232 activeThreads
.remove(thread_num
);
237 assert(_status
== BaseSimpleCPU::Running
);
239 threadInfo
[thread_num
]->notIdleFraction
= 0;
241 if (activeThreads
.empty()) {
244 if (fetchEvent
.scheduled()) {
245 deschedule(fetchEvent
);
249 BaseCPU::suspendContext(thread_num
);
253 TimingSimpleCPU::handleReadPacket(PacketPtr pkt
)
255 SimpleExecContext
&t_info
= *threadInfo
[curThread
];
256 SimpleThread
* thread
= t_info
.thread
;
258 RequestPtr req
= pkt
->req
;
260 // We're about the issues a locked load, so tell the monitor
261 // to start caring about this address
262 if (pkt
->isRead() && pkt
->req
->isLLSC()) {
263 TheISA::handleLockedRead(thread
, pkt
->req
);
265 if (req
->isMmappedIpr()) {
266 Cycles delay
= TheISA::handleIprRead(thread
->getTC(), pkt
);
267 new IprEvent(pkt
, this, clockEdge(delay
));
268 _status
= DcacheWaitResponse
;
270 } else if (!dcachePort
.sendTimingReq(pkt
)) {
271 _status
= DcacheRetry
;
274 _status
= DcacheWaitResponse
;
275 // memory system takes ownership of packet
278 return dcache_pkt
== NULL
;
282 TimingSimpleCPU::sendData(RequestPtr req
, uint8_t *data
, uint64_t *res
,
285 SimpleExecContext
&t_info
= *threadInfo
[curThread
];
286 SimpleThread
* thread
= t_info
.thread
;
288 PacketPtr pkt
= buildPacket(req
, read
);
289 pkt
->dataDynamic
<uint8_t>(data
);
290 if (req
->getFlags().isSet(Request::NO_ACCESS
)) {
293 completeDataAccess(pkt
);
295 handleReadPacket(pkt
);
297 bool do_access
= true; // flag to suppress cache access
300 do_access
= TheISA::handleLockedWrite(thread
, req
, dcachePort
.cacheBlockMask
);
301 } else if (req
->isCondSwap()) {
303 req
->setExtraData(*res
);
309 threadSnoop(pkt
, curThread
);
311 _status
= DcacheWaitResponse
;
312 completeDataAccess(pkt
);
318 TimingSimpleCPU::sendSplitData(RequestPtr req1
, RequestPtr req2
,
319 RequestPtr req
, uint8_t *data
, bool read
)
321 PacketPtr pkt1
, pkt2
;
322 buildSplitPacket(pkt1
, pkt2
, req1
, req2
, req
, data
, read
);
323 if (req
->getFlags().isSet(Request::NO_ACCESS
)) {
325 pkt1
->makeResponse();
326 completeDataAccess(pkt1
);
328 SplitFragmentSenderState
* send_state
=
329 dynamic_cast<SplitFragmentSenderState
*>(pkt1
->senderState
);
330 if (handleReadPacket(pkt1
)) {
331 send_state
->clearFromParent();
332 send_state
= dynamic_cast<SplitFragmentSenderState
*>(
334 if (handleReadPacket(pkt2
)) {
335 send_state
->clearFromParent();
340 SplitFragmentSenderState
* send_state
=
341 dynamic_cast<SplitFragmentSenderState
*>(pkt1
->senderState
);
342 if (handleWritePacket()) {
343 send_state
->clearFromParent();
345 send_state
= dynamic_cast<SplitFragmentSenderState
*>(
347 if (handleWritePacket()) {
348 send_state
->clearFromParent();
355 TimingSimpleCPU::translationFault(const Fault
&fault
)
357 // fault may be NoFault in cases where a fault is suppressed,
358 // for instance prefetches.
362 // Since there was a fault, we shouldn't trace this instruction.
373 TimingSimpleCPU::buildPacket(RequestPtr req
, bool read
)
375 return read
? Packet::createRead(req
) : Packet::createWrite(req
);
379 TimingSimpleCPU::buildSplitPacket(PacketPtr
&pkt1
, PacketPtr
&pkt2
,
380 RequestPtr req1
, RequestPtr req2
, RequestPtr req
,
381 uint8_t *data
, bool read
)
385 assert(!req1
->isMmappedIpr() && !req2
->isMmappedIpr());
387 if (req
->getFlags().isSet(Request::NO_ACCESS
)) {
388 pkt1
= buildPacket(req
, read
);
392 pkt1
= buildPacket(req1
, read
);
393 pkt2
= buildPacket(req2
, read
);
395 PacketPtr pkt
= new Packet(req
, pkt1
->cmd
.responseCommand());
397 pkt
->dataDynamic
<uint8_t>(data
);
398 pkt1
->dataStatic
<uint8_t>(data
);
399 pkt2
->dataStatic
<uint8_t>(data
+ req1
->getSize());
401 SplitMainSenderState
* main_send_state
= new SplitMainSenderState
;
402 pkt
->senderState
= main_send_state
;
403 main_send_state
->fragments
[0] = pkt1
;
404 main_send_state
->fragments
[1] = pkt2
;
405 main_send_state
->outstanding
= 2;
406 pkt1
->senderState
= new SplitFragmentSenderState(pkt
, 0);
407 pkt2
->senderState
= new SplitFragmentSenderState(pkt
, 1);
411 TimingSimpleCPU::readMem(Addr addr
, uint8_t *data
,
412 unsigned size
, unsigned flags
)
414 panic("readMem() is for atomic accesses, and should "
415 "never be called on TimingSimpleCPU.\n");
419 TimingSimpleCPU::initiateMemRead(Addr addr
, unsigned size
, unsigned flags
)
421 SimpleExecContext
&t_info
= *threadInfo
[curThread
];
422 SimpleThread
* thread
= t_info
.thread
;
426 const Addr pc
= thread
->instAddr();
427 unsigned block_size
= cacheLineSize();
428 BaseTLB::Mode mode
= BaseTLB::Read
;
431 traceData
->setMem(addr
, size
, flags
);
433 RequestPtr req
= new Request(asid
, addr
, size
, flags
, dataMasterId(), pc
,
434 thread
->contextId());
436 req
->taskId(taskId());
438 Addr split_addr
= roundDown(addr
+ size
- 1, block_size
);
439 assert(split_addr
<= addr
|| split_addr
- addr
< block_size
);
441 _status
= DTBWaitResponse
;
442 if (split_addr
> addr
) {
443 RequestPtr req1
, req2
;
444 assert(!req
->isLLSC() && !req
->isSwap());
445 req
->splitOnVaddr(split_addr
, req1
, req2
);
447 WholeTranslationState
*state
=
448 new WholeTranslationState(req
, req1
, req2
, new uint8_t[size
],
450 DataTranslation
<TimingSimpleCPU
*> *trans1
=
451 new DataTranslation
<TimingSimpleCPU
*>(this, state
, 0);
452 DataTranslation
<TimingSimpleCPU
*> *trans2
=
453 new DataTranslation
<TimingSimpleCPU
*>(this, state
, 1);
455 thread
->dtb
->translateTiming(req1
, thread
->getTC(), trans1
, mode
);
456 thread
->dtb
->translateTiming(req2
, thread
->getTC(), trans2
, mode
);
458 WholeTranslationState
*state
=
459 new WholeTranslationState(req
, new uint8_t[size
], NULL
, mode
);
460 DataTranslation
<TimingSimpleCPU
*> *translation
461 = new DataTranslation
<TimingSimpleCPU
*>(this, state
);
462 thread
->dtb
->translateTiming(req
, thread
->getTC(), translation
, mode
);
469 TimingSimpleCPU::handleWritePacket()
471 SimpleExecContext
&t_info
= *threadInfo
[curThread
];
472 SimpleThread
* thread
= t_info
.thread
;
474 RequestPtr req
= dcache_pkt
->req
;
475 if (req
->isMmappedIpr()) {
476 Cycles delay
= TheISA::handleIprWrite(thread
->getTC(), dcache_pkt
);
477 new IprEvent(dcache_pkt
, this, clockEdge(delay
));
478 _status
= DcacheWaitResponse
;
480 } else if (!dcachePort
.sendTimingReq(dcache_pkt
)) {
481 _status
= DcacheRetry
;
483 _status
= DcacheWaitResponse
;
484 // memory system takes ownership of packet
487 return dcache_pkt
== NULL
;
491 TimingSimpleCPU::writeMem(uint8_t *data
, unsigned size
,
492 Addr addr
, unsigned flags
, uint64_t *res
)
494 SimpleExecContext
&t_info
= *threadInfo
[curThread
];
495 SimpleThread
* thread
= t_info
.thread
;
497 uint8_t *newData
= new uint8_t[size
];
499 const Addr pc
= thread
->instAddr();
500 unsigned block_size
= cacheLineSize();
501 BaseTLB::Mode mode
= BaseTLB::Write
;
504 assert(flags
& Request::CACHE_BLOCK_ZERO
);
505 // This must be a cache block cleaning request
506 memset(newData
, 0, size
);
508 memcpy(newData
, data
, size
);
512 traceData
->setMem(addr
, size
, flags
);
514 RequestPtr req
= new Request(asid
, addr
, size
, flags
, dataMasterId(), pc
,
515 thread
->contextId());
517 req
->taskId(taskId());
519 Addr split_addr
= roundDown(addr
+ size
- 1, block_size
);
520 assert(split_addr
<= addr
|| split_addr
- addr
< block_size
);
522 _status
= DTBWaitResponse
;
523 if (split_addr
> addr
) {
524 RequestPtr req1
, req2
;
525 assert(!req
->isLLSC() && !req
->isSwap());
526 req
->splitOnVaddr(split_addr
, req1
, req2
);
528 WholeTranslationState
*state
=
529 new WholeTranslationState(req
, req1
, req2
, newData
, res
, mode
);
530 DataTranslation
<TimingSimpleCPU
*> *trans1
=
531 new DataTranslation
<TimingSimpleCPU
*>(this, state
, 0);
532 DataTranslation
<TimingSimpleCPU
*> *trans2
=
533 new DataTranslation
<TimingSimpleCPU
*>(this, state
, 1);
535 thread
->dtb
->translateTiming(req1
, thread
->getTC(), trans1
, mode
);
536 thread
->dtb
->translateTiming(req2
, thread
->getTC(), trans2
, mode
);
538 WholeTranslationState
*state
=
539 new WholeTranslationState(req
, newData
, res
, mode
);
540 DataTranslation
<TimingSimpleCPU
*> *translation
=
541 new DataTranslation
<TimingSimpleCPU
*>(this, state
);
542 thread
->dtb
->translateTiming(req
, thread
->getTC(), translation
, mode
);
545 // Translation faults will be returned via finishTranslation()
550 TimingSimpleCPU::threadSnoop(PacketPtr pkt
, ThreadID sender
)
552 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
554 if (getCpuAddrMonitor(tid
)->doMonitor(pkt
)) {
557 TheISA::handleLockedSnoop(threadInfo
[tid
]->thread
, pkt
,
558 dcachePort
.cacheBlockMask
);
564 TimingSimpleCPU::finishTranslation(WholeTranslationState
*state
)
566 _status
= BaseSimpleCPU::Running
;
568 if (state
->getFault() != NoFault
) {
569 if (state
->isPrefetch()) {
572 delete [] state
->data
;
574 translationFault(state
->getFault());
576 if (!state
->isSplit
) {
577 sendData(state
->mainReq
, state
->data
, state
->res
,
578 state
->mode
== BaseTLB::Read
);
580 sendSplitData(state
->sreqLow
, state
->sreqHigh
, state
->mainReq
,
581 state
->data
, state
->mode
== BaseTLB::Read
);
590 TimingSimpleCPU::fetch()
592 // Change thread if multi-threaded
595 SimpleExecContext
&t_info
= *threadInfo
[curThread
];
596 SimpleThread
* thread
= t_info
.thread
;
598 DPRINTF(SimpleCPU
, "Fetch\n");
600 if (!curStaticInst
|| !curStaticInst
->isDelayedCommit()) {
601 checkForInterrupts();
605 // We must have just got suspended by a PC event
609 TheISA::PCState pcState
= thread
->pcState();
610 bool needToFetch
= !isRomMicroPC(pcState
.microPC()) &&
614 _status
= BaseSimpleCPU::Running
;
615 Request
*ifetch_req
= new Request();
616 ifetch_req
->taskId(taskId());
617 ifetch_req
->setContext(thread
->contextId());
618 setupFetchRequest(ifetch_req
);
619 DPRINTF(SimpleCPU
, "Translating address %#x\n", ifetch_req
->getVaddr());
620 thread
->itb
->translateTiming(ifetch_req
, thread
->getTC(),
621 &fetchTranslation
, BaseTLB::Execute
);
623 _status
= IcacheWaitResponse
;
624 completeIfetch(NULL
);
632 TimingSimpleCPU::sendFetch(const Fault
&fault
, RequestPtr req
,
635 if (fault
== NoFault
) {
636 DPRINTF(SimpleCPU
, "Sending fetch for addr %#x(pa: %#x)\n",
637 req
->getVaddr(), req
->getPaddr());
638 ifetch_pkt
= new Packet(req
, MemCmd::ReadReq
);
639 ifetch_pkt
->dataStatic(&inst
);
640 DPRINTF(SimpleCPU
, " -- pkt addr: %#x\n", ifetch_pkt
->getAddr());
642 if (!icachePort
.sendTimingReq(ifetch_pkt
)) {
643 // Need to wait for retry
644 _status
= IcacheRetry
;
646 // Need to wait for cache to respond
647 _status
= IcacheWaitResponse
;
648 // ownership of packet transferred to memory system
652 DPRINTF(SimpleCPU
, "Translation of addr %#x faulted\n", req
->getVaddr());
654 // fetch fault: advance directly to next instruction (fault handler)
655 _status
= BaseSimpleCPU::Running
;
664 TimingSimpleCPU::advanceInst(const Fault
&fault
)
666 SimpleExecContext
&t_info
= *threadInfo
[curThread
];
668 if (_status
== Faulting
)
671 if (fault
!= NoFault
) {
673 DPRINTF(SimpleCPU
, "Fault occured, scheduling fetch event\n");
674 reschedule(fetchEvent
, clockEdge(), true);
680 if (!t_info
.stayAtPC
)
683 if (tryCompleteDrain())
686 if (_status
== BaseSimpleCPU::Running
) {
687 // kick off fetch of next instruction... callback from icache
688 // response will cause that instruction to be executed,
689 // keeping the CPU running.
696 TimingSimpleCPU::completeIfetch(PacketPtr pkt
)
698 SimpleExecContext
& t_info
= *threadInfo
[curThread
];
700 DPRINTF(SimpleCPU
, "Complete ICache Fetch for addr %#x\n", pkt
?
703 // received a response from the icache: execute the received
705 assert(!pkt
|| !pkt
->isError());
706 assert(_status
== IcacheWaitResponse
);
708 _status
= BaseSimpleCPU::Running
;
713 pkt
->req
->setAccessLatency();
717 if (curStaticInst
&& curStaticInst
->isMemRef()) {
718 // load or store: just send to dcache
719 Fault fault
= curStaticInst
->initiateAcc(&t_info
, traceData
);
721 // If we're not running now the instruction will complete in a dcache
722 // response callback or the instruction faulted and has started an
724 if (_status
== BaseSimpleCPU::Running
) {
725 if (fault
!= NoFault
&& traceData
) {
726 // If there was a fault, we shouldn't trace this instruction.
732 // @todo remove me after debugging with legion done
733 if (curStaticInst
&& (!curStaticInst
->isMicroop() ||
734 curStaticInst
->isFirstMicroop()))
738 } else if (curStaticInst
) {
739 // non-memory instruction: execute completely now
740 Fault fault
= curStaticInst
->execute(&t_info
, traceData
);
742 // keep an instruction count
743 if (fault
== NoFault
)
745 else if (traceData
&& !DTRACE(ExecFaulting
)) {
751 // @todo remove me after debugging with legion done
752 if (curStaticInst
&& (!curStaticInst
->isMicroop() ||
753 curStaticInst
->isFirstMicroop()))
757 advanceInst(NoFault
);
767 TimingSimpleCPU::IcachePort::ITickEvent::process()
769 cpu
->completeIfetch(pkt
);
773 TimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt
)
775 DPRINTF(SimpleCPU
, "Received fetch response %#x\n", pkt
->getAddr());
776 // we should only ever see one response per cycle since we only
777 // issue a new request once this response is sunk
778 assert(!tickEvent
.scheduled());
779 // delay processing of returned data until next CPU clock edge
780 tickEvent
.schedule(pkt
, cpu
->clockEdge());
786 TimingSimpleCPU::IcachePort::recvReqRetry()
788 // we shouldn't get a retry unless we have a packet that we're
789 // waiting to transmit
790 assert(cpu
->ifetch_pkt
!= NULL
);
791 assert(cpu
->_status
== IcacheRetry
);
792 PacketPtr tmp
= cpu
->ifetch_pkt
;
793 if (sendTimingReq(tmp
)) {
794 cpu
->_status
= IcacheWaitResponse
;
795 cpu
->ifetch_pkt
= NULL
;
800 TimingSimpleCPU::completeDataAccess(PacketPtr pkt
)
802 // received a response from the dcache: complete the load or store
804 assert(!pkt
->isError());
805 assert(_status
== DcacheWaitResponse
|| _status
== DTBWaitResponse
||
806 pkt
->req
->getFlags().isSet(Request::NO_ACCESS
));
808 pkt
->req
->setAccessLatency();
812 if (pkt
->senderState
) {
813 SplitFragmentSenderState
* send_state
=
814 dynamic_cast<SplitFragmentSenderState
*>(pkt
->senderState
);
818 PacketPtr big_pkt
= send_state
->bigPkt
;
821 SplitMainSenderState
* main_send_state
=
822 dynamic_cast<SplitMainSenderState
*>(big_pkt
->senderState
);
823 assert(main_send_state
);
824 // Record the fact that this packet is no longer outstanding.
825 assert(main_send_state
->outstanding
!= 0);
826 main_send_state
->outstanding
--;
828 if (main_send_state
->outstanding
) {
831 delete main_send_state
;
832 big_pkt
->senderState
= NULL
;
837 _status
= BaseSimpleCPU::Running
;
839 Fault fault
= curStaticInst
->completeAcc(pkt
, threadInfo
[curThread
],
842 // keep an instruction count
843 if (fault
== NoFault
)
845 else if (traceData
) {
846 // If there was a fault, we shouldn't trace this instruction.
860 TimingSimpleCPU::updateCycleCounts()
862 const Cycles
delta(curCycle() - previousCycle
);
865 ppCycles
->notify(delta
);
867 previousCycle
= curCycle();
871 TimingSimpleCPU::DcachePort::recvTimingSnoopReq(PacketPtr pkt
)
873 for (ThreadID tid
= 0; tid
< cpu
->numThreads
; tid
++) {
874 if (cpu
->getCpuAddrMonitor(tid
)->doMonitor(pkt
)) {
879 // Making it uniform across all CPUs:
880 // The CPUs need to be woken up only on an invalidation packet (when using caches)
881 // or on an incoming write packet (when not using caches)
882 // It is not necessary to wake up the processor on all incoming packets
883 if (pkt
->isInvalidate() || pkt
->isWrite()) {
884 for (auto &t_info
: cpu
->threadInfo
) {
885 TheISA::handleLockedSnoop(t_info
->thread
, pkt
, cacheBlockMask
);
891 TimingSimpleCPU::DcachePort::recvFunctionalSnoop(PacketPtr pkt
)
893 for (ThreadID tid
= 0; tid
< cpu
->numThreads
; tid
++) {
894 if (cpu
->getCpuAddrMonitor(tid
)->doMonitor(pkt
)) {
901 TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt
)
903 DPRINTF(SimpleCPU
, "Received load/store response %#x\n", pkt
->getAddr());
905 // The timing CPU is not really ticked, instead it relies on the
906 // memory system (fetch and load/store) to set the pace.
907 if (!tickEvent
.scheduled()) {
908 // Delay processing of returned data until next CPU clock edge
909 tickEvent
.schedule(pkt
, cpu
->clockEdge());
912 // In the case of a split transaction and a cache that is
913 // faster than a CPU we could get two responses in the
914 // same tick, delay the second one
915 if (!retryRespEvent
.scheduled())
916 cpu
->schedule(retryRespEvent
, cpu
->clockEdge(Cycles(1)));
922 TimingSimpleCPU::DcachePort::DTickEvent::process()
924 cpu
->completeDataAccess(pkt
);
928 TimingSimpleCPU::DcachePort::recvReqRetry()
930 // we shouldn't get a retry unless we have a packet that we're
931 // waiting to transmit
932 assert(cpu
->dcache_pkt
!= NULL
);
933 assert(cpu
->_status
== DcacheRetry
);
934 PacketPtr tmp
= cpu
->dcache_pkt
;
935 if (tmp
->senderState
) {
936 // This is a packet from a split access.
937 SplitFragmentSenderState
* send_state
=
938 dynamic_cast<SplitFragmentSenderState
*>(tmp
->senderState
);
940 PacketPtr big_pkt
= send_state
->bigPkt
;
942 SplitMainSenderState
* main_send_state
=
943 dynamic_cast<SplitMainSenderState
*>(big_pkt
->senderState
);
944 assert(main_send_state
);
946 if (sendTimingReq(tmp
)) {
947 // If we were able to send without retrying, record that fact
948 // and try sending the other fragment.
949 send_state
->clearFromParent();
950 int other_index
= main_send_state
->getPendingFragment();
951 if (other_index
> 0) {
952 tmp
= main_send_state
->fragments
[other_index
];
953 cpu
->dcache_pkt
= tmp
;
954 if ((big_pkt
->isRead() && cpu
->handleReadPacket(tmp
)) ||
955 (big_pkt
->isWrite() && cpu
->handleWritePacket())) {
956 main_send_state
->fragments
[other_index
] = NULL
;
959 cpu
->_status
= DcacheWaitResponse
;
960 // memory system takes ownership of packet
961 cpu
->dcache_pkt
= NULL
;
964 } else if (sendTimingReq(tmp
)) {
965 cpu
->_status
= DcacheWaitResponse
;
966 // memory system takes ownership of packet
967 cpu
->dcache_pkt
= NULL
;
971 TimingSimpleCPU::IprEvent::IprEvent(Packet
*_pkt
, TimingSimpleCPU
*_cpu
,
973 : pkt(_pkt
), cpu(_cpu
)
975 cpu
->schedule(this, t
);
979 TimingSimpleCPU::IprEvent::process()
981 cpu
->completeDataAccess(pkt
);
985 TimingSimpleCPU::IprEvent::description() const
987 return "Timing Simple CPU Delay IPR event";
992 TimingSimpleCPU::printAddr(Addr a
)
994 dcachePort
.printAddr(a
);
998 ////////////////////////////////////////////////////////////////////////
1000 // TimingSimpleCPU Simulation Object
1003 TimingSimpleCPUParams::create()
1005 return new TimingSimpleCPU(this);