2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
31 #include "arch/locked_mem.hh"
32 #include "arch/mmaped_ipr.hh"
33 #include "arch/utility.hh"
34 #include "base/bigint.hh"
35 #include "cpu/exetrace.hh"
36 #include "cpu/simple/timing.hh"
37 #include "mem/packet.hh"
38 #include "mem/packet_access.hh"
39 #include "params/TimingSimpleCPU.hh"
40 #include "sim/system.hh"
43 using namespace TheISA
;
46 TimingSimpleCPU::getPort(const std::string
&if_name
, int idx
)
48 if (if_name
== "dcache_port")
50 else if (if_name
== "icache_port")
53 panic("No Such Port\n");
57 TimingSimpleCPU::init()
61 for (int i
= 0; i
< threadContexts
.size(); ++i
) {
62 ThreadContext
*tc
= threadContexts
[i
];
64 // initialize CPU, including PC
65 TheISA::initCPU(tc
, _cpuId
);
71 TimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt
)
73 panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
78 TimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt
)
80 //No internal storage to update, jusst return
85 TimingSimpleCPU::CpuPort::recvStatusChange(Status status
)
87 if (status
== RangeChange
) {
88 if (!snoopRangeSent
) {
89 snoopRangeSent
= true;
90 sendStatusChange(Port::RangeChange
);
95 panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
100 TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt
, Tick t
)
103 cpu
->schedule(this, t
);
106 TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams
*p
)
107 : BaseSimpleCPU(p
), icachePort(this, p
->clock
), dcachePort(this, p
->clock
), fetchEvent(this)
111 icachePort
.snoopRangeSent
= false;
112 dcachePort
.snoopRangeSent
= false;
114 ifetch_pkt
= dcache_pkt
= NULL
;
117 changeState(SimObject::Running
);
121 TimingSimpleCPU::~TimingSimpleCPU()
126 TimingSimpleCPU::serialize(ostream
&os
)
128 SimObject::State so_state
= SimObject::getState();
129 SERIALIZE_ENUM(so_state
);
130 BaseSimpleCPU::serialize(os
);
134 TimingSimpleCPU::unserialize(Checkpoint
*cp
, const string
§ion
)
136 SimObject::State so_state
;
137 UNSERIALIZE_ENUM(so_state
);
138 BaseSimpleCPU::unserialize(cp
, section
);
142 TimingSimpleCPU::drain(Event
*drain_event
)
144 // TimingSimpleCPU is ready to drain if it's not waiting for
145 // an access to complete.
146 if (_status
== Idle
|| _status
== Running
|| _status
== SwitchedOut
) {
147 changeState(SimObject::Drained
);
150 changeState(SimObject::Draining
);
151 drainEvent
= drain_event
;
157 TimingSimpleCPU::resume()
159 DPRINTF(SimpleCPU
, "Resume\n");
160 if (_status
!= SwitchedOut
&& _status
!= Idle
) {
161 assert(system
->getMemoryMode() == Enums::timing
);
163 if (fetchEvent
.scheduled())
164 deschedule(fetchEvent
);
166 schedule(fetchEvent
, nextCycle());
169 changeState(SimObject::Running
);
173 TimingSimpleCPU::switchOut()
175 assert(_status
== Running
|| _status
== Idle
);
176 _status
= SwitchedOut
;
177 numCycles
+= tickToCycles(curTick
- previousTick
);
179 // If we've been scheduled to resume but are then told to switch out,
180 // we'll need to cancel it.
181 if (fetchEvent
.scheduled())
182 deschedule(fetchEvent
);
187 TimingSimpleCPU::takeOverFrom(BaseCPU
*oldCPU
)
189 BaseCPU::takeOverFrom(oldCPU
, &icachePort
, &dcachePort
);
191 // if any of this CPU's ThreadContexts are active, mark the CPU as
192 // running and schedule its tick event.
193 for (int i
= 0; i
< threadContexts
.size(); ++i
) {
194 ThreadContext
*tc
= threadContexts
[i
];
195 if (tc
->status() == ThreadContext::Active
&& _status
!= Running
) {
201 if (_status
!= Running
) {
204 assert(threadContexts
.size() == 1);
205 previousTick
= curTick
;
210 TimingSimpleCPU::activateContext(int thread_num
, int delay
)
212 DPRINTF(SimpleCPU
, "ActivateContext %d (%d cycles)\n", thread_num
, delay
);
214 assert(thread_num
== 0);
217 assert(_status
== Idle
);
222 // kick things off by initiating the fetch of the next instruction
223 schedule(fetchEvent
, nextCycle(curTick
+ ticks(delay
)));
228 TimingSimpleCPU::suspendContext(int thread_num
)
230 DPRINTF(SimpleCPU
, "SuspendContext %d\n", thread_num
);
232 assert(thread_num
== 0);
235 assert(_status
== Running
);
237 // just change status to Idle... if status != Running,
238 // completeInst() will not initiate fetch of next instruction.
247 TimingSimpleCPU::read(Addr addr
, T
&data
, unsigned flags
)
250 new Request(/* asid */ 0, addr
, sizeof(T
), flags
, thread
->readPC(),
251 _cpuId
, /* thread ID */ 0);
254 traceData
->setAddr(req
->getVaddr());
257 // translate to physical address
258 Fault fault
= thread
->translateDataReadReq(req
);
260 // Now do the access.
261 if (fault
== NoFault
) {
265 MemCmd::LoadLockedReq
: MemCmd::ReadReq
),
267 pkt
->dataDynamic
<T
>(new T
);
269 if (req
->isMmapedIpr()) {
271 delay
= TheISA::handleIprRead(thread
->getTC(), pkt
);
272 new IprEvent(pkt
, this, nextCycle(curTick
+ delay
));
273 _status
= DcacheWaitResponse
;
275 } else if (!dcachePort
.sendTiming(pkt
)) {
276 _status
= DcacheRetry
;
279 _status
= DcacheWaitResponse
;
280 // memory system takes ownership of packet
284 // This will need a new way to tell if it has a dcache attached.
285 if (req
->isUncacheable())
286 recordEvent("Uncached Read");
292 traceData
->setData(data
);
298 TimingSimpleCPU::translateDataReadAddr(Addr vaddr
, Addr
&paddr
,
299 int size
, unsigned flags
)
302 new Request(0, vaddr
, size
, flags
, thread
->readPC(), _cpuId
, 0);
305 traceData
->setAddr(vaddr
);
308 Fault fault
= thread
->translateDataWriteReq(req
);
310 if (fault
== NoFault
)
311 paddr
= req
->getPaddr();
317 #ifndef DOXYGEN_SHOULD_SKIP_THIS
321 TimingSimpleCPU::read(Addr addr
, Twin64_t
&data
, unsigned flags
);
325 TimingSimpleCPU::read(Addr addr
, Twin32_t
&data
, unsigned flags
);
329 TimingSimpleCPU::read(Addr addr
, uint64_t &data
, unsigned flags
);
333 TimingSimpleCPU::read(Addr addr
, uint32_t &data
, unsigned flags
);
337 TimingSimpleCPU::read(Addr addr
, uint16_t &data
, unsigned flags
);
341 TimingSimpleCPU::read(Addr addr
, uint8_t &data
, unsigned flags
);
343 #endif //DOXYGEN_SHOULD_SKIP_THIS
347 TimingSimpleCPU::read(Addr addr
, double &data
, unsigned flags
)
349 return read(addr
, *(uint64_t*)&data
, flags
);
354 TimingSimpleCPU::read(Addr addr
, float &data
, unsigned flags
)
356 return read(addr
, *(uint32_t*)&data
, flags
);
362 TimingSimpleCPU::read(Addr addr
, int32_t &data
, unsigned flags
)
364 return read(addr
, (uint32_t&)data
, flags
);
370 TimingSimpleCPU::write(T data
, Addr addr
, unsigned flags
, uint64_t *res
)
373 new Request(/* asid */ 0, addr
, sizeof(T
), flags
, thread
->readPC(),
374 _cpuId
, /* thread ID */ 0);
377 traceData
->setAddr(req
->getVaddr());
380 // translate to physical address
381 Fault fault
= thread
->translateDataWriteReq(req
);
383 // Now do the access.
384 if (fault
== NoFault
) {
385 MemCmd cmd
= MemCmd::WriteReq
; // default
386 bool do_access
= true; // flag to suppress cache access
388 if (req
->isLocked()) {
389 cmd
= MemCmd::StoreCondReq
;
390 do_access
= TheISA::handleLockedWrite(thread
, req
);
391 } else if (req
->isSwap()) {
392 cmd
= MemCmd::SwapReq
;
393 if (req
->isCondSwap()) {
395 req
->setExtraData(*res
);
399 // Note: need to allocate dcache_pkt even if do_access is
400 // false, as it's used unconditionally to call completeAcc().
401 assert(dcache_pkt
== NULL
);
402 dcache_pkt
= new Packet(req
, cmd
, Packet::Broadcast
);
403 dcache_pkt
->allocate();
404 dcache_pkt
->set(data
);
407 if (req
->isMmapedIpr()) {
409 dcache_pkt
->set(htog(data
));
410 delay
= TheISA::handleIprWrite(thread
->getTC(), dcache_pkt
);
411 new IprEvent(dcache_pkt
, this, nextCycle(curTick
+ delay
));
412 _status
= DcacheWaitResponse
;
414 } else if (!dcachePort
.sendTiming(dcache_pkt
)) {
415 _status
= DcacheRetry
;
417 _status
= DcacheWaitResponse
;
418 // memory system takes ownership of packet
422 // This will need a new way to tell if it's hooked up to a cache or not.
423 if (req
->isUncacheable())
424 recordEvent("Uncached Write");
430 traceData
->setData(data
);
433 // If the write needs to have a fault on the access, consider calling
434 // changeStatus() and changing it to "bad addr write" or something.
439 TimingSimpleCPU::translateDataWriteAddr(Addr vaddr
, Addr
&paddr
,
440 int size
, unsigned flags
)
443 new Request(0, vaddr
, size
, flags
, thread
->readPC(), _cpuId
, 0);
446 traceData
->setAddr(vaddr
);
449 Fault fault
= thread
->translateDataWriteReq(req
);
451 if (fault
== NoFault
)
452 paddr
= req
->getPaddr();
459 #ifndef DOXYGEN_SHOULD_SKIP_THIS
462 TimingSimpleCPU::write(Twin32_t data
, Addr addr
,
463 unsigned flags
, uint64_t *res
);
467 TimingSimpleCPU::write(Twin64_t data
, Addr addr
,
468 unsigned flags
, uint64_t *res
);
472 TimingSimpleCPU::write(uint64_t data
, Addr addr
,
473 unsigned flags
, uint64_t *res
);
477 TimingSimpleCPU::write(uint32_t data
, Addr addr
,
478 unsigned flags
, uint64_t *res
);
482 TimingSimpleCPU::write(uint16_t data
, Addr addr
,
483 unsigned flags
, uint64_t *res
);
487 TimingSimpleCPU::write(uint8_t data
, Addr addr
,
488 unsigned flags
, uint64_t *res
);
490 #endif //DOXYGEN_SHOULD_SKIP_THIS
494 TimingSimpleCPU::write(double data
, Addr addr
, unsigned flags
, uint64_t *res
)
496 return write(*(uint64_t*)&data
, addr
, flags
, res
);
501 TimingSimpleCPU::write(float data
, Addr addr
, unsigned flags
, uint64_t *res
)
503 return write(*(uint32_t*)&data
, addr
, flags
, res
);
509 TimingSimpleCPU::write(int32_t data
, Addr addr
, unsigned flags
, uint64_t *res
)
511 return write((uint32_t)data
, addr
, flags
, res
);
516 TimingSimpleCPU::fetch()
518 DPRINTF(SimpleCPU
, "Fetch\n");
520 if (!curStaticInst
|| !curStaticInst
->isDelayedCommit())
521 checkForInterrupts();
525 bool fromRom
= isRomMicroPC(thread
->readMicroPC());
528 Request
*ifetch_req
= new Request();
529 ifetch_req
->setThreadContext(_cpuId
, /* thread ID */ 0);
530 Fault fault
= setupFetchRequest(ifetch_req
);
532 ifetch_pkt
= new Packet(ifetch_req
, MemCmd::ReadReq
, Packet::Broadcast
);
533 ifetch_pkt
->dataStatic(&inst
);
535 if (fault
== NoFault
) {
536 if (!icachePort
.sendTiming(ifetch_pkt
)) {
537 // Need to wait for retry
538 _status
= IcacheRetry
;
540 // Need to wait for cache to respond
541 _status
= IcacheWaitResponse
;
542 // ownership of packet transferred to memory system
548 // fetch fault: advance directly to next instruction (fault handler)
552 _status
= IcacheWaitResponse
;
553 completeIfetch(NULL
);
556 numCycles
+= tickToCycles(curTick
- previousTick
);
557 previousTick
= curTick
;
562 TimingSimpleCPU::advanceInst(Fault fault
)
564 if (fault
!= NoFault
|| !stayAtPC
)
567 if (_status
== Running
) {
568 // kick off fetch of next instruction... callback from icache
569 // response will cause that instruction to be executed,
570 // keeping the CPU running.
577 TimingSimpleCPU::completeIfetch(PacketPtr pkt
)
579 DPRINTF(SimpleCPU
, "Complete ICache Fetch\n");
581 // received a response from the icache: execute the received
584 assert(!pkt
|| !pkt
->isError());
585 assert(_status
== IcacheWaitResponse
);
589 numCycles
+= tickToCycles(curTick
- previousTick
);
590 previousTick
= curTick
;
592 if (getState() == SimObject::Draining
) {
604 curStaticInst
->isMemRef() && !curStaticInst
->isDataPrefetch()) {
605 // load or store: just send to dcache
606 Fault fault
= curStaticInst
->initiateAcc(this, traceData
);
607 if (_status
!= Running
) {
608 // instruction will complete in dcache response callback
609 assert(_status
== DcacheWaitResponse
|| _status
== DcacheRetry
);
610 assert(fault
== NoFault
);
612 if (fault
== NoFault
) {
613 // Note that ARM can have NULL packets if the instruction gets
614 // squashed due to predication
615 // early fail on store conditional: complete now
616 assert(dcache_pkt
!= NULL
|| THE_ISA
== ARM_ISA
);
618 fault
= curStaticInst
->completeAcc(dcache_pkt
, this,
620 if (dcache_pkt
!= NULL
)
622 delete dcache_pkt
->req
;
627 // keep an instruction count
628 if (fault
== NoFault
)
630 } else if (traceData
) {
631 // If there was a fault, we shouldn't trace this instruction.
637 // @todo remove me after debugging with legion done
638 if (curStaticInst
&& (!curStaticInst
->isMicroop() ||
639 curStaticInst
->isFirstMicroop()))
643 } else if (curStaticInst
) {
644 // non-memory instruction: execute completely now
645 Fault fault
= curStaticInst
->execute(this, traceData
);
647 // keep an instruction count
648 if (fault
== NoFault
)
650 else if (traceData
) {
651 // If there was a fault, we shouldn't trace this instruction.
657 // @todo remove me after debugging with legion done
658 if (curStaticInst
&& (!curStaticInst
->isMicroop() ||
659 curStaticInst
->isFirstMicroop()))
663 advanceInst(NoFault
);
673 TimingSimpleCPU::IcachePort::ITickEvent::process()
675 cpu
->completeIfetch(pkt
);
679 TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt
)
681 if (pkt
->isResponse() && !pkt
->wasNacked()) {
682 // delay processing of returned data until next CPU clock edge
683 Tick next_tick
= cpu
->nextCycle(curTick
);
685 if (next_tick
== curTick
)
686 cpu
->completeIfetch(pkt
);
688 tickEvent
.schedule(pkt
, next_tick
);
692 else if (pkt
->wasNacked()) {
693 assert(cpu
->_status
== IcacheWaitResponse
);
695 if (!sendTiming(pkt
)) {
696 cpu
->_status
= IcacheRetry
;
697 cpu
->ifetch_pkt
= pkt
;
700 //Snooping a Coherence Request, do nothing
705 TimingSimpleCPU::IcachePort::recvRetry()
707 // we shouldn't get a retry unless we have a packet that we're
708 // waiting to transmit
709 assert(cpu
->ifetch_pkt
!= NULL
);
710 assert(cpu
->_status
== IcacheRetry
);
711 PacketPtr tmp
= cpu
->ifetch_pkt
;
712 if (sendTiming(tmp
)) {
713 cpu
->_status
= IcacheWaitResponse
;
714 cpu
->ifetch_pkt
= NULL
;
719 TimingSimpleCPU::completeDataAccess(PacketPtr pkt
)
721 // received a response from the dcache: complete the load or store
723 assert(!pkt
->isError());
724 assert(_status
== DcacheWaitResponse
);
727 numCycles
+= tickToCycles(curTick
- previousTick
);
728 previousTick
= curTick
;
730 Fault fault
= curStaticInst
->completeAcc(pkt
, this, traceData
);
732 // keep an instruction count
733 if (fault
== NoFault
)
735 else if (traceData
) {
736 // If there was a fault, we shouldn't trace this instruction.
741 // the locked flag may be cleared on the response packet, so check
742 // pkt->req and not pkt to see if it was a load-locked
743 if (pkt
->isRead() && pkt
->req
->isLocked()) {
744 TheISA::handleLockedRead(thread
, pkt
->req
);
752 if (getState() == SimObject::Draining
) {
764 TimingSimpleCPU::completeDrain()
766 DPRINTF(Config
, "Done draining\n");
767 changeState(SimObject::Drained
);
768 drainEvent
->process();
772 TimingSimpleCPU::DcachePort::setPeer(Port
*port
)
777 // Update the ThreadContext's memory ports (Functional/Virtual
779 cpu
->tcBase()->connectMemPorts(cpu
->tcBase());
784 TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt
)
786 if (pkt
->isResponse() && !pkt
->wasNacked()) {
787 // delay processing of returned data until next CPU clock edge
788 Tick next_tick
= cpu
->nextCycle(curTick
);
790 if (next_tick
== curTick
)
791 cpu
->completeDataAccess(pkt
);
793 tickEvent
.schedule(pkt
, next_tick
);
797 else if (pkt
->wasNacked()) {
798 assert(cpu
->_status
== DcacheWaitResponse
);
800 if (!sendTiming(pkt
)) {
801 cpu
->_status
= DcacheRetry
;
802 cpu
->dcache_pkt
= pkt
;
805 //Snooping a Coherence Request, do nothing
810 TimingSimpleCPU::DcachePort::DTickEvent::process()
812 cpu
->completeDataAccess(pkt
);
816 TimingSimpleCPU::DcachePort::recvRetry()
818 // we shouldn't get a retry unless we have a packet that we're
819 // waiting to transmit
820 assert(cpu
->dcache_pkt
!= NULL
);
821 assert(cpu
->_status
== DcacheRetry
);
822 PacketPtr tmp
= cpu
->dcache_pkt
;
823 if (sendTiming(tmp
)) {
824 cpu
->_status
= DcacheWaitResponse
;
825 // memory system takes ownership of packet
826 cpu
->dcache_pkt
= NULL
;
830 TimingSimpleCPU::IprEvent::IprEvent(Packet
*_pkt
, TimingSimpleCPU
*_cpu
,
832 : pkt(_pkt
), cpu(_cpu
)
834 cpu
->schedule(this, t
);
838 TimingSimpleCPU::IprEvent::process()
840 cpu
->completeDataAccess(pkt
);
844 TimingSimpleCPU::IprEvent::description() const
846 return "Timing Simple CPU Delay IPR event";
851 TimingSimpleCPU::printAddr(Addr a
)
853 dcachePort
.printAddr(a
);
857 ////////////////////////////////////////////////////////////////////////
859 // TimingSimpleCPU Simulation Object
862 TimingSimpleCPUParams::create()
866 if (workload
.size() != 1)
867 panic("only one workload allowed");
869 return new TimingSimpleCPU(this);