2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
31 #include "arch/locked_mem.hh"
32 #include "arch/mmaped_ipr.hh"
33 #include "arch/utility.hh"
34 #include "base/bigint.hh"
35 #include "cpu/exetrace.hh"
36 #include "cpu/simple/timing.hh"
37 #include "mem/packet.hh"
38 #include "mem/packet_access.hh"
39 #include "params/TimingSimpleCPU.hh"
40 #include "sim/system.hh"
43 using namespace TheISA
;
46 TimingSimpleCPU::getPort(const std::string
&if_name
, int idx
)
48 if (if_name
== "dcache_port")
50 else if (if_name
== "icache_port")
53 panic("No Such Port\n");
57 TimingSimpleCPU::init()
61 for (int i
= 0; i
< threadContexts
.size(); ++i
) {
62 ThreadContext
*tc
= threadContexts
[i
];
64 // initialize CPU, including PC
65 TheISA::initCPU(tc
, tc
->readCpuId());
71 TimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt
)
73 panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
78 TimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt
)
80 //No internal storage to update, jusst return
85 TimingSimpleCPU::CpuPort::recvStatusChange(Status status
)
87 if (status
== RangeChange
) {
88 if (!snoopRangeSent
) {
89 snoopRangeSent
= true;
90 sendStatusChange(Port::RangeChange
);
95 panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
100 TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt
, Tick t
)
106 TimingSimpleCPU::TimingSimpleCPU(Params
*p
)
107 : BaseSimpleCPU(p
), icachePort(this, p
->clock
), dcachePort(this, p
->clock
)
111 icachePort
.snoopRangeSent
= false;
112 dcachePort
.snoopRangeSent
= false;
114 ifetch_pkt
= dcache_pkt
= NULL
;
118 changeState(SimObject::Running
);
122 TimingSimpleCPU::~TimingSimpleCPU()
127 TimingSimpleCPU::serialize(ostream
&os
)
129 SimObject::State so_state
= SimObject::getState();
130 SERIALIZE_ENUM(so_state
);
131 BaseSimpleCPU::serialize(os
);
135 TimingSimpleCPU::unserialize(Checkpoint
*cp
, const string
§ion
)
137 SimObject::State so_state
;
138 UNSERIALIZE_ENUM(so_state
);
139 BaseSimpleCPU::unserialize(cp
, section
);
143 TimingSimpleCPU::drain(Event
*drain_event
)
145 // TimingSimpleCPU is ready to drain if it's not waiting for
146 // an access to complete.
147 if (status() == Idle
|| status() == Running
|| status() == SwitchedOut
) {
148 changeState(SimObject::Drained
);
151 changeState(SimObject::Draining
);
152 drainEvent
= drain_event
;
158 TimingSimpleCPU::resume()
160 if (_status
!= SwitchedOut
&& _status
!= Idle
) {
161 assert(system
->getMemoryMode() == Enums::timing
);
163 // Delete the old event if it existed.
165 if (fetchEvent
->scheduled())
166 fetchEvent
->deschedule();
171 fetchEvent
= new FetchEvent(this, nextCycle());
174 changeState(SimObject::Running
);
178 TimingSimpleCPU::switchOut()
180 assert(status() == Running
|| status() == Idle
);
181 _status
= SwitchedOut
;
182 numCycles
+= tickToCycles(curTick
- previousTick
);
184 // If we've been scheduled to resume but are then told to switch out,
185 // we'll need to cancel it.
186 if (fetchEvent
&& fetchEvent
->scheduled())
187 fetchEvent
->deschedule();
192 TimingSimpleCPU::takeOverFrom(BaseCPU
*oldCPU
)
194 BaseCPU::takeOverFrom(oldCPU
, &icachePort
, &dcachePort
);
196 // if any of this CPU's ThreadContexts are active, mark the CPU as
197 // running and schedule its tick event.
198 for (int i
= 0; i
< threadContexts
.size(); ++i
) {
199 ThreadContext
*tc
= threadContexts
[i
];
200 if (tc
->status() == ThreadContext::Active
&& _status
!= Running
) {
206 if (_status
!= Running
) {
209 assert(threadContexts
.size() == 1);
210 cpuId
= tc
->readCpuId();
211 previousTick
= curTick
;
216 TimingSimpleCPU::activateContext(int thread_num
, int delay
)
218 assert(thread_num
== 0);
221 assert(_status
== Idle
);
226 // kick things off by initiating the fetch of the next instruction
227 fetchEvent
= new FetchEvent(this, nextCycle(curTick
+ ticks(delay
)));
232 TimingSimpleCPU::suspendContext(int thread_num
)
234 assert(thread_num
== 0);
237 assert(_status
== Running
);
239 // just change status to Idle... if status != Running,
240 // completeInst() will not initiate fetch of next instruction.
249 TimingSimpleCPU::read(Addr addr
, T
&data
, unsigned flags
)
252 new Request(/* asid */ 0, addr
, sizeof(T
), flags
, thread
->readPC(),
253 cpuId
, /* thread ID */ 0);
256 traceData
->setAddr(req
->getVaddr());
259 // translate to physical address
260 Fault fault
= thread
->translateDataReadReq(req
);
262 // Now do the access.
263 if (fault
== NoFault
) {
267 MemCmd::LoadLockedReq
: MemCmd::ReadReq
),
269 pkt
->dataDynamic
<T
>(new T
);
271 if (req
->isMmapedIpr()) {
273 delay
= TheISA::handleIprRead(thread
->getTC(), pkt
);
274 new IprEvent(pkt
, this, nextCycle(curTick
+ delay
));
275 _status
= DcacheWaitResponse
;
277 } else if (!dcachePort
.sendTiming(pkt
)) {
278 _status
= DcacheRetry
;
281 _status
= DcacheWaitResponse
;
282 // memory system takes ownership of packet
286 // This will need a new way to tell if it has a dcache attached.
287 if (req
->isUncacheable())
288 recordEvent("Uncached Read");
297 TimingSimpleCPU::translateDataReadAddr(Addr vaddr
, Addr
&paddr
,
298 int size
, unsigned flags
)
301 new Request(0, vaddr
, size
, flags
, thread
->readPC(), cpuId
, 0);
304 traceData
->setAddr(vaddr
);
307 Fault fault
= thread
->translateDataWriteReq(req
);
309 if (fault
== NoFault
)
310 paddr
= req
->getPaddr();
316 #ifndef DOXYGEN_SHOULD_SKIP_THIS
320 TimingSimpleCPU::read(Addr addr
, Twin64_t
&data
, unsigned flags
);
324 TimingSimpleCPU::read(Addr addr
, Twin32_t
&data
, unsigned flags
);
328 TimingSimpleCPU::read(Addr addr
, uint64_t &data
, unsigned flags
);
332 TimingSimpleCPU::read(Addr addr
, uint32_t &data
, unsigned flags
);
336 TimingSimpleCPU::read(Addr addr
, uint16_t &data
, unsigned flags
);
340 TimingSimpleCPU::read(Addr addr
, uint8_t &data
, unsigned flags
);
342 #endif //DOXYGEN_SHOULD_SKIP_THIS
346 TimingSimpleCPU::read(Addr addr
, double &data
, unsigned flags
)
348 return read(addr
, *(uint64_t*)&data
, flags
);
353 TimingSimpleCPU::read(Addr addr
, float &data
, unsigned flags
)
355 return read(addr
, *(uint32_t*)&data
, flags
);
361 TimingSimpleCPU::read(Addr addr
, int32_t &data
, unsigned flags
)
363 return read(addr
, (uint32_t&)data
, flags
);
369 TimingSimpleCPU::write(T data
, Addr addr
, unsigned flags
, uint64_t *res
)
372 new Request(/* asid */ 0, addr
, sizeof(T
), flags
, thread
->readPC(),
373 cpuId
, /* thread ID */ 0);
376 traceData
->setAddr(req
->getVaddr());
379 // translate to physical address
380 Fault fault
= thread
->translateDataWriteReq(req
);
382 // Now do the access.
383 if (fault
== NoFault
) {
384 MemCmd cmd
= MemCmd::WriteReq
; // default
385 bool do_access
= true; // flag to suppress cache access
387 if (req
->isLocked()) {
388 cmd
= MemCmd::StoreCondReq
;
389 do_access
= TheISA::handleLockedWrite(thread
, req
);
390 } else if (req
->isSwap()) {
391 cmd
= MemCmd::SwapReq
;
392 if (req
->isCondSwap()) {
394 req
->setExtraData(*res
);
398 // Note: need to allocate dcache_pkt even if do_access is
399 // false, as it's used unconditionally to call completeAcc().
400 assert(dcache_pkt
== NULL
);
401 dcache_pkt
= new Packet(req
, cmd
, Packet::Broadcast
);
402 dcache_pkt
->allocate();
403 dcache_pkt
->set(data
);
406 if (req
->isMmapedIpr()) {
408 dcache_pkt
->set(htog(data
));
409 delay
= TheISA::handleIprWrite(thread
->getTC(), dcache_pkt
);
410 new IprEvent(dcache_pkt
, this, nextCycle(curTick
+ delay
));
411 _status
= DcacheWaitResponse
;
413 } else if (!dcachePort
.sendTiming(dcache_pkt
)) {
414 _status
= DcacheRetry
;
416 _status
= DcacheWaitResponse
;
417 // memory system takes ownership of packet
421 // This will need a new way to tell if it's hooked up to a cache or not.
422 if (req
->isUncacheable())
423 recordEvent("Uncached Write");
429 // If the write needs to have a fault on the access, consider calling
430 // changeStatus() and changing it to "bad addr write" or something.
435 TimingSimpleCPU::translateDataWriteAddr(Addr vaddr
, Addr
&paddr
,
436 int size
, unsigned flags
)
439 new Request(0, vaddr
, size
, flags
, thread
->readPC(), cpuId
, 0);
442 traceData
->setAddr(vaddr
);
445 Fault fault
= thread
->translateDataWriteReq(req
);
447 if (fault
== NoFault
)
448 paddr
= req
->getPaddr();
455 #ifndef DOXYGEN_SHOULD_SKIP_THIS
458 TimingSimpleCPU::write(Twin32_t data
, Addr addr
,
459 unsigned flags
, uint64_t *res
);
463 TimingSimpleCPU::write(Twin64_t data
, Addr addr
,
464 unsigned flags
, uint64_t *res
);
468 TimingSimpleCPU::write(uint64_t data
, Addr addr
,
469 unsigned flags
, uint64_t *res
);
473 TimingSimpleCPU::write(uint32_t data
, Addr addr
,
474 unsigned flags
, uint64_t *res
);
478 TimingSimpleCPU::write(uint16_t data
, Addr addr
,
479 unsigned flags
, uint64_t *res
);
483 TimingSimpleCPU::write(uint8_t data
, Addr addr
,
484 unsigned flags
, uint64_t *res
);
486 #endif //DOXYGEN_SHOULD_SKIP_THIS
490 TimingSimpleCPU::write(double data
, Addr addr
, unsigned flags
, uint64_t *res
)
492 return write(*(uint64_t*)&data
, addr
, flags
, res
);
497 TimingSimpleCPU::write(float data
, Addr addr
, unsigned flags
, uint64_t *res
)
499 return write(*(uint32_t*)&data
, addr
, flags
, res
);
505 TimingSimpleCPU::write(int32_t data
, Addr addr
, unsigned flags
, uint64_t *res
)
507 return write((uint32_t)data
, addr
, flags
, res
);
512 TimingSimpleCPU::fetch()
514 if (!curStaticInst
|| !curStaticInst
->isDelayedCommit())
515 checkForInterrupts();
517 Request
*ifetch_req
= new Request();
518 ifetch_req
->setThreadContext(cpuId
, /* thread ID */ 0);
519 Fault fault
= setupFetchRequest(ifetch_req
);
521 ifetch_pkt
= new Packet(ifetch_req
, MemCmd::ReadReq
, Packet::Broadcast
);
522 ifetch_pkt
->dataStatic(&inst
);
524 if (fault
== NoFault
) {
525 if (!icachePort
.sendTiming(ifetch_pkt
)) {
526 // Need to wait for retry
527 _status
= IcacheRetry
;
529 // Need to wait for cache to respond
530 _status
= IcacheWaitResponse
;
531 // ownership of packet transferred to memory system
537 // fetch fault: advance directly to next instruction (fault handler)
541 numCycles
+= tickToCycles(curTick
- previousTick
);
542 previousTick
= curTick
;
547 TimingSimpleCPU::advanceInst(Fault fault
)
551 if (_status
== Running
) {
552 // kick off fetch of next instruction... callback from icache
553 // response will cause that instruction to be executed,
554 // keeping the CPU running.
561 TimingSimpleCPU::completeIfetch(PacketPtr pkt
)
563 // received a response from the icache: execute the received
565 assert(!pkt
->isError());
566 assert(_status
== IcacheWaitResponse
);
570 numCycles
+= tickToCycles(curTick
- previousTick
);
571 previousTick
= curTick
;
573 if (getState() == SimObject::Draining
) {
582 if (curStaticInst
->isMemRef() && !curStaticInst
->isDataPrefetch()) {
583 // load or store: just send to dcache
584 Fault fault
= curStaticInst
->initiateAcc(this, traceData
);
585 if (_status
!= Running
) {
586 // instruction will complete in dcache response callback
587 assert(_status
== DcacheWaitResponse
|| _status
== DcacheRetry
);
588 assert(fault
== NoFault
);
590 if (fault
== NoFault
) {
591 // early fail on store conditional: complete now
592 assert(dcache_pkt
!= NULL
);
593 fault
= curStaticInst
->completeAcc(dcache_pkt
, this,
595 delete dcache_pkt
->req
;
599 // keep an instruction count
600 if (fault
== NoFault
)
602 } else if (traceData
) {
603 // If there was a fault, we shouldn't trace this instruction.
609 // @todo remove me after debugging with legion done
610 if (curStaticInst
&& (!curStaticInst
->isMicroop() ||
611 curStaticInst
->isFirstMicroop()))
616 // non-memory instruction: execute completely now
617 Fault fault
= curStaticInst
->execute(this, traceData
);
619 // keep an instruction count
620 if (fault
== NoFault
)
622 else if (traceData
) {
623 // If there was a fault, we shouldn't trace this instruction.
629 // @todo remove me after debugging with legion done
630 if (curStaticInst
&& (!curStaticInst
->isMicroop() ||
631 curStaticInst
->isFirstMicroop()))
641 TimingSimpleCPU::IcachePort::ITickEvent::process()
643 cpu
->completeIfetch(pkt
);
647 TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt
)
649 if (pkt
->isResponse() && !pkt
->wasNacked()) {
650 // delay processing of returned data until next CPU clock edge
651 Tick next_tick
= cpu
->nextCycle(curTick
);
653 if (next_tick
== curTick
)
654 cpu
->completeIfetch(pkt
);
656 tickEvent
.schedule(pkt
, next_tick
);
660 else if (pkt
->wasNacked()) {
661 assert(cpu
->_status
== IcacheWaitResponse
);
663 if (!sendTiming(pkt
)) {
664 cpu
->_status
= IcacheRetry
;
665 cpu
->ifetch_pkt
= pkt
;
668 //Snooping a Coherence Request, do nothing
673 TimingSimpleCPU::IcachePort::recvRetry()
675 // we shouldn't get a retry unless we have a packet that we're
676 // waiting to transmit
677 assert(cpu
->ifetch_pkt
!= NULL
);
678 assert(cpu
->_status
== IcacheRetry
);
679 PacketPtr tmp
= cpu
->ifetch_pkt
;
680 if (sendTiming(tmp
)) {
681 cpu
->_status
= IcacheWaitResponse
;
682 cpu
->ifetch_pkt
= NULL
;
687 TimingSimpleCPU::completeDataAccess(PacketPtr pkt
)
689 // received a response from the dcache: complete the load or store
691 assert(!pkt
->isError());
692 assert(_status
== DcacheWaitResponse
);
695 numCycles
+= tickToCycles(curTick
- previousTick
);
696 previousTick
= curTick
;
698 Fault fault
= curStaticInst
->completeAcc(pkt
, this, traceData
);
700 // keep an instruction count
701 if (fault
== NoFault
)
703 else if (traceData
) {
704 // If there was a fault, we shouldn't trace this instruction.
709 if (pkt
->isRead() && pkt
->isLocked()) {
710 TheISA::handleLockedRead(thread
, pkt
->req
);
718 if (getState() == SimObject::Draining
) {
730 TimingSimpleCPU::completeDrain()
732 DPRINTF(Config
, "Done draining\n");
733 changeState(SimObject::Drained
);
734 drainEvent
->process();
738 TimingSimpleCPU::DcachePort::setPeer(Port
*port
)
743 // Update the ThreadContext's memory ports (Functional/Virtual
745 cpu
->tcBase()->connectMemPorts();
750 TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt
)
752 if (pkt
->isResponse() && !pkt
->wasNacked()) {
753 // delay processing of returned data until next CPU clock edge
754 Tick next_tick
= cpu
->nextCycle(curTick
);
756 if (next_tick
== curTick
)
757 cpu
->completeDataAccess(pkt
);
759 tickEvent
.schedule(pkt
, next_tick
);
763 else if (pkt
->wasNacked()) {
764 assert(cpu
->_status
== DcacheWaitResponse
);
766 if (!sendTiming(pkt
)) {
767 cpu
->_status
= DcacheRetry
;
768 cpu
->dcache_pkt
= pkt
;
771 //Snooping a Coherence Request, do nothing
776 TimingSimpleCPU::DcachePort::DTickEvent::process()
778 cpu
->completeDataAccess(pkt
);
782 TimingSimpleCPU::DcachePort::recvRetry()
784 // we shouldn't get a retry unless we have a packet that we're
785 // waiting to transmit
786 assert(cpu
->dcache_pkt
!= NULL
);
787 assert(cpu
->_status
== DcacheRetry
);
788 PacketPtr tmp
= cpu
->dcache_pkt
;
789 if (sendTiming(tmp
)) {
790 cpu
->_status
= DcacheWaitResponse
;
791 // memory system takes ownership of packet
792 cpu
->dcache_pkt
= NULL
;
796 TimingSimpleCPU::IprEvent::IprEvent(Packet
*_pkt
, TimingSimpleCPU
*_cpu
, Tick t
)
797 : Event(&mainEventQueue
), pkt(_pkt
), cpu(_cpu
)
803 TimingSimpleCPU::IprEvent::process()
805 cpu
->completeDataAccess(pkt
);
809 TimingSimpleCPU::IprEvent::description()
811 return "Timing Simple CPU Delay IPR event";
815 ////////////////////////////////////////////////////////////////////////
817 // TimingSimpleCPU Simulation Object
820 TimingSimpleCPUParams::create()
822 TimingSimpleCPU::Params
*params
= new TimingSimpleCPU::Params();
824 params
->numberOfThreads
= 1;
825 params
->max_insts_any_thread
= max_insts_any_thread
;
826 params
->max_insts_all_threads
= max_insts_all_threads
;
827 params
->max_loads_any_thread
= max_loads_any_thread
;
828 params
->max_loads_all_threads
= max_loads_all_threads
;
829 params
->progress_interval
= progress_interval
;
830 params
->deferRegistration
= defer_registration
;
831 params
->clock
= clock
;
832 params
->phase
= phase
;
833 params
->functionTrace
= function_trace
;
834 params
->functionTraceStart
= function_trace_start
;
835 params
->system
= system
;
836 params
->cpu_id
= cpu_id
;
837 params
->tracer
= tracer
;
842 params
->profile
= profile
;
843 params
->do_quiesce
= do_quiesce
;
844 params
->do_checkpoint_insts
= do_checkpoint_insts
;
845 params
->do_statistics_insts
= do_statistics_insts
;
847 if (workload
.size() != 1)
848 panic("only one workload allowed");
849 params
->process
= workload
[0];
852 TimingSimpleCPU
*cpu
= new TimingSimpleCPU(params
);