src/cpu/simple/timing.cc

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  */
  30
  31 #include "arch/utility.hh"
  32 #include "cpu/exetrace.hh"
  33 #include "cpu/simple/timing.hh"
  34 #include "mem/packet_impl.hh"
  35 #include "sim/builder.hh"
  36
  37 using namespace std;
  38 using namespace TheISA;
  39
  40
  41 void
  42 TimingSimpleCPU::init()
  43 {
  44     //Create Memory Ports (conect them up)
  45     Port *mem_dport = mem->getPort("");
  46     dcachePort.setPeer(mem_dport);
  47     mem_dport->setPeer(&dcachePort);
  48
  49     Port *mem_iport = mem->getPort("");
  50     icachePort.setPeer(mem_iport);
  51     mem_iport->setPeer(&icachePort);
  52
  53     BaseCPU::init();
  54 #if FULL_SYSTEM
  55     for (int i = 0; i < threadContexts.size(); ++i) {
  56         ThreadContext *tc = threadContexts[i];
  57
  58         // initialize CPU, including PC
  59         TheISA::initCPU(tc, tc->readCpuId());
  60     }
  61 #endif
  62 }
  63
  64 Tick
  65 TimingSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
  66 {
  67     panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
  68     return curTick;
  69 }
  70
  71 void
  72 TimingSimpleCPU::CpuPort::recvFunctional(Packet *pkt)
  73 {
  74     panic("TimingSimpleCPU doesn't expect recvFunctional callback!");
  75 }
  76
  77 void
  78 TimingSimpleCPU::CpuPort::recvStatusChange(Status status)
  79 {
  80     if (status == RangeChange)
  81         return;
  82
  83     panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
  84 }
  85
  86 TimingSimpleCPU::TimingSimpleCPU(Params *p)
  87     : BaseSimpleCPU(p), icachePort(this), dcachePort(this)
  88 {
  89     _status = Idle;
  90     ifetch_pkt = dcache_pkt = NULL;
  91     drainEvent = NULL;
  92     state = SimObject::Timing;
  93 }
  94
  95
  96 TimingSimpleCPU::~TimingSimpleCPU()
  97 {
  98 }
  99
 100 void
 101 TimingSimpleCPU::serialize(ostream &os)
 102 {
 103     SERIALIZE_ENUM(_status);
 104     BaseSimpleCPU::serialize(os);
 105 }
 106
 107 void
 108 TimingSimpleCPU::unserialize(Checkpoint *cp, const string &section)
 109 {
 110     UNSERIALIZE_ENUM(_status);
 111     BaseSimpleCPU::unserialize(cp, section);
 112 }
 113
 114 bool
 115 TimingSimpleCPU::drain(Event *drain_event)
 116 {
 117     // TimingSimpleCPU is ready to drain if it's not waiting for
 118     // an access to complete.
 119     if (status() == Idle || status() == Running || status() == SwitchedOut) {
 120         changeState(SimObject::DrainedTiming);
 121         return false;
 122     } else {
 123         changeState(SimObject::Draining);
 124         drainEvent = drain_event;
 125         return true;
 126     }
 127 }
 128
 129 void
 130 TimingSimpleCPU::resume()
 131 {
 132     if (_status != SwitchedOut && _status != Idle) {
 133         Event *e =
 134             new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, true);
 135         e->schedule(curTick);
 136     }
 137 }
 138
 139 void
 140 TimingSimpleCPU::setMemoryMode(State new_mode)
 141 {
 142     assert(new_mode == SimObject::Timing);
 143 }
 144
 145 void
 146 TimingSimpleCPU::switchOut()
 147 {
 148     assert(status() == Running || status() == Idle);
 149     _status = SwitchedOut;
 150 }
 151
 152
 153 void
 154 TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
 155 {
 156     BaseCPU::takeOverFrom(oldCPU);
 157
 158     // if any of this CPU's ThreadContexts are active, mark the CPU as
 159     // running and schedule its tick event.
 160     for (int i = 0; i < threadContexts.size(); ++i) {
 161         ThreadContext *tc = threadContexts[i];
 162         if (tc->status() == ThreadContext::Active && _status != Running) {
 163             _status = Running;
 164             break;
 165         }
 166     }
 167 }
 168
 169
 170 void
 171 TimingSimpleCPU::activateContext(int thread_num, int delay)
 172 {
 173     assert(thread_num == 0);
 174     assert(thread);
 175
 176     assert(_status == Idle);
 177
 178     notIdleFraction++;
 179     _status = Running;
 180     // kick things off by initiating the fetch of the next instruction
 181     Event *e =
 182         new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, true);
 183     e->schedule(curTick + cycles(delay));
 184 }
 185
 186
 187 void
 188 TimingSimpleCPU::suspendContext(int thread_num)
 189 {
 190     assert(thread_num == 0);
 191     assert(thread);
 192
 193     assert(_status == Running);
 194
 195     // just change status to Idle... if status != Running,
 196     // completeInst() will not initiate fetch of next instruction.
 197
 198     notIdleFraction--;
 199     _status = Idle;
 200 }
 201
 202
 203 template <class T>
 204 Fault
 205 TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
 206 {
 207     // need to fill in CPU & thread IDs here
 208     Request *data_read_req = new Request();
 209     data_read_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
 210     data_read_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
 211
 212     if (traceData) {
 213         traceData->setAddr(data_read_req->getVaddr());
 214     }
 215
 216    // translate to physical address
 217     Fault fault = thread->translateDataReadReq(data_read_req);
 218
 219     // Now do the access.
 220     if (fault == NoFault) {
 221         Packet *data_read_pkt =
 222             new Packet(data_read_req, Packet::ReadReq, Packet::Broadcast);
 223         data_read_pkt->dataDynamic<T>(new T);
 224
 225         if (!dcachePort.sendTiming(data_read_pkt)) {
 226             _status = DcacheRetry;
 227             dcache_pkt = data_read_pkt;
 228         } else {
 229             _status = DcacheWaitResponse;
 230             dcache_pkt = NULL;
 231         }
 232     }
 233
 234     // This will need a new way to tell if it has a dcache attached.
 235     if (data_read_req->getFlags() & UNCACHEABLE)
 236         recordEvent("Uncached Read");
 237
 238     return fault;
 239 }
 240
 241 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 242
 243 template
 244 Fault
 245 TimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
 246
 247 template
 248 Fault
 249 TimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
 250
 251 template
 252 Fault
 253 TimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
 254
 255 template
 256 Fault
 257 TimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
 258
 259 #endif //DOXYGEN_SHOULD_SKIP_THIS
 260
 261 template<>
 262 Fault
 263 TimingSimpleCPU::read(Addr addr, double &data, unsigned flags)
 264 {
 265     return read(addr, *(uint64_t*)&data, flags);
 266 }
 267
 268 template<>
 269 Fault
 270 TimingSimpleCPU::read(Addr addr, float &data, unsigned flags)
 271 {
 272     return read(addr, *(uint32_t*)&data, flags);
 273 }
 274
 275
 276 template<>
 277 Fault
 278 TimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
 279 {
 280     return read(addr, (uint32_t&)data, flags);
 281 }
 282
 283
 284 template <class T>
 285 Fault
 286 TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
 287 {
 288     // need to fill in CPU & thread IDs here
 289     Request *data_write_req = new Request();
 290     data_write_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
 291     data_write_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
 292
 293     // translate to physical address
 294     Fault fault = thread->translateDataWriteReq(data_write_req);
 295     // Now do the access.
 296     if (fault == NoFault) {
 297         Packet *data_write_pkt =
 298             new Packet(data_write_req, Packet::WriteReq, Packet::Broadcast);
 299         data_write_pkt->allocate();
 300         data_write_pkt->set(data);
 301
 302         if (!dcachePort.sendTiming(data_write_pkt)) {
 303             _status = DcacheRetry;
 304             dcache_pkt = data_write_pkt;
 305         } else {
 306             _status = DcacheWaitResponse;
 307             dcache_pkt = NULL;
 308         }
 309     }
 310
 311     // This will need a new way to tell if it's hooked up to a cache or not.
 312     if (data_write_req->getFlags() & UNCACHEABLE)
 313         recordEvent("Uncached Write");
 314
 315     // If the write needs to have a fault on the access, consider calling
 316     // changeStatus() and changing it to "bad addr write" or something.
 317     return fault;
 318 }
 319
 320
 321 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 322 template
 323 Fault
 324 TimingSimpleCPU::write(uint64_t data, Addr addr,
 325                        unsigned flags, uint64_t *res);
 326
 327 template
 328 Fault
 329 TimingSimpleCPU::write(uint32_t data, Addr addr,
 330                        unsigned flags, uint64_t *res);
 331
 332 template
 333 Fault
 334 TimingSimpleCPU::write(uint16_t data, Addr addr,
 335                        unsigned flags, uint64_t *res);
 336
 337 template
 338 Fault
 339 TimingSimpleCPU::write(uint8_t data, Addr addr,
 340                        unsigned flags, uint64_t *res);
 341
 342 #endif //DOXYGEN_SHOULD_SKIP_THIS
 343
 344 template<>
 345 Fault
 346 TimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
 347 {
 348     return write(*(uint64_t*)&data, addr, flags, res);
 349 }
 350
 351 template<>
 352 Fault
 353 TimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
 354 {
 355     return write(*(uint32_t*)&data, addr, flags, res);
 356 }
 357
 358
 359 template<>
 360 Fault
 361 TimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
 362 {
 363     return write((uint32_t)data, addr, flags, res);
 364 }
 365
 366
 367 void
 368 TimingSimpleCPU::fetch()
 369 {
 370     checkForInterrupts();
 371
 372     // need to fill in CPU & thread IDs here
 373     Request *ifetch_req = new Request();
 374     ifetch_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
 375     Fault fault = setupFetchRequest(ifetch_req);
 376
 377     ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
 378     ifetch_pkt->dataStatic(&inst);
 379
 380     if (fault == NoFault) {
 381         if (!icachePort.sendTiming(ifetch_pkt)) {
 382             // Need to wait for retry
 383             _status = IcacheRetry;
 384         } else {
 385             // Need to wait for cache to respond
 386             _status = IcacheWaitResponse;
 387             // ownership of packet transferred to memory system
 388             ifetch_pkt = NULL;
 389         }
 390     } else {
 391         // fetch fault: advance directly to next instruction (fault handler)
 392         advanceInst(fault);
 393     }
 394 }
 395
 396
 397 void
 398 TimingSimpleCPU::advanceInst(Fault fault)
 399 {
 400     advancePC(fault);
 401
 402     if (_status == Running) {
 403         // kick off fetch of next instruction... callback from icache
 404         // response will cause that instruction to be executed,
 405         // keeping the CPU running.
 406         fetch();
 407     }
 408 }
 409
 410
 411 void
 412 TimingSimpleCPU::completeIfetch(Packet *pkt)
 413 {
 414     // received a response from the icache: execute the received
 415     // instruction
 416     assert(pkt->result == Packet::Success);
 417     assert(_status == IcacheWaitResponse);
 418
 419     _status = Running;
 420
 421     delete pkt->req;
 422     delete pkt;
 423
 424     if (getState() == SimObject::Draining) {
 425         completeDrain();
 426         return;
 427     }
 428
 429     preExecute();
 430     if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) {
 431         // load or store: just send to dcache
 432         Fault fault = curStaticInst->initiateAcc(this, traceData);
 433         if (fault == NoFault) {
 434             // successfully initiated access: instruction will
 435             // complete in dcache response callback
 436             assert(_status == DcacheWaitResponse);
 437         } else {
 438             // fault: complete now to invoke fault handler
 439             postExecute();
 440             advanceInst(fault);
 441         }
 442     } else {
 443         // non-memory instruction: execute completely now
 444         Fault fault = curStaticInst->execute(this, traceData);
 445         postExecute();
 446         advanceInst(fault);
 447     }
 448 }
 449
 450
 451 bool
 452 TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
 453 {
 454     cpu->completeIfetch(pkt);
 455     return true;
 456 }
 457
 458 void
 459 TimingSimpleCPU::IcachePort::recvRetry()
 460 {
 461     // we shouldn't get a retry unless we have a packet that we're
 462     // waiting to transmit
 463     assert(cpu->ifetch_pkt != NULL);
 464     assert(cpu->_status == IcacheRetry);
 465     Packet *tmp = cpu->ifetch_pkt;
 466     if (sendTiming(tmp)) {
 467         cpu->_status = IcacheWaitResponse;
 468         cpu->ifetch_pkt = NULL;
 469     }
 470 }
 471
 472 void
 473 TimingSimpleCPU::completeDataAccess(Packet *pkt)
 474 {
 475     // received a response from the dcache: complete the load or store
 476     // instruction
 477     assert(pkt->result == Packet::Success);
 478     assert(_status == DcacheWaitResponse);
 479     _status = Running;
 480
 481     if (getState() == SimObject::Draining) {
 482         completeDrain();
 483
 484         delete pkt->req;
 485         delete pkt;
 486
 487         return;
 488     }
 489
 490     Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
 491
 492     delete pkt->req;
 493     delete pkt;
 494
 495     postExecute();
 496     advanceInst(fault);
 497 }
 498
 499
 500 void
 501 TimingSimpleCPU::completeDrain()
 502 {
 503     DPRINTF(Config, "Done draining\n");
 504     changeState(SimObject::DrainedTiming);
 505     drainEvent->process();
 506 }
 507
 508 bool
 509 TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt)
 510 {
 511     cpu->completeDataAccess(pkt);
 512     return true;
 513 }
 514
 515 void
 516 TimingSimpleCPU::DcachePort::recvRetry()
 517 {
 518     // we shouldn't get a retry unless we have a packet that we're
 519     // waiting to transmit
 520     assert(cpu->dcache_pkt != NULL);
 521     assert(cpu->_status == DcacheRetry);
 522     Packet *tmp = cpu->dcache_pkt;
 523     if (sendTiming(tmp)) {
 524         cpu->_status = DcacheWaitResponse;
 525         cpu->dcache_pkt = NULL;
 526     }
 527 }
 528
 529
 530 ////////////////////////////////////////////////////////////////////////
 531 //
 532 //  TimingSimpleCPU Simulation Object
 533 //
 534 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU)
 535
 536     Param<Counter> max_insts_any_thread;
 537     Param<Counter> max_insts_all_threads;
 538     Param<Counter> max_loads_any_thread;
 539     Param<Counter> max_loads_all_threads;
 540     SimObjectParam<MemObject *> mem;
 541
 542 #if FULL_SYSTEM
 543     SimObjectParam<AlphaITB *> itb;
 544     SimObjectParam<AlphaDTB *> dtb;
 545     SimObjectParam<System *> system;
 546     Param<int> cpu_id;
 547     Param<Tick> profile;
 548 #else
 549     SimObjectParam<Process *> workload;
 550 #endif // FULL_SYSTEM
 551
 552     Param<int> clock;
 553
 554     Param<bool> defer_registration;
 555     Param<int> width;
 556     Param<bool> function_trace;
 557     Param<Tick> function_trace_start;
 558     Param<bool> simulate_stalls;
 559
 560 END_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU)
 561
 562 BEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU)
 563
 564     INIT_PARAM(max_insts_any_thread,
 565                "terminate when any thread reaches this inst count"),
 566     INIT_PARAM(max_insts_all_threads,
 567                "terminate when all threads have reached this inst count"),
 568     INIT_PARAM(max_loads_any_thread,
 569                "terminate when any thread reaches this load count"),
 570     INIT_PARAM(max_loads_all_threads,
 571                "terminate when all threads have reached this load count"),
 572     INIT_PARAM(mem, "memory"),
 573
 574 #if FULL_SYSTEM
 575     INIT_PARAM(itb, "Instruction TLB"),
 576     INIT_PARAM(dtb, "Data TLB"),
 577     INIT_PARAM(system, "system object"),
 578     INIT_PARAM(cpu_id, "processor ID"),
 579     INIT_PARAM(profile, ""),
 580 #else
 581     INIT_PARAM(workload, "processes to run"),
 582 #endif // FULL_SYSTEM
 583
 584     INIT_PARAM(clock, "clock speed"),
 585     INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
 586     INIT_PARAM(width, "cpu width"),
 587     INIT_PARAM(function_trace, "Enable function trace"),
 588     INIT_PARAM(function_trace_start, "Cycle to start function trace"),
 589     INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
 590
 591 END_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU)
 592
 593
 594 CREATE_SIM_OBJECT(TimingSimpleCPU)
 595 {
 596     TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params();
 597     params->name = getInstanceName();
 598     params->numberOfThreads = 1;
 599     params->max_insts_any_thread = max_insts_any_thread;
 600     params->max_insts_all_threads = max_insts_all_threads;
 601     params->max_loads_any_thread = max_loads_any_thread;
 602     params->max_loads_all_threads = max_loads_all_threads;
 603     params->deferRegistration = defer_registration;
 604     params->clock = clock;
 605     params->functionTrace = function_trace;
 606     params->functionTraceStart = function_trace_start;
 607     params->mem = mem;
 608
 609 #if FULL_SYSTEM
 610     params->itb = itb;
 611     params->dtb = dtb;
 612     params->system = system;
 613     params->cpu_id = cpu_id;
 614     params->profile = profile;
 615 #else
 616     params->process = workload;
 617 #endif
 618
 619     TimingSimpleCPU *cpu = new TimingSimpleCPU(params);
 620     return cpu;
 621 }
 622
 623 REGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU)
 624