2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
31 #include "arch/locked_mem.hh"
32 #include "arch/utility.hh"
33 #include "base/bigint.hh"
34 #include "cpu/exetrace.hh"
35 #include "cpu/simple/timing.hh"
36 #include "mem/packet.hh"
37 #include "mem/packet_access.hh"
38 #include "params/TimingSimpleCPU.hh"
39 #include "sim/system.hh"
42 using namespace TheISA
;
45 TimingSimpleCPU::getPort(const std::string
&if_name
, int idx
)
47 if (if_name
== "dcache_port")
49 else if (if_name
== "icache_port")
52 panic("No Such Port\n");
56 TimingSimpleCPU::init()
60 for (int i
= 0; i
< threadContexts
.size(); ++i
) {
61 ThreadContext
*tc
= threadContexts
[i
];
63 // initialize CPU, including PC
64 TheISA::initCPU(tc
, tc
->readCpuId());
70 TimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt
)
72 panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
77 TimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt
)
79 //No internal storage to update, jusst return
84 TimingSimpleCPU::CpuPort::recvStatusChange(Status status
)
86 if (status
== RangeChange
) {
87 if (!snoopRangeSent
) {
88 snoopRangeSent
= true;
89 sendStatusChange(Port::RangeChange
);
94 panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
99 TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt
, Tick t
)
105 TimingSimpleCPU::TimingSimpleCPU(Params
*p
)
106 : BaseSimpleCPU(p
), icachePort(this, p
->clock
), dcachePort(this, p
->clock
),
111 icachePort
.snoopRangeSent
= false;
112 dcachePort
.snoopRangeSent
= false;
114 ifetch_pkt
= dcache_pkt
= NULL
;
118 changeState(SimObject::Running
);
122 TimingSimpleCPU::~TimingSimpleCPU()
127 TimingSimpleCPU::serialize(ostream
&os
)
129 SimObject::State so_state
= SimObject::getState();
130 SERIALIZE_ENUM(so_state
);
131 BaseSimpleCPU::serialize(os
);
135 TimingSimpleCPU::unserialize(Checkpoint
*cp
, const string
§ion
)
137 SimObject::State so_state
;
138 UNSERIALIZE_ENUM(so_state
);
139 BaseSimpleCPU::unserialize(cp
, section
);
143 TimingSimpleCPU::drain(Event
*drain_event
)
145 // TimingSimpleCPU is ready to drain if it's not waiting for
146 // an access to complete.
147 if (status() == Idle
|| status() == Running
|| status() == SwitchedOut
) {
148 changeState(SimObject::Drained
);
151 changeState(SimObject::Draining
);
152 drainEvent
= drain_event
;
158 TimingSimpleCPU::resume()
160 if (_status
!= SwitchedOut
&& _status
!= Idle
) {
161 assert(system
->getMemoryMode() == Enums::timing
);
163 // Delete the old event if it existed.
165 if (fetchEvent
->scheduled())
166 fetchEvent
->deschedule();
171 fetchEvent
= new FetchEvent(this, nextCycle());
174 changeState(SimObject::Running
);
175 previousTick
= curTick
;
179 TimingSimpleCPU::switchOut()
181 assert(status() == Running
|| status() == Idle
);
182 _status
= SwitchedOut
;
183 numCycles
+= curTick
- previousTick
;
185 // If we've been scheduled to resume but are then told to switch out,
186 // we'll need to cancel it.
187 if (fetchEvent
&& fetchEvent
->scheduled())
188 fetchEvent
->deschedule();
193 TimingSimpleCPU::takeOverFrom(BaseCPU
*oldCPU
)
195 BaseCPU::takeOverFrom(oldCPU
, &icachePort
, &dcachePort
);
197 // if any of this CPU's ThreadContexts are active, mark the CPU as
198 // running and schedule its tick event.
199 for (int i
= 0; i
< threadContexts
.size(); ++i
) {
200 ThreadContext
*tc
= threadContexts
[i
];
201 if (tc
->status() == ThreadContext::Active
&& _status
!= Running
) {
207 if (_status
!= Running
) {
214 TimingSimpleCPU::activateContext(int thread_num
, int delay
)
216 assert(thread_num
== 0);
219 assert(_status
== Idle
);
224 // kick things off by initiating the fetch of the next instruction
225 fetchEvent
= new FetchEvent(this, nextCycle(curTick
+ cycles(delay
)));
230 TimingSimpleCPU::suspendContext(int thread_num
)
232 assert(thread_num
== 0);
235 assert(_status
== Running
);
237 // just change status to Idle... if status != Running,
238 // completeInst() will not initiate fetch of next instruction.
247 TimingSimpleCPU::read(Addr addr
, T
&data
, unsigned flags
)
250 new Request(/* asid */ 0, addr
, sizeof(T
), flags
, thread
->readPC(),
251 cpu_id
, /* thread ID */ 0);
254 traceData
->setAddr(req
->getVaddr());
257 // translate to physical address
258 Fault fault
= thread
->translateDataReadReq(req
);
260 // Now do the access.
261 if (fault
== NoFault
) {
265 MemCmd::LoadLockedReq
: MemCmd::ReadReq
),
267 pkt
->dataDynamic
<T
>(new T
);
269 if (!dcachePort
.sendTiming(pkt
)) {
270 _status
= DcacheRetry
;
273 _status
= DcacheWaitResponse
;
274 // memory system takes ownership of packet
278 // This will need a new way to tell if it has a dcache attached.
279 if (req
->isUncacheable())
280 recordEvent("Uncached Read");
288 #ifndef DOXYGEN_SHOULD_SKIP_THIS
292 TimingSimpleCPU::read(Addr addr
, Twin64_t
&data
, unsigned flags
);
296 TimingSimpleCPU::read(Addr addr
, Twin32_t
&data
, unsigned flags
);
300 TimingSimpleCPU::read(Addr addr
, uint64_t &data
, unsigned flags
);
304 TimingSimpleCPU::read(Addr addr
, uint32_t &data
, unsigned flags
);
308 TimingSimpleCPU::read(Addr addr
, uint16_t &data
, unsigned flags
);
312 TimingSimpleCPU::read(Addr addr
, uint8_t &data
, unsigned flags
);
314 #endif //DOXYGEN_SHOULD_SKIP_THIS
318 TimingSimpleCPU::read(Addr addr
, double &data
, unsigned flags
)
320 return read(addr
, *(uint64_t*)&data
, flags
);
325 TimingSimpleCPU::read(Addr addr
, float &data
, unsigned flags
)
327 return read(addr
, *(uint32_t*)&data
, flags
);
333 TimingSimpleCPU::read(Addr addr
, int32_t &data
, unsigned flags
)
335 return read(addr
, (uint32_t&)data
, flags
);
341 TimingSimpleCPU::write(T data
, Addr addr
, unsigned flags
, uint64_t *res
)
344 new Request(/* asid */ 0, addr
, sizeof(T
), flags
, thread
->readPC(),
345 cpu_id
, /* thread ID */ 0);
348 traceData
->setAddr(req
->getVaddr());
351 // translate to physical address
352 Fault fault
= thread
->translateDataWriteReq(req
);
354 // Now do the access.
355 if (fault
== NoFault
) {
356 MemCmd cmd
= MemCmd::WriteReq
; // default
357 bool do_access
= true; // flag to suppress cache access
359 if (req
->isLocked()) {
360 cmd
= MemCmd::StoreCondReq
;
361 do_access
= TheISA::handleLockedWrite(thread
, req
);
362 } else if (req
->isSwap()) {
363 cmd
= MemCmd::SwapReq
;
364 if (req
->isCondSwap()) {
366 req
->setExtraData(*res
);
370 // Note: need to allocate dcache_pkt even if do_access is
371 // false, as it's used unconditionally to call completeAcc().
372 assert(dcache_pkt
== NULL
);
373 dcache_pkt
= new Packet(req
, cmd
, Packet::Broadcast
);
374 dcache_pkt
->allocate();
375 dcache_pkt
->set(data
);
378 if (!dcachePort
.sendTiming(dcache_pkt
)) {
379 _status
= DcacheRetry
;
381 _status
= DcacheWaitResponse
;
382 // memory system takes ownership of packet
386 // This will need a new way to tell if it's hooked up to a cache or not.
387 if (req
->isUncacheable())
388 recordEvent("Uncached Write");
394 // If the write needs to have a fault on the access, consider calling
395 // changeStatus() and changing it to "bad addr write" or something.
400 #ifndef DOXYGEN_SHOULD_SKIP_THIS
403 TimingSimpleCPU::write(Twin32_t data
, Addr addr
,
404 unsigned flags
, uint64_t *res
);
408 TimingSimpleCPU::write(Twin64_t data
, Addr addr
,
409 unsigned flags
, uint64_t *res
);
413 TimingSimpleCPU::write(uint64_t data
, Addr addr
,
414 unsigned flags
, uint64_t *res
);
418 TimingSimpleCPU::write(uint32_t data
, Addr addr
,
419 unsigned flags
, uint64_t *res
);
423 TimingSimpleCPU::write(uint16_t data
, Addr addr
,
424 unsigned flags
, uint64_t *res
);
428 TimingSimpleCPU::write(uint8_t data
, Addr addr
,
429 unsigned flags
, uint64_t *res
);
431 #endif //DOXYGEN_SHOULD_SKIP_THIS
435 TimingSimpleCPU::write(double data
, Addr addr
, unsigned flags
, uint64_t *res
)
437 return write(*(uint64_t*)&data
, addr
, flags
, res
);
442 TimingSimpleCPU::write(float data
, Addr addr
, unsigned flags
, uint64_t *res
)
444 return write(*(uint32_t*)&data
, addr
, flags
, res
);
450 TimingSimpleCPU::write(int32_t data
, Addr addr
, unsigned flags
, uint64_t *res
)
452 return write((uint32_t)data
, addr
, flags
, res
);
457 TimingSimpleCPU::fetch()
459 if (!curStaticInst
|| !curStaticInst
->isDelayedCommit())
460 checkForInterrupts();
462 Request
*ifetch_req
= new Request();
463 ifetch_req
->setThreadContext(cpu_id
, /* thread ID */ 0);
464 Fault fault
= setupFetchRequest(ifetch_req
);
466 ifetch_pkt
= new Packet(ifetch_req
, MemCmd::ReadReq
, Packet::Broadcast
);
467 ifetch_pkt
->dataStatic(&inst
);
469 if (fault
== NoFault
) {
470 if (!icachePort
.sendTiming(ifetch_pkt
)) {
471 // Need to wait for retry
472 _status
= IcacheRetry
;
474 // Need to wait for cache to respond
475 _status
= IcacheWaitResponse
;
476 // ownership of packet transferred to memory system
482 // fetch fault: advance directly to next instruction (fault handler)
486 numCycles
+= curTick
- previousTick
;
487 previousTick
= curTick
;
492 TimingSimpleCPU::advanceInst(Fault fault
)
496 if (_status
== Running
) {
497 // kick off fetch of next instruction... callback from icache
498 // response will cause that instruction to be executed,
499 // keeping the CPU running.
506 TimingSimpleCPU::completeIfetch(PacketPtr pkt
)
508 // received a response from the icache: execute the received
510 assert(!pkt
->isError());
511 assert(_status
== IcacheWaitResponse
);
515 numCycles
+= curTick
- previousTick
;
516 previousTick
= curTick
;
518 if (getState() == SimObject::Draining
) {
527 if (curStaticInst
->isMemRef() && !curStaticInst
->isDataPrefetch()) {
528 // load or store: just send to dcache
529 Fault fault
= curStaticInst
->initiateAcc(this, traceData
);
530 if (_status
!= Running
) {
531 // instruction will complete in dcache response callback
532 assert(_status
== DcacheWaitResponse
|| _status
== DcacheRetry
);
533 assert(fault
== NoFault
);
535 if (fault
== NoFault
) {
536 // early fail on store conditional: complete now
537 assert(dcache_pkt
!= NULL
);
538 fault
= curStaticInst
->completeAcc(dcache_pkt
, this,
540 delete dcache_pkt
->req
;
548 // non-memory instruction: execute completely now
549 Fault fault
= curStaticInst
->execute(this, traceData
);
559 TimingSimpleCPU::IcachePort::ITickEvent::process()
561 cpu
->completeIfetch(pkt
);
565 TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt
)
567 if (pkt
->isResponse()) {
568 // delay processing of returned data until next CPU clock edge
569 Tick next_tick
= cpu
->nextCycle(curTick
);
571 if (next_tick
== curTick
)
572 cpu
->completeIfetch(pkt
);
574 tickEvent
.schedule(pkt
, next_tick
);
578 else if (pkt
->wasNacked()) {
579 assert(cpu
->_status
== IcacheWaitResponse
);
581 if (!sendTiming(pkt
)) {
582 cpu
->_status
= IcacheRetry
;
583 cpu
->ifetch_pkt
= pkt
;
586 //Snooping a Coherence Request, do nothing
591 TimingSimpleCPU::IcachePort::recvRetry()
593 // we shouldn't get a retry unless we have a packet that we're
594 // waiting to transmit
595 assert(cpu
->ifetch_pkt
!= NULL
);
596 assert(cpu
->_status
== IcacheRetry
);
597 PacketPtr tmp
= cpu
->ifetch_pkt
;
598 if (sendTiming(tmp
)) {
599 cpu
->_status
= IcacheWaitResponse
;
600 cpu
->ifetch_pkt
= NULL
;
605 TimingSimpleCPU::completeDataAccess(PacketPtr pkt
)
607 // received a response from the dcache: complete the load or store
609 assert(!pkt
->isError());
610 assert(_status
== DcacheWaitResponse
);
613 numCycles
+= curTick
- previousTick
;
614 previousTick
= curTick
;
616 Fault fault
= curStaticInst
->completeAcc(pkt
, this, traceData
);
618 if (pkt
->isRead() && pkt
->isLocked()) {
619 TheISA::handleLockedRead(thread
, pkt
->req
);
627 if (getState() == SimObject::Draining
) {
639 TimingSimpleCPU::completeDrain()
641 DPRINTF(Config
, "Done draining\n");
642 changeState(SimObject::Drained
);
643 drainEvent
->process();
647 TimingSimpleCPU::DcachePort::setPeer(Port
*port
)
652 // Update the ThreadContext's memory ports (Functional/Virtual
654 cpu
->tcBase()->connectMemPorts();
659 TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt
)
661 if (pkt
->isResponse()) {
662 // delay processing of returned data until next CPU clock edge
663 Tick next_tick
= cpu
->nextCycle(curTick
);
665 if (next_tick
== curTick
)
666 cpu
->completeDataAccess(pkt
);
668 tickEvent
.schedule(pkt
, next_tick
);
672 else if (pkt
->wasNacked()) {
673 assert(cpu
->_status
== DcacheWaitResponse
);
675 if (!sendTiming(pkt
)) {
676 cpu
->_status
= DcacheRetry
;
677 cpu
->dcache_pkt
= pkt
;
680 //Snooping a Coherence Request, do nothing
685 TimingSimpleCPU::DcachePort::DTickEvent::process()
687 cpu
->completeDataAccess(pkt
);
691 TimingSimpleCPU::DcachePort::recvRetry()
693 // we shouldn't get a retry unless we have a packet that we're
694 // waiting to transmit
695 assert(cpu
->dcache_pkt
!= NULL
);
696 assert(cpu
->_status
== DcacheRetry
);
697 PacketPtr tmp
= cpu
->dcache_pkt
;
698 if (sendTiming(tmp
)) {
699 cpu
->_status
= DcacheWaitResponse
;
700 // memory system takes ownership of packet
701 cpu
->dcache_pkt
= NULL
;
706 ////////////////////////////////////////////////////////////////////////
708 // TimingSimpleCPU Simulation Object
711 TimingSimpleCPUParams::create()
713 TimingSimpleCPU::Params
*params
= new TimingSimpleCPU::Params();
715 params
->numberOfThreads
= 1;
716 params
->max_insts_any_thread
= max_insts_any_thread
;
717 params
->max_insts_all_threads
= max_insts_all_threads
;
718 params
->max_loads_any_thread
= max_loads_any_thread
;
719 params
->max_loads_all_threads
= max_loads_all_threads
;
720 params
->progress_interval
= progress_interval
;
721 params
->deferRegistration
= defer_registration
;
722 params
->clock
= clock
;
723 params
->phase
= phase
;
724 params
->functionTrace
= function_trace
;
725 params
->functionTraceStart
= function_trace_start
;
726 params
->system
= system
;
727 params
->cpu_id
= cpu_id
;
728 params
->tracer
= tracer
;
733 params
->profile
= profile
;
734 params
->do_quiesce
= do_quiesce
;
735 params
->do_checkpoint_insts
= do_checkpoint_insts
;
736 params
->do_statistics_insts
= do_statistics_insts
;
738 if (workload
.size() != 1)
739 panic("only one workload allowed");
740 params
->process
= workload
[0];
743 TimingSimpleCPU
*cpu
= new TimingSimpleCPU(params
);