2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
31 #include "arch/locked_mem.hh"
32 #include "arch/mmaped_ipr.hh"
33 #include "arch/utility.hh"
34 #include "base/bigint.hh"
35 #include "cpu/exetrace.hh"
36 #include "cpu/simple/timing.hh"
37 #include "mem/packet.hh"
38 #include "mem/packet_access.hh"
39 #include "params/TimingSimpleCPU.hh"
40 #include "sim/system.hh"
43 using namespace TheISA
;
46 TimingSimpleCPU::getPort(const std::string
&if_name
, int idx
)
48 if (if_name
== "dcache_port")
50 else if (if_name
== "icache_port")
53 panic("No Such Port\n");
57 TimingSimpleCPU::init()
60 cpuId
= tc
->readCpuId();
62 for (int i
= 0; i
< threadContexts
.size(); ++i
) {
63 ThreadContext
*tc
= threadContexts
[i
];
65 // initialize CPU, including PC
66 TheISA::initCPU(tc
, cpuId
);
72 TimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt
)
74 panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
79 TimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt
)
81 //No internal storage to update, jusst return
86 TimingSimpleCPU::CpuPort::recvStatusChange(Status status
)
88 if (status
== RangeChange
) {
89 if (!snoopRangeSent
) {
90 snoopRangeSent
= true;
91 sendStatusChange(Port::RangeChange
);
96 panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
101 TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt
, Tick t
)
107 TimingSimpleCPU::TimingSimpleCPU(Params
*p
)
108 : BaseSimpleCPU(p
), icachePort(this, p
->clock
), dcachePort(this, p
->clock
)
112 icachePort
.snoopRangeSent
= false;
113 dcachePort
.snoopRangeSent
= false;
115 ifetch_pkt
= dcache_pkt
= NULL
;
119 changeState(SimObject::Running
);
123 TimingSimpleCPU::~TimingSimpleCPU()
128 TimingSimpleCPU::serialize(ostream
&os
)
130 SimObject::State so_state
= SimObject::getState();
131 SERIALIZE_ENUM(so_state
);
132 BaseSimpleCPU::serialize(os
);
136 TimingSimpleCPU::unserialize(Checkpoint
*cp
, const string
§ion
)
138 SimObject::State so_state
;
139 UNSERIALIZE_ENUM(so_state
);
140 BaseSimpleCPU::unserialize(cp
, section
);
144 TimingSimpleCPU::drain(Event
*drain_event
)
146 // TimingSimpleCPU is ready to drain if it's not waiting for
147 // an access to complete.
148 if (status() == Idle
|| status() == Running
|| status() == SwitchedOut
) {
149 changeState(SimObject::Drained
);
152 changeState(SimObject::Draining
);
153 drainEvent
= drain_event
;
159 TimingSimpleCPU::resume()
161 DPRINTF(SimpleCPU
, "Resume\n");
162 if (_status
!= SwitchedOut
&& _status
!= Idle
) {
163 assert(system
->getMemoryMode() == Enums::timing
);
165 // Delete the old event if it existed.
167 if (fetchEvent
->scheduled())
168 fetchEvent
->deschedule();
173 fetchEvent
= new FetchEvent(this, nextCycle());
176 changeState(SimObject::Running
);
180 TimingSimpleCPU::switchOut()
182 assert(status() == Running
|| status() == Idle
);
183 _status
= SwitchedOut
;
184 numCycles
+= tickToCycles(curTick
- previousTick
);
186 // If we've been scheduled to resume but are then told to switch out,
187 // we'll need to cancel it.
188 if (fetchEvent
&& fetchEvent
->scheduled())
189 fetchEvent
->deschedule();
194 TimingSimpleCPU::takeOverFrom(BaseCPU
*oldCPU
)
196 BaseCPU::takeOverFrom(oldCPU
, &icachePort
, &dcachePort
);
198 // if any of this CPU's ThreadContexts are active, mark the CPU as
199 // running and schedule its tick event.
200 for (int i
= 0; i
< threadContexts
.size(); ++i
) {
201 ThreadContext
*tc
= threadContexts
[i
];
202 if (tc
->status() == ThreadContext::Active
&& _status
!= Running
) {
208 if (_status
!= Running
) {
211 assert(threadContexts
.size() == 1);
212 cpuId
= tc
->readCpuId();
213 previousTick
= curTick
;
218 TimingSimpleCPU::activateContext(int thread_num
, int delay
)
220 DPRINTF(SimpleCPU
, "ActivateContext %d (%d cycles)\n", thread_num
, delay
);
222 assert(thread_num
== 0);
225 assert(_status
== Idle
);
230 // kick things off by initiating the fetch of the next instruction
231 fetchEvent
= new FetchEvent(this, nextCycle(curTick
+ ticks(delay
)));
236 TimingSimpleCPU::suspendContext(int thread_num
)
238 DPRINTF(SimpleCPU
, "SuspendContext %d\n", thread_num
);
240 assert(thread_num
== 0);
243 assert(_status
== Running
);
245 // just change status to Idle... if status != Running,
246 // completeInst() will not initiate fetch of next instruction.
255 TimingSimpleCPU::read(Addr addr
, T
&data
, unsigned flags
)
258 new Request(/* asid */ 0, addr
, sizeof(T
), flags
, thread
->readPC(),
259 cpuId
, /* thread ID */ 0);
262 traceData
->setAddr(req
->getVaddr());
265 // translate to physical address
266 Fault fault
= thread
->translateDataReadReq(req
);
268 // Now do the access.
269 if (fault
== NoFault
) {
273 MemCmd::LoadLockedReq
: MemCmd::ReadReq
),
275 pkt
->dataDynamic
<T
>(new T
);
277 if (req
->isMmapedIpr()) {
279 delay
= TheISA::handleIprRead(thread
->getTC(), pkt
);
280 new IprEvent(pkt
, this, nextCycle(curTick
+ delay
));
281 _status
= DcacheWaitResponse
;
283 } else if (!dcachePort
.sendTiming(pkt
)) {
284 _status
= DcacheRetry
;
287 _status
= DcacheWaitResponse
;
288 // memory system takes ownership of packet
292 // This will need a new way to tell if it has a dcache attached.
293 if (req
->isUncacheable())
294 recordEvent("Uncached Read");
303 TimingSimpleCPU::translateDataReadAddr(Addr vaddr
, Addr
&paddr
,
304 int size
, unsigned flags
)
307 new Request(0, vaddr
, size
, flags
, thread
->readPC(), cpuId
, 0);
310 traceData
->setAddr(vaddr
);
313 Fault fault
= thread
->translateDataWriteReq(req
);
315 if (fault
== NoFault
)
316 paddr
= req
->getPaddr();
322 #ifndef DOXYGEN_SHOULD_SKIP_THIS
326 TimingSimpleCPU::read(Addr addr
, Twin64_t
&data
, unsigned flags
);
330 TimingSimpleCPU::read(Addr addr
, Twin32_t
&data
, unsigned flags
);
334 TimingSimpleCPU::read(Addr addr
, uint64_t &data
, unsigned flags
);
338 TimingSimpleCPU::read(Addr addr
, uint32_t &data
, unsigned flags
);
342 TimingSimpleCPU::read(Addr addr
, uint16_t &data
, unsigned flags
);
346 TimingSimpleCPU::read(Addr addr
, uint8_t &data
, unsigned flags
);
348 #endif //DOXYGEN_SHOULD_SKIP_THIS
352 TimingSimpleCPU::read(Addr addr
, double &data
, unsigned flags
)
354 return read(addr
, *(uint64_t*)&data
, flags
);
359 TimingSimpleCPU::read(Addr addr
, float &data
, unsigned flags
)
361 return read(addr
, *(uint32_t*)&data
, flags
);
367 TimingSimpleCPU::read(Addr addr
, int32_t &data
, unsigned flags
)
369 return read(addr
, (uint32_t&)data
, flags
);
375 TimingSimpleCPU::write(T data
, Addr addr
, unsigned flags
, uint64_t *res
)
378 new Request(/* asid */ 0, addr
, sizeof(T
), flags
, thread
->readPC(),
379 cpuId
, /* thread ID */ 0);
382 traceData
->setAddr(req
->getVaddr());
385 // translate to physical address
386 Fault fault
= thread
->translateDataWriteReq(req
);
388 // Now do the access.
389 if (fault
== NoFault
) {
390 MemCmd cmd
= MemCmd::WriteReq
; // default
391 bool do_access
= true; // flag to suppress cache access
393 if (req
->isLocked()) {
394 cmd
= MemCmd::StoreCondReq
;
395 do_access
= TheISA::handleLockedWrite(thread
, req
);
396 } else if (req
->isSwap()) {
397 cmd
= MemCmd::SwapReq
;
398 if (req
->isCondSwap()) {
400 req
->setExtraData(*res
);
404 // Note: need to allocate dcache_pkt even if do_access is
405 // false, as it's used unconditionally to call completeAcc().
406 assert(dcache_pkt
== NULL
);
407 dcache_pkt
= new Packet(req
, cmd
, Packet::Broadcast
);
408 dcache_pkt
->allocate();
409 dcache_pkt
->set(data
);
412 if (req
->isMmapedIpr()) {
414 dcache_pkt
->set(htog(data
));
415 delay
= TheISA::handleIprWrite(thread
->getTC(), dcache_pkt
);
416 new IprEvent(dcache_pkt
, this, nextCycle(curTick
+ delay
));
417 _status
= DcacheWaitResponse
;
419 } else if (!dcachePort
.sendTiming(dcache_pkt
)) {
420 _status
= DcacheRetry
;
422 _status
= DcacheWaitResponse
;
423 // memory system takes ownership of packet
427 // This will need a new way to tell if it's hooked up to a cache or not.
428 if (req
->isUncacheable())
429 recordEvent("Uncached Write");
435 // If the write needs to have a fault on the access, consider calling
436 // changeStatus() and changing it to "bad addr write" or something.
441 TimingSimpleCPU::translateDataWriteAddr(Addr vaddr
, Addr
&paddr
,
442 int size
, unsigned flags
)
445 new Request(0, vaddr
, size
, flags
, thread
->readPC(), cpuId
, 0);
448 traceData
->setAddr(vaddr
);
451 Fault fault
= thread
->translateDataWriteReq(req
);
453 if (fault
== NoFault
)
454 paddr
= req
->getPaddr();
461 #ifndef DOXYGEN_SHOULD_SKIP_THIS
464 TimingSimpleCPU::write(Twin32_t data
, Addr addr
,
465 unsigned flags
, uint64_t *res
);
469 TimingSimpleCPU::write(Twin64_t data
, Addr addr
,
470 unsigned flags
, uint64_t *res
);
474 TimingSimpleCPU::write(uint64_t data
, Addr addr
,
475 unsigned flags
, uint64_t *res
);
479 TimingSimpleCPU::write(uint32_t data
, Addr addr
,
480 unsigned flags
, uint64_t *res
);
484 TimingSimpleCPU::write(uint16_t data
, Addr addr
,
485 unsigned flags
, uint64_t *res
);
489 TimingSimpleCPU::write(uint8_t data
, Addr addr
,
490 unsigned flags
, uint64_t *res
);
492 #endif //DOXYGEN_SHOULD_SKIP_THIS
496 TimingSimpleCPU::write(double data
, Addr addr
, unsigned flags
, uint64_t *res
)
498 return write(*(uint64_t*)&data
, addr
, flags
, res
);
503 TimingSimpleCPU::write(float data
, Addr addr
, unsigned flags
, uint64_t *res
)
505 return write(*(uint32_t*)&data
, addr
, flags
, res
);
511 TimingSimpleCPU::write(int32_t data
, Addr addr
, unsigned flags
, uint64_t *res
)
513 return write((uint32_t)data
, addr
, flags
, res
);
518 TimingSimpleCPU::fetch()
520 DPRINTF(SimpleCPU
, "Fetch\n");
522 if (!curStaticInst
|| !curStaticInst
->isDelayedCommit())
523 checkForInterrupts();
525 Request
*ifetch_req
= new Request();
526 ifetch_req
->setThreadContext(cpuId
, /* thread ID */ 0);
527 Fault fault
= setupFetchRequest(ifetch_req
);
529 ifetch_pkt
= new Packet(ifetch_req
, MemCmd::ReadReq
, Packet::Broadcast
);
530 ifetch_pkt
->dataStatic(&inst
);
532 if (fault
== NoFault
) {
533 if (!icachePort
.sendTiming(ifetch_pkt
)) {
534 // Need to wait for retry
535 _status
= IcacheRetry
;
537 // Need to wait for cache to respond
538 _status
= IcacheWaitResponse
;
539 // ownership of packet transferred to memory system
545 // fetch fault: advance directly to next instruction (fault handler)
549 numCycles
+= tickToCycles(curTick
- previousTick
);
550 previousTick
= curTick
;
555 TimingSimpleCPU::advanceInst(Fault fault
)
559 if (_status
== Running
) {
560 // kick off fetch of next instruction... callback from icache
561 // response will cause that instruction to be executed,
562 // keeping the CPU running.
569 TimingSimpleCPU::completeIfetch(PacketPtr pkt
)
571 DPRINTF(SimpleCPU
, "Complete ICache Fetch\n");
573 // received a response from the icache: execute the received
575 assert(!pkt
->isError());
576 assert(_status
== IcacheWaitResponse
);
580 numCycles
+= tickToCycles(curTick
- previousTick
);
581 previousTick
= curTick
;
583 if (getState() == SimObject::Draining
) {
592 if (curStaticInst
->isMemRef() && !curStaticInst
->isDataPrefetch()) {
593 // load or store: just send to dcache
594 Fault fault
= curStaticInst
->initiateAcc(this, traceData
);
595 if (_status
!= Running
) {
596 // instruction will complete in dcache response callback
597 assert(_status
== DcacheWaitResponse
|| _status
== DcacheRetry
);
598 assert(fault
== NoFault
);
600 if (fault
== NoFault
) {
601 // early fail on store conditional: complete now
602 assert(dcache_pkt
!= NULL
);
603 fault
= curStaticInst
->completeAcc(dcache_pkt
, this,
605 delete dcache_pkt
->req
;
609 // keep an instruction count
610 if (fault
== NoFault
)
612 } else if (traceData
) {
613 // If there was a fault, we shouldn't trace this instruction.
619 // @todo remove me after debugging with legion done
620 if (curStaticInst
&& (!curStaticInst
->isMicroop() ||
621 curStaticInst
->isFirstMicroop()))
626 // non-memory instruction: execute completely now
627 Fault fault
= curStaticInst
->execute(this, traceData
);
629 // keep an instruction count
630 if (fault
== NoFault
)
632 else if (traceData
) {
633 // If there was a fault, we shouldn't trace this instruction.
639 // @todo remove me after debugging with legion done
640 if (curStaticInst
&& (!curStaticInst
->isMicroop() ||
641 curStaticInst
->isFirstMicroop()))
651 TimingSimpleCPU::IcachePort::ITickEvent::process()
653 cpu
->completeIfetch(pkt
);
657 TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt
)
659 if (pkt
->isResponse() && !pkt
->wasNacked()) {
660 // delay processing of returned data until next CPU clock edge
661 Tick next_tick
= cpu
->nextCycle(curTick
);
663 if (next_tick
== curTick
)
664 cpu
->completeIfetch(pkt
);
666 tickEvent
.schedule(pkt
, next_tick
);
670 else if (pkt
->wasNacked()) {
671 assert(cpu
->_status
== IcacheWaitResponse
);
673 if (!sendTiming(pkt
)) {
674 cpu
->_status
= IcacheRetry
;
675 cpu
->ifetch_pkt
= pkt
;
678 //Snooping a Coherence Request, do nothing
683 TimingSimpleCPU::IcachePort::recvRetry()
685 // we shouldn't get a retry unless we have a packet that we're
686 // waiting to transmit
687 assert(cpu
->ifetch_pkt
!= NULL
);
688 assert(cpu
->_status
== IcacheRetry
);
689 PacketPtr tmp
= cpu
->ifetch_pkt
;
690 if (sendTiming(tmp
)) {
691 cpu
->_status
= IcacheWaitResponse
;
692 cpu
->ifetch_pkt
= NULL
;
697 TimingSimpleCPU::completeDataAccess(PacketPtr pkt
)
699 // received a response from the dcache: complete the load or store
701 assert(!pkt
->isError());
702 assert(_status
== DcacheWaitResponse
);
705 numCycles
+= tickToCycles(curTick
- previousTick
);
706 previousTick
= curTick
;
708 Fault fault
= curStaticInst
->completeAcc(pkt
, this, traceData
);
710 // keep an instruction count
711 if (fault
== NoFault
)
713 else if (traceData
) {
714 // If there was a fault, we shouldn't trace this instruction.
719 if (pkt
->isRead() && pkt
->isLocked()) {
720 TheISA::handleLockedRead(thread
, pkt
->req
);
728 if (getState() == SimObject::Draining
) {
740 TimingSimpleCPU::completeDrain()
742 DPRINTF(Config
, "Done draining\n");
743 changeState(SimObject::Drained
);
744 drainEvent
->process();
748 TimingSimpleCPU::DcachePort::setPeer(Port
*port
)
753 // Update the ThreadContext's memory ports (Functional/Virtual
755 cpu
->tcBase()->connectMemPorts();
760 TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt
)
762 if (pkt
->isResponse() && !pkt
->wasNacked()) {
763 // delay processing of returned data until next CPU clock edge
764 Tick next_tick
= cpu
->nextCycle(curTick
);
766 if (next_tick
== curTick
)
767 cpu
->completeDataAccess(pkt
);
769 tickEvent
.schedule(pkt
, next_tick
);
773 else if (pkt
->wasNacked()) {
774 assert(cpu
->_status
== DcacheWaitResponse
);
776 if (!sendTiming(pkt
)) {
777 cpu
->_status
= DcacheRetry
;
778 cpu
->dcache_pkt
= pkt
;
781 //Snooping a Coherence Request, do nothing
786 TimingSimpleCPU::DcachePort::DTickEvent::process()
788 cpu
->completeDataAccess(pkt
);
792 TimingSimpleCPU::DcachePort::recvRetry()
794 // we shouldn't get a retry unless we have a packet that we're
795 // waiting to transmit
796 assert(cpu
->dcache_pkt
!= NULL
);
797 assert(cpu
->_status
== DcacheRetry
);
798 PacketPtr tmp
= cpu
->dcache_pkt
;
799 if (sendTiming(tmp
)) {
800 cpu
->_status
= DcacheWaitResponse
;
801 // memory system takes ownership of packet
802 cpu
->dcache_pkt
= NULL
;
806 TimingSimpleCPU::IprEvent::IprEvent(Packet
*_pkt
, TimingSimpleCPU
*_cpu
, Tick t
)
807 : Event(&mainEventQueue
), pkt(_pkt
), cpu(_cpu
)
813 TimingSimpleCPU::IprEvent::process()
815 cpu
->completeDataAccess(pkt
);
819 TimingSimpleCPU::IprEvent::description()
821 return "Timing Simple CPU Delay IPR event";
826 TimingSimpleCPU::printAddr(Addr a
)
828 dcachePort
.printAddr(a
);
832 ////////////////////////////////////////////////////////////////////////
834 // TimingSimpleCPU Simulation Object
837 TimingSimpleCPUParams::create()
839 TimingSimpleCPU::Params
*params
= new TimingSimpleCPU::Params();
841 params
->numberOfThreads
= 1;
842 params
->max_insts_any_thread
= max_insts_any_thread
;
843 params
->max_insts_all_threads
= max_insts_all_threads
;
844 params
->max_loads_any_thread
= max_loads_any_thread
;
845 params
->max_loads_all_threads
= max_loads_all_threads
;
846 params
->progress_interval
= progress_interval
;
847 params
->deferRegistration
= defer_registration
;
848 params
->clock
= clock
;
849 params
->phase
= phase
;
850 params
->functionTrace
= function_trace
;
851 params
->functionTraceStart
= function_trace_start
;
852 params
->system
= system
;
853 params
->cpu_id
= cpu_id
;
854 params
->tracer
= tracer
;
859 params
->profile
= profile
;
860 params
->do_quiesce
= do_quiesce
;
861 params
->do_checkpoint_insts
= do_checkpoint_insts
;
862 params
->do_statistics_insts
= do_statistics_insts
;
864 if (workload
.size() != 1)
865 panic("only one workload allowed");
866 params
->process
= workload
[0];
869 TimingSimpleCPU
*cpu
= new TimingSimpleCPU(params
);