2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
31 #include "arch/locked_mem.hh"
32 #include "arch/utility.hh"
33 #include "base/bigint.hh"
34 #include "cpu/exetrace.hh"
35 #include "cpu/simple/timing.hh"
36 #include "mem/packet.hh"
37 #include "mem/packet_access.hh"
38 #include "sim/builder.hh"
39 #include "sim/system.hh"
42 using namespace TheISA
;
45 TimingSimpleCPU::getPort(const std::string
&if_name
, int idx
)
47 if (if_name
== "dcache_port")
49 else if (if_name
== "icache_port")
52 panic("No Such Port\n");
56 TimingSimpleCPU::init()
60 for (int i
= 0; i
< threadContexts
.size(); ++i
) {
61 ThreadContext
*tc
= threadContexts
[i
];
63 // initialize CPU, including PC
64 TheISA::initCPU(tc
, tc
->readCpuId());
70 TimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt
)
72 panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
77 TimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt
)
79 //No internal storage to update, jusst return
84 TimingSimpleCPU::CpuPort::recvStatusChange(Status status
)
86 if (status
== RangeChange
) {
87 if (!snoopRangeSent
) {
88 snoopRangeSent
= true;
89 sendStatusChange(Port::RangeChange
);
94 panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
99 TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt
, Tick t
)
105 TimingSimpleCPU::TimingSimpleCPU(Params
*p
)
106 : BaseSimpleCPU(p
), icachePort(this, p
->clock
), dcachePort(this, p
->clock
),
111 icachePort
.snoopRangeSent
= false;
112 dcachePort
.snoopRangeSent
= false;
114 ifetch_pkt
= dcache_pkt
= NULL
;
118 changeState(SimObject::Running
);
122 TimingSimpleCPU::~TimingSimpleCPU()
127 TimingSimpleCPU::serialize(ostream
&os
)
129 SimObject::State so_state
= SimObject::getState();
130 SERIALIZE_ENUM(so_state
);
131 BaseSimpleCPU::serialize(os
);
135 TimingSimpleCPU::unserialize(Checkpoint
*cp
, const string
§ion
)
137 SimObject::State so_state
;
138 UNSERIALIZE_ENUM(so_state
);
139 BaseSimpleCPU::unserialize(cp
, section
);
143 TimingSimpleCPU::drain(Event
*drain_event
)
145 // TimingSimpleCPU is ready to drain if it's not waiting for
146 // an access to complete.
147 if (status() == Idle
|| status() == Running
|| status() == SwitchedOut
) {
148 changeState(SimObject::Drained
);
151 changeState(SimObject::Draining
);
152 drainEvent
= drain_event
;
158 TimingSimpleCPU::resume()
160 if (_status
!= SwitchedOut
&& _status
!= Idle
) {
161 assert(system
->getMemoryMode() == System::Timing
);
163 // Delete the old event if it existed.
165 if (fetchEvent
->scheduled())
166 fetchEvent
->deschedule();
171 fetchEvent
= new FetchEvent(this, nextCycle());
174 changeState(SimObject::Running
);
175 previousTick
= curTick
;
179 TimingSimpleCPU::switchOut()
181 assert(status() == Running
|| status() == Idle
);
182 _status
= SwitchedOut
;
183 numCycles
+= curTick
- previousTick
;
185 // If we've been scheduled to resume but are then told to switch out,
186 // we'll need to cancel it.
187 if (fetchEvent
&& fetchEvent
->scheduled())
188 fetchEvent
->deschedule();
193 TimingSimpleCPU::takeOverFrom(BaseCPU
*oldCPU
)
195 BaseCPU::takeOverFrom(oldCPU
, &icachePort
, &dcachePort
);
197 // if any of this CPU's ThreadContexts are active, mark the CPU as
198 // running and schedule its tick event.
199 for (int i
= 0; i
< threadContexts
.size(); ++i
) {
200 ThreadContext
*tc
= threadContexts
[i
];
201 if (tc
->status() == ThreadContext::Active
&& _status
!= Running
) {
207 if (_status
!= Running
) {
214 TimingSimpleCPU::activateContext(int thread_num
, int delay
)
216 assert(thread_num
== 0);
219 assert(_status
== Idle
);
224 // kick things off by initiating the fetch of the next instruction
225 fetchEvent
= new FetchEvent(this, nextCycle(curTick
+ cycles(delay
)));
230 TimingSimpleCPU::suspendContext(int thread_num
)
232 assert(thread_num
== 0);
235 assert(_status
== Running
);
237 // just change status to Idle... if status != Running,
238 // completeInst() will not initiate fetch of next instruction.
247 TimingSimpleCPU::read(Addr addr
, T
&data
, unsigned flags
)
250 new Request(/* asid */ 0, addr
, sizeof(T
), flags
, thread
->readPC(),
251 cpu_id
, /* thread ID */ 0);
254 traceData
->setAddr(req
->getVaddr());
257 // translate to physical address
258 Fault fault
= thread
->translateDataReadReq(req
);
260 // Now do the access.
261 if (fault
== NoFault
) {
263 new Packet(req
, MemCmd::ReadReq
, Packet::Broadcast
);
264 pkt
->dataDynamic
<T
>(new T
);
266 if (!dcachePort
.sendTiming(pkt
)) {
267 _status
= DcacheRetry
;
270 _status
= DcacheWaitResponse
;
271 // memory system takes ownership of packet
275 // This will need a new way to tell if it has a dcache attached.
276 if (req
->isUncacheable())
277 recordEvent("Uncached Read");
285 #ifndef DOXYGEN_SHOULD_SKIP_THIS
289 TimingSimpleCPU::read(Addr addr
, Twin64_t
&data
, unsigned flags
);
293 TimingSimpleCPU::read(Addr addr
, Twin32_t
&data
, unsigned flags
);
297 TimingSimpleCPU::read(Addr addr
, uint64_t &data
, unsigned flags
);
301 TimingSimpleCPU::read(Addr addr
, uint32_t &data
, unsigned flags
);
305 TimingSimpleCPU::read(Addr addr
, uint16_t &data
, unsigned flags
);
309 TimingSimpleCPU::read(Addr addr
, uint8_t &data
, unsigned flags
);
311 #endif //DOXYGEN_SHOULD_SKIP_THIS
315 TimingSimpleCPU::read(Addr addr
, double &data
, unsigned flags
)
317 return read(addr
, *(uint64_t*)&data
, flags
);
322 TimingSimpleCPU::read(Addr addr
, float &data
, unsigned flags
)
324 return read(addr
, *(uint32_t*)&data
, flags
);
330 TimingSimpleCPU::read(Addr addr
, int32_t &data
, unsigned flags
)
332 return read(addr
, (uint32_t&)data
, flags
);
338 TimingSimpleCPU::write(T data
, Addr addr
, unsigned flags
, uint64_t *res
)
341 new Request(/* asid */ 0, addr
, sizeof(T
), flags
, thread
->readPC(),
342 cpu_id
, /* thread ID */ 0);
345 traceData
->setAddr(req
->getVaddr());
348 // translate to physical address
349 Fault fault
= thread
->translateDataWriteReq(req
);
351 // Now do the access.
352 if (fault
== NoFault
) {
353 assert(dcache_pkt
== NULL
);
355 dcache_pkt
= new Packet(req
, MemCmd::SwapReq
, Packet::Broadcast
);
357 dcache_pkt
= new Packet(req
, MemCmd::WriteReq
, Packet::Broadcast
);
358 dcache_pkt
->allocate();
359 dcache_pkt
->set(data
);
361 bool do_access
= true; // flag to suppress cache access
363 if (req
->isLocked()) {
364 do_access
= TheISA::handleLockedWrite(thread
, req
);
366 if (req
->isCondSwap()) {
368 req
->setExtraData(*res
);
372 if (!dcachePort
.sendTiming(dcache_pkt
)) {
373 _status
= DcacheRetry
;
375 _status
= DcacheWaitResponse
;
376 // memory system takes ownership of packet
380 // This will need a new way to tell if it's hooked up to a cache or not.
381 if (req
->isUncacheable())
382 recordEvent("Uncached Write");
388 // If the write needs to have a fault on the access, consider calling
389 // changeStatus() and changing it to "bad addr write" or something.
394 #ifndef DOXYGEN_SHOULD_SKIP_THIS
397 TimingSimpleCPU::write(Twin32_t data
, Addr addr
,
398 unsigned flags
, uint64_t *res
);
402 TimingSimpleCPU::write(Twin64_t data
, Addr addr
,
403 unsigned flags
, uint64_t *res
);
407 TimingSimpleCPU::write(uint64_t data
, Addr addr
,
408 unsigned flags
, uint64_t *res
);
412 TimingSimpleCPU::write(uint32_t data
, Addr addr
,
413 unsigned flags
, uint64_t *res
);
417 TimingSimpleCPU::write(uint16_t data
, Addr addr
,
418 unsigned flags
, uint64_t *res
);
422 TimingSimpleCPU::write(uint8_t data
, Addr addr
,
423 unsigned flags
, uint64_t *res
);
425 #endif //DOXYGEN_SHOULD_SKIP_THIS
429 TimingSimpleCPU::write(double data
, Addr addr
, unsigned flags
, uint64_t *res
)
431 return write(*(uint64_t*)&data
, addr
, flags
, res
);
436 TimingSimpleCPU::write(float data
, Addr addr
, unsigned flags
, uint64_t *res
)
438 return write(*(uint32_t*)&data
, addr
, flags
, res
);
444 TimingSimpleCPU::write(int32_t data
, Addr addr
, unsigned flags
, uint64_t *res
)
446 return write((uint32_t)data
, addr
, flags
, res
);
451 TimingSimpleCPU::fetch()
453 if (!curStaticInst
|| !curStaticInst
->isDelayedCommit())
454 checkForInterrupts();
456 Request
*ifetch_req
= new Request();
457 ifetch_req
->setThreadContext(cpu_id
, /* thread ID */ 0);
458 Fault fault
= setupFetchRequest(ifetch_req
);
460 ifetch_pkt
= new Packet(ifetch_req
, MemCmd::ReadReq
, Packet::Broadcast
);
461 ifetch_pkt
->dataStatic(&inst
);
463 if (fault
== NoFault
) {
464 if (!icachePort
.sendTiming(ifetch_pkt
)) {
465 // Need to wait for retry
466 _status
= IcacheRetry
;
468 // Need to wait for cache to respond
469 _status
= IcacheWaitResponse
;
470 // ownership of packet transferred to memory system
476 // fetch fault: advance directly to next instruction (fault handler)
480 numCycles
+= curTick
- previousTick
;
481 previousTick
= curTick
;
486 TimingSimpleCPU::advanceInst(Fault fault
)
490 if (_status
== Running
) {
491 // kick off fetch of next instruction... callback from icache
492 // response will cause that instruction to be executed,
493 // keeping the CPU running.
500 TimingSimpleCPU::completeIfetch(PacketPtr pkt
)
502 // received a response from the icache: execute the received
504 assert(pkt
->result
== Packet::Success
);
505 assert(_status
== IcacheWaitResponse
);
509 numCycles
+= curTick
- previousTick
;
510 previousTick
= curTick
;
512 if (getState() == SimObject::Draining
) {
521 if (curStaticInst
->isMemRef() && !curStaticInst
->isDataPrefetch()) {
522 // load or store: just send to dcache
523 Fault fault
= curStaticInst
->initiateAcc(this, traceData
);
524 if (_status
!= Running
) {
525 // instruction will complete in dcache response callback
526 assert(_status
== DcacheWaitResponse
|| _status
== DcacheRetry
);
527 assert(fault
== NoFault
);
529 if (fault
== NoFault
) {
530 // early fail on store conditional: complete now
531 assert(dcache_pkt
!= NULL
);
532 fault
= curStaticInst
->completeAcc(dcache_pkt
, this,
534 delete dcache_pkt
->req
;
542 // non-memory instruction: execute completely now
543 Fault fault
= curStaticInst
->execute(this, traceData
);
553 TimingSimpleCPU::IcachePort::ITickEvent::process()
555 cpu
->completeIfetch(pkt
);
559 TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt
)
561 if (pkt
->isResponse()) {
562 // delay processing of returned data until next CPU clock edge
563 Tick next_tick
= cpu
->nextCycle(curTick
);
565 if (next_tick
== curTick
)
566 cpu
->completeIfetch(pkt
);
568 tickEvent
.schedule(pkt
, next_tick
);
572 else if (pkt
->result
== Packet::Nacked
) {
573 assert(cpu
->_status
== IcacheWaitResponse
);
575 if (!sendTiming(pkt
)) {
576 cpu
->_status
= IcacheRetry
;
577 cpu
->ifetch_pkt
= pkt
;
580 //Snooping a Coherence Request, do nothing
585 TimingSimpleCPU::IcachePort::recvRetry()
587 // we shouldn't get a retry unless we have a packet that we're
588 // waiting to transmit
589 assert(cpu
->ifetch_pkt
!= NULL
);
590 assert(cpu
->_status
== IcacheRetry
);
591 PacketPtr tmp
= cpu
->ifetch_pkt
;
592 if (sendTiming(tmp
)) {
593 cpu
->_status
= IcacheWaitResponse
;
594 cpu
->ifetch_pkt
= NULL
;
599 TimingSimpleCPU::completeDataAccess(PacketPtr pkt
)
601 // received a response from the dcache: complete the load or store
603 assert(pkt
->result
== Packet::Success
);
604 assert(_status
== DcacheWaitResponse
);
607 numCycles
+= curTick
- previousTick
;
608 previousTick
= curTick
;
610 Fault fault
= curStaticInst
->completeAcc(pkt
, this, traceData
);
612 if (pkt
->isRead() && pkt
->req
->isLocked()) {
613 TheISA::handleLockedRead(thread
, pkt
->req
);
621 if (getState() == SimObject::Draining
) {
633 TimingSimpleCPU::completeDrain()
635 DPRINTF(Config
, "Done draining\n");
636 changeState(SimObject::Drained
);
637 drainEvent
->process();
641 TimingSimpleCPU::DcachePort::setPeer(Port
*port
)
646 // Update the ThreadContext's memory ports (Functional/Virtual
648 cpu
->tcBase()->connectMemPorts();
653 TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt
)
655 if (pkt
->isResponse()) {
656 // delay processing of returned data until next CPU clock edge
657 Tick next_tick
= cpu
->nextCycle(curTick
);
659 if (next_tick
== curTick
)
660 cpu
->completeDataAccess(pkt
);
662 tickEvent
.schedule(pkt
, next_tick
);
666 else if (pkt
->result
== Packet::Nacked
) {
667 assert(cpu
->_status
== DcacheWaitResponse
);
669 if (!sendTiming(pkt
)) {
670 cpu
->_status
= DcacheRetry
;
671 cpu
->dcache_pkt
= pkt
;
674 //Snooping a Coherence Request, do nothing
679 TimingSimpleCPU::DcachePort::DTickEvent::process()
681 cpu
->completeDataAccess(pkt
);
685 TimingSimpleCPU::DcachePort::recvRetry()
687 // we shouldn't get a retry unless we have a packet that we're
688 // waiting to transmit
689 assert(cpu
->dcache_pkt
!= NULL
);
690 assert(cpu
->_status
== DcacheRetry
);
691 PacketPtr tmp
= cpu
->dcache_pkt
;
692 if (sendTiming(tmp
)) {
693 cpu
->_status
= DcacheWaitResponse
;
694 // memory system takes ownership of packet
695 cpu
->dcache_pkt
= NULL
;
700 ////////////////////////////////////////////////////////////////////////
702 // TimingSimpleCPU Simulation Object
704 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU
)
706 Param
<Counter
> max_insts_any_thread
;
707 Param
<Counter
> max_insts_all_threads
;
708 Param
<Counter
> max_loads_any_thread
;
709 Param
<Counter
> max_loads_all_threads
;
710 Param
<Tick
> progress_interval
;
711 SimObjectParam
<System
*> system
;
715 SimObjectParam
<TheISA::ITB
*> itb
;
716 SimObjectParam
<TheISA::DTB
*> dtb
;
719 Param
<bool> do_quiesce
;
720 Param
<bool> do_checkpoint_insts
;
721 Param
<bool> do_statistics_insts
;
723 SimObjectParam
<Process
*> workload
;
724 #endif // FULL_SYSTEM
729 Param
<bool> defer_registration
;
731 Param
<bool> function_trace
;
732 Param
<Tick
> function_trace_start
;
733 Param
<bool> simulate_stalls
;
735 END_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU
)
737 BEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU
)
739 INIT_PARAM(max_insts_any_thread
,
740 "terminate when any thread reaches this inst count"),
741 INIT_PARAM(max_insts_all_threads
,
742 "terminate when all threads have reached this inst count"),
743 INIT_PARAM(max_loads_any_thread
,
744 "terminate when any thread reaches this load count"),
745 INIT_PARAM(max_loads_all_threads
,
746 "terminate when all threads have reached this load count"),
747 INIT_PARAM(progress_interval
, "Progress interval"),
748 INIT_PARAM(system
, "system object"),
749 INIT_PARAM(cpu_id
, "processor ID"),
752 INIT_PARAM(itb
, "Instruction TLB"),
753 INIT_PARAM(dtb
, "Data TLB"),
754 INIT_PARAM(profile
, ""),
755 INIT_PARAM(do_quiesce
, ""),
756 INIT_PARAM(do_checkpoint_insts
, ""),
757 INIT_PARAM(do_statistics_insts
, ""),
759 INIT_PARAM(workload
, "processes to run"),
760 #endif // FULL_SYSTEM
762 INIT_PARAM(clock
, "clock speed"),
763 INIT_PARAM_DFLT(phase
, "clock phase", 0),
764 INIT_PARAM(defer_registration
, "defer system registration (for sampling)"),
765 INIT_PARAM(width
, "cpu width"),
766 INIT_PARAM(function_trace
, "Enable function trace"),
767 INIT_PARAM(function_trace_start
, "Cycle to start function trace"),
768 INIT_PARAM(simulate_stalls
, "Simulate cache stall cycles")
770 END_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU
)
773 CREATE_SIM_OBJECT(TimingSimpleCPU
)
775 TimingSimpleCPU::Params
*params
= new TimingSimpleCPU::Params();
776 params
->name
= getInstanceName();
777 params
->numberOfThreads
= 1;
778 params
->max_insts_any_thread
= max_insts_any_thread
;
779 params
->max_insts_all_threads
= max_insts_all_threads
;
780 params
->max_loads_any_thread
= max_loads_any_thread
;
781 params
->max_loads_all_threads
= max_loads_all_threads
;
782 params
->progress_interval
= progress_interval
;
783 params
->deferRegistration
= defer_registration
;
784 params
->clock
= clock
;
785 params
->phase
= phase
;
786 params
->functionTrace
= function_trace
;
787 params
->functionTraceStart
= function_trace_start
;
788 params
->system
= system
;
789 params
->cpu_id
= cpu_id
;
794 params
->profile
= profile
;
795 params
->do_quiesce
= do_quiesce
;
796 params
->do_checkpoint_insts
= do_checkpoint_insts
;
797 params
->do_statistics_insts
= do_statistics_insts
;
799 params
->process
= workload
;
802 TimingSimpleCPU
*cpu
= new TimingSimpleCPU(params
);
806 REGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU
)