2 * Copyright (c) 2012-2013,2015 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
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26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Steve Reinhardt
43 #ifndef __CPU_SIMPLE_TIMING_HH__
44 #define __CPU_SIMPLE_TIMING_HH__
46 #include "cpu/simple/base.hh"
47 #include "cpu/simple/exec_context.hh"
48 #include "cpu/translation.hh"
49 #include "params/TimingSimpleCPU.hh"
51 class TimingSimpleCPU : public BaseSimpleCPU
55 TimingSimpleCPU(TimingSimpleCPUParams * params);
56 virtual ~TimingSimpleCPU();
63 * If an access needs to be broken into fragments, currently at most two,
64 * the the following two classes are used as the sender state of the
65 * packets so the CPU can keep track of everything. In the main packet
66 * sender state, there's an array with a spot for each fragment. If a
67 * fragment has already been accepted by the CPU, aka isn't waiting for
68 * a retry, it's pointer is NULL. After each fragment has successfully
69 * been processed, the "outstanding" counter is decremented. Once the
70 * count is zero, the entire larger access is complete.
72 class SplitMainSenderState : public Packet::SenderState
76 PacketPtr fragments[2];
83 } else if (fragments[1]) {
91 class SplitFragmentSenderState : public Packet::SenderState
94 SplitFragmentSenderState(PacketPtr _bigPkt, int _index) :
95 bigPkt(_bigPkt), index(_index)
103 SplitMainSenderState * main_send_state =
104 dynamic_cast<SplitMainSenderState *>(bigPkt->senderState);
105 main_send_state->fragments[index] = NULL;
109 class FetchTranslation : public BaseTLB::Translation
112 TimingSimpleCPU *cpu;
115 FetchTranslation(TimingSimpleCPU *_cpu)
122 assert(cpu->_status == BaseSimpleCPU::Running);
123 cpu->_status = ITBWaitResponse;
127 finish(const Fault &fault, RequestPtr req, ThreadContext *tc,
130 cpu->sendFetch(fault, req, tc);
133 FetchTranslation fetchTranslation;
135 void threadSnoop(PacketPtr pkt, ThreadID sender);
136 void sendData(RequestPtr req, uint8_t *data, uint64_t *res, bool read);
137 void sendSplitData(RequestPtr req1, RequestPtr req2, RequestPtr req,
138 uint8_t *data, bool read);
140 void translationFault(const Fault &fault);
142 PacketPtr buildPacket(RequestPtr req, bool read);
143 void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
144 RequestPtr req1, RequestPtr req2, RequestPtr req,
145 uint8_t *data, bool read);
147 bool handleReadPacket(PacketPtr pkt);
148 // This function always implicitly uses dcache_pkt.
149 bool handleWritePacket();
152 * A TimingCPUPort overrides the default behaviour of the
153 * recvTiming and recvRetry and implements events for the
154 * scheduling of handling of incoming packets in the following
157 class TimingCPUPort : public MasterPort
161 TimingCPUPort(const std::string& _name, TimingSimpleCPU* _cpu)
162 : MasterPort(_name, _cpu), cpu(_cpu),
163 retryRespEvent([this]{ sendRetryResp(); }, name())
168 TimingSimpleCPU* cpu;
170 struct TickEvent : public Event
173 TimingSimpleCPU *cpu;
175 TickEvent(TimingSimpleCPU *_cpu) : pkt(NULL), cpu(_cpu) {}
176 const char *description() const { return "Timing CPU tick"; }
177 void schedule(PacketPtr _pkt, Tick t);
180 EventFunctionWrapper retryRespEvent;
183 class IcachePort : public TimingCPUPort
187 IcachePort(TimingSimpleCPU *_cpu)
188 : TimingCPUPort(_cpu->name() + ".icache_port", _cpu),
194 virtual bool recvTimingResp(PacketPtr pkt);
196 virtual void recvReqRetry();
198 struct ITickEvent : public TickEvent
201 ITickEvent(TimingSimpleCPU *_cpu)
204 const char *description() const { return "Timing CPU icache tick"; }
207 ITickEvent tickEvent;
211 class DcachePort : public TimingCPUPort
215 DcachePort(TimingSimpleCPU *_cpu)
216 : TimingCPUPort(_cpu->name() + ".dcache_port", _cpu),
219 cacheBlockMask = ~(cpu->cacheLineSize() - 1);
225 /** Snoop a coherence request, we need to check if this causes
226 * a wakeup event on a cpu that is monitoring an address
228 virtual void recvTimingSnoopReq(PacketPtr pkt);
229 virtual void recvFunctionalSnoop(PacketPtr pkt);
231 virtual bool recvTimingResp(PacketPtr pkt);
233 virtual void recvReqRetry();
235 virtual bool isSnooping() const {
239 struct DTickEvent : public TickEvent
241 DTickEvent(TimingSimpleCPU *_cpu)
244 const char *description() const { return "Timing CPU dcache tick"; }
247 DTickEvent tickEvent;
251 void updateCycleCounts();
253 IcachePort icachePort;
254 DcachePort dcachePort;
256 PacketPtr ifetch_pkt;
257 PacketPtr dcache_pkt;
259 Cycles previousCycle;
263 /** Return a reference to the data port. */
264 MasterPort &getDataPort() override { return dcachePort; }
266 /** Return a reference to the instruction port. */
267 MasterPort &getInstPort() override { return icachePort; }
271 DrainState drain() override;
272 void drainResume() override;
274 void switchOut() override;
275 void takeOverFrom(BaseCPU *oldCPU) override;
277 void verifyMemoryMode() const override;
279 void activateContext(ThreadID thread_num) override;
280 void suspendContext(ThreadID thread_num) override;
282 Fault readMem(Addr addr, uint8_t *data, unsigned size,
283 Request::Flags flags) override;
285 Fault initiateMemRead(Addr addr, unsigned size,
286 Request::Flags flags) override;
288 Fault writeMem(uint8_t *data, unsigned size,
289 Addr addr, Request::Flags flags, uint64_t *res) override;
292 void sendFetch(const Fault &fault, RequestPtr req, ThreadContext *tc);
293 void completeIfetch(PacketPtr );
294 void completeDataAccess(PacketPtr pkt);
295 void advanceInst(const Fault &fault);
297 /** This function is used by the page table walker to determine if it could
298 * translate the a pending request or if the underlying request has been
299 * squashed. This always returns false for the simple timing CPU as it never
300 * executes any instructions speculatively.
301 * @ return Is the current instruction squashed?
303 bool isSquashed() const { return false; }
306 * Print state of address in memory system via PrintReq (for
309 void printAddr(Addr a);
312 * Finish a DTB translation.
313 * @param state The DTB translation state.
315 void finishTranslation(WholeTranslationState *state);
319 EventFunctionWrapper fetchEvent;
321 struct IprEvent : Event {
323 TimingSimpleCPU *cpu;
324 IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t);
325 virtual void process();
326 virtual const char *description() const;
330 * Check if a system is in a drained state.
332 * We need to drain if:
334 * <li>We are in the middle of a microcode sequence as some CPUs
335 * (e.g., HW accelerated CPUs) can't be started in the middle
336 * of a gem5 microcode sequence.
338 * <li>Stay at PC is true.
340 * <li>A fetch event is scheduled. Normally this would never be the
341 * case with microPC() == 0, but right after a context is
342 * activated it can happen.
346 SimpleExecContext& t_info = *threadInfo[curThread];
347 SimpleThread* thread = t_info.thread;
349 return thread->microPC() == 0 && !t_info.stayAtPC &&
350 !fetchEvent.scheduled();
354 * Try to complete a drain request.
356 * @returns true if the CPU is drained, false otherwise.
358 bool tryCompleteDrain();
361 #endif // __CPU_SIMPLE_TIMING_HH__