2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
31 #ifndef __CPU_SIMPLE_TIMING_HH__
32 #define __CPU_SIMPLE_TIMING_HH__
34 #include "cpu/simple/base.hh"
36 #include "params/TimingSimpleCPU.hh"
38 class TimingSimpleCPU : public BaseSimpleCPU
42 TimingSimpleCPU(TimingSimpleCPUParams * params);
43 virtual ~TimingSimpleCPU();
53 * If an access needs to be broken into fragments, currently at most two,
54 * the the following two classes are used as the sender state of the
55 * packets so the CPU can keep track of everything. In the main packet
56 * sender state, there's an array with a spot for each fragment. If a
57 * fragment has already been accepted by the CPU, aka isn't waiting for
58 * a retry, it's pointer is NULL. After each fragment has successfully
59 * been processed, the "outstanding" counter is decremented. Once the
60 * count is zero, the entire larger access is complete.
62 class SplitMainSenderState : public Packet::SenderState
66 PacketPtr fragments[2];
73 } else if (fragments[1]) {
81 class SplitFragmentSenderState : public Packet::SenderState
84 SplitFragmentSenderState(PacketPtr _bigPkt, int _index) :
85 bigPkt(_bigPkt), index(_index)
93 SplitMainSenderState * main_send_state =
94 dynamic_cast<SplitMainSenderState *>(bigPkt->senderState);
95 main_send_state->fragments[index] = NULL;
99 class FetchTranslation : public BaseTLB::Translation
102 TimingSimpleCPU *cpu;
105 FetchTranslation(TimingSimpleCPU *_cpu) : cpu(_cpu)
108 void finish(Fault fault, RequestPtr req,
109 ThreadContext *tc, bool write)
111 cpu->sendFetch(fault, req, tc);
114 FetchTranslation fetchTranslation;
116 class DataTranslation : public BaseTLB::Translation
119 TimingSimpleCPU *cpu;
125 DataTranslation(TimingSimpleCPU *_cpu,
126 uint8_t *_data, uint64_t *_res, bool _read) :
127 cpu(_cpu), data(_data), res(_res), read(_read)
131 finish(Fault fault, RequestPtr req,
132 ThreadContext *tc, bool write)
134 cpu->sendData(fault, req, data, res, read);
139 class SplitDataTranslation : public BaseTLB::Translation
142 struct WholeTranslationState
146 RequestPtr requests[2];
152 WholeTranslationState(RequestPtr req1, RequestPtr req2,
153 RequestPtr main, uint8_t *_data, bool _read)
159 faults[0] = faults[1] = NoFault;
165 TimingSimpleCPU *cpu;
167 WholeTranslationState *state;
169 SplitDataTranslation(TimingSimpleCPU *_cpu, int _index,
170 WholeTranslationState *_state) :
171 cpu(_cpu), index(_index), state(_state)
175 finish(Fault fault, RequestPtr req,
176 ThreadContext *tc, bool write)
179 assert(state->outstanding);
180 state->faults[index] = fault;
181 if (--state->outstanding == 0) {
182 cpu->sendSplitData(state->faults[0],
195 void sendData(Fault fault, RequestPtr req,
196 uint8_t *data, uint64_t *res, bool read);
197 void sendSplitData(Fault fault1, Fault fault2,
198 RequestPtr req1, RequestPtr req2, RequestPtr req,
199 uint8_t *data, bool read);
201 void translationFault(Fault fault);
203 void buildPacket(PacketPtr &pkt, RequestPtr req, bool read);
204 void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
205 RequestPtr req1, RequestPtr req2, RequestPtr req,
206 uint8_t *data, bool read);
208 bool handleReadPacket(PacketPtr pkt);
209 // This function always implicitly uses dcache_pkt.
210 bool handleWritePacket();
212 class CpuPort : public Port
215 TimingSimpleCPU *cpu;
220 CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat)
221 : Port(_name, _cpu), cpu(_cpu), lat(_lat)
228 virtual Tick recvAtomic(PacketPtr pkt);
230 virtual void recvFunctional(PacketPtr pkt);
232 virtual void recvStatusChange(Status status);
234 virtual void getDeviceAddressRanges(AddrRangeList &resp,
236 { resp.clear(); snoop = false; }
238 struct TickEvent : public Event
241 TimingSimpleCPU *cpu;
243 TickEvent(TimingSimpleCPU *_cpu) : cpu(_cpu) {}
244 const char *description() const { return "Timing CPU tick"; }
245 void schedule(PacketPtr _pkt, Tick t);
250 class IcachePort : public CpuPort
254 IcachePort(TimingSimpleCPU *_cpu, Tick _lat)
255 : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu)
260 virtual bool recvTiming(PacketPtr pkt);
262 virtual void recvRetry();
264 struct ITickEvent : public TickEvent
267 ITickEvent(TimingSimpleCPU *_cpu)
270 const char *description() const { return "Timing CPU icache tick"; }
273 ITickEvent tickEvent;
277 class DcachePort : public CpuPort
281 DcachePort(TimingSimpleCPU *_cpu, Tick _lat)
282 : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu)
285 virtual void setPeer(Port *port);
289 virtual bool recvTiming(PacketPtr pkt);
291 virtual void recvRetry();
293 struct DTickEvent : public TickEvent
295 DTickEvent(TimingSimpleCPU *_cpu)
298 const char *description() const { return "Timing CPU dcache tick"; }
301 DTickEvent tickEvent;
305 IcachePort icachePort;
306 DcachePort dcachePort;
308 PacketPtr ifetch_pkt;
309 PacketPtr dcache_pkt;
315 virtual Port *getPort(const std::string &if_name, int idx = -1);
317 virtual void serialize(std::ostream &os);
318 virtual void unserialize(Checkpoint *cp, const std::string §ion);
320 virtual unsigned int drain(Event *drain_event);
321 virtual void resume();
324 void takeOverFrom(BaseCPU *oldCPU);
326 virtual void activateContext(int thread_num, int delay);
327 virtual void suspendContext(int thread_num);
330 Fault read(Addr addr, T &data, unsigned flags);
333 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
336 void sendFetch(Fault fault, RequestPtr req, ThreadContext *tc);
337 void completeIfetch(PacketPtr );
338 void completeDataAccess(PacketPtr pkt);
339 void advanceInst(Fault fault);
342 * Print state of address in memory system via PrintReq (for
345 void printAddr(Addr a);
349 typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
350 FetchEvent fetchEvent;
352 struct IprEvent : Event {
354 TimingSimpleCPU *cpu;
355 IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t);
356 virtual void process();
357 virtual const char *description() const;
360 void completeDrain();
363 #endif // __CPU_SIMPLE_TIMING_HH__