2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
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16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
31 #ifndef __CPU_SIMPLE_TIMING_HH__
32 #define __CPU_SIMPLE_TIMING_HH__
34 #include "cpu/simple/base.hh"
36 class TimingSimpleCPU : public BaseSimpleCPU
40 struct Params : public BaseSimpleCPU::Params {
43 TimingSimpleCPU(Params *params);
44 virtual ~TimingSimpleCPU();
65 Status status() const { return _status; }
69 class CpuPort : public Port
76 CpuPort(const std::string &_name, TimingSimpleCPU *_cpu)
77 : Port(_name), cpu(_cpu)
82 virtual Tick recvAtomic(Packet *pkt);
84 virtual void recvFunctional(Packet *pkt);
86 virtual void recvStatusChange(Status status);
88 virtual void getDeviceAddressRanges(AddrRangeList &resp,
90 { resp.clear(); snoop.clear(); }
93 class IcachePort : public CpuPort
97 IcachePort(TimingSimpleCPU *_cpu)
98 : CpuPort(_cpu->name() + "-iport", _cpu)
103 virtual bool recvTiming(Packet *pkt);
105 virtual void recvRetry();
108 class DcachePort : public CpuPort
112 DcachePort(TimingSimpleCPU *_cpu)
113 : CpuPort(_cpu->name() + "-dport", _cpu)
118 virtual bool recvTiming(Packet *pkt);
120 virtual void recvRetry();
123 IcachePort icachePort;
124 DcachePort dcachePort;
131 virtual void serialize(std::ostream &os);
132 virtual void unserialize(Checkpoint *cp, const std::string §ion);
134 void switchOut(Sampler *s);
135 void takeOverFrom(BaseCPU *oldCPU);
137 virtual void activateContext(int thread_num, int delay);
138 virtual void suspendContext(int thread_num);
141 Fault read(Addr addr, T &data, unsigned flags);
144 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
147 void completeIfetch(Packet *);
148 void completeDataAccess(Packet *);
149 void advanceInst(Fault fault);
152 #endif // __CPU_SIMPLE_TIMING_HH__