src/cpu/simple/timing.hh

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  */
  30
  31 #ifndef __CPU_SIMPLE_TIMING_HH__
  32 #define __CPU_SIMPLE_TIMING_HH__
  33
  34 #include "cpu/simple/base.hh"
  35
  36 class TimingSimpleCPU : public BaseSimpleCPU
  37 {
  38   public:
  39
  40     struct Params : public BaseSimpleCPU::Params {
  41     };
  42
  43     TimingSimpleCPU(Params *params);
  44     virtual ~TimingSimpleCPU();
  45
  46     virtual void init();
  47
  48   public:
  49     //
  50     enum Status {
  51         Idle,
  52         Running,
  53         IcacheRetry,
  54         IcacheWaitResponse,
  55         IcacheWaitSwitch,
  56         DcacheRetry,
  57         DcacheWaitResponse,
  58         DcacheWaitSwitch,
  59         SwitchedOut
  60     };
  61
  62   protected:
  63     Status _status;
  64
  65     Status status() const { return _status; }
  66
  67     Event *drainEvent;
  68
  69     Event *fetchEvent;
  70
  71   private:
  72
  73     class CpuPort : public Port
  74     {
  75       protected:
  76         TimingSimpleCPU *cpu;
  77         Tick lat;
  78
  79       public:
  80
  81         CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat)
  82             : Port(_name), cpu(_cpu), lat(_lat)
  83         { }
  84
  85       protected:
  86
  87         virtual Tick recvAtomic(Packet *pkt);
  88
  89         virtual void recvFunctional(Packet *pkt);
  90
  91         virtual void recvStatusChange(Status status);
  92
  93         virtual void getDeviceAddressRanges(AddrRangeList &resp,
  94             AddrRangeList &snoop)
  95         { resp.clear(); snoop.clear(); }
  96
  97         struct TickEvent : public Event
  98         {
  99             Packet *pkt;
 100             TimingSimpleCPU *cpu;
 101
 102             TickEvent(TimingSimpleCPU *_cpu)
 103                 :Event(&mainEventQueue), cpu(_cpu) {}
 104             const char *description() { return "Timing CPU clock event"; }
 105             void schedule(Packet *_pkt, Tick t);
 106         };
 107
 108     };
 109
 110     class IcachePort : public CpuPort
 111     {
 112       public:
 113
 114         IcachePort(TimingSimpleCPU *_cpu, Tick _lat)
 115             : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu)
 116         { }
 117
 118       protected:
 119
 120         virtual bool recvTiming(Packet *pkt);
 121
 122         virtual void recvRetry();
 123
 124         struct ITickEvent : public TickEvent
 125         {
 126
 127             ITickEvent(TimingSimpleCPU *_cpu)
 128                 : TickEvent(_cpu) {}
 129             void process();
 130             const char *description() { return "Timing CPU clock event"; }
 131         };
 132
 133         ITickEvent tickEvent;
 134
 135     };
 136
 137     class DcachePort : public CpuPort
 138     {
 139       public:
 140
 141         DcachePort(TimingSimpleCPU *_cpu, Tick _lat)
 142             : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu)
 143         { }
 144
 145       protected:
 146
 147         virtual bool recvTiming(Packet *pkt);
 148
 149         virtual void recvRetry();
 150
 151         struct DTickEvent : public TickEvent
 152         {
 153             DTickEvent(TimingSimpleCPU *_cpu)
 154                 : TickEvent(_cpu) {}
 155             void process();
 156             const char *description() { return "Timing CPU clock event"; }
 157         };
 158
 159         DTickEvent tickEvent;
 160
 161     };
 162
 163     IcachePort icachePort;
 164     DcachePort dcachePort;
 165
 166     Packet *ifetch_pkt;
 167     Packet *dcache_pkt;
 168
 169     int cpu_id;
 170
 171   public:
 172
 173     virtual Port *getPort(const std::string &if_name, int idx = -1);
 174
 175     virtual void serialize(std::ostream &os);
 176     virtual void unserialize(Checkpoint *cp, const std::string &section);
 177
 178     virtual unsigned int drain(Event *drain_event);
 179     virtual void resume();
 180
 181     void switchOut();
 182     void takeOverFrom(BaseCPU *oldCPU);
 183
 184     virtual void activateContext(int thread_num, int delay);
 185     virtual void suspendContext(int thread_num);
 186
 187     template <class T>
 188     Fault read(Addr addr, T &data, unsigned flags);
 189
 190     template <class T>
 191     Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
 192
 193     void fetch();
 194     void completeIfetch(Packet *);
 195     void completeDataAccess(Packet *);
 196     void advanceInst(Fault fault);
 197   private:
 198     void completeDrain();
 199 };
 200
 201 #endif // __CPU_SIMPLE_TIMING_HH__