2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
31 #ifndef __CPU_SIMPLE_TIMING_HH__
32 #define __CPU_SIMPLE_TIMING_HH__
34 #include "cpu/simple/base.hh"
36 class TimingSimpleCPU : public BaseSimpleCPU
40 struct Params : public BaseSimpleCPU::Params {
43 TimingSimpleCPU(Params *params);
44 virtual ~TimingSimpleCPU();
65 Status status() const { return _status; }
73 class CpuPort : public Port
81 CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat)
82 : Port(_name), cpu(_cpu), lat(_lat)
87 virtual Tick recvAtomic(Packet *pkt);
89 virtual void recvFunctional(Packet *pkt);
91 virtual void recvStatusChange(Status status);
93 virtual void getDeviceAddressRanges(AddrRangeList &resp,
95 { resp.clear(); snoop.clear(); }
97 struct TickEvent : public Event
100 TimingSimpleCPU *cpu;
102 TickEvent(TimingSimpleCPU *_cpu)
103 :Event(&mainEventQueue), cpu(_cpu) {}
104 const char *description() { return "Timing CPU clock event"; }
105 void schedule(Packet *_pkt, Tick t);
110 class IcachePort : public CpuPort
114 IcachePort(TimingSimpleCPU *_cpu, Tick _lat)
115 : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu)
120 virtual bool recvTiming(Packet *pkt);
122 virtual void recvRetry();
124 struct ITickEvent : public TickEvent
127 ITickEvent(TimingSimpleCPU *_cpu)
130 const char *description() { return "Timing CPU clock event"; }
133 ITickEvent tickEvent;
137 class DcachePort : public CpuPort
141 DcachePort(TimingSimpleCPU *_cpu, Tick _lat)
142 : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu)
147 virtual bool recvTiming(Packet *pkt);
149 virtual void recvRetry();
151 struct DTickEvent : public TickEvent
153 DTickEvent(TimingSimpleCPU *_cpu)
156 const char *description() { return "Timing CPU clock event"; }
159 DTickEvent tickEvent;
163 IcachePort icachePort;
164 DcachePort dcachePort;
171 virtual Port *getPort(const std::string &if_name, int idx = -1);
173 virtual void serialize(std::ostream &os);
174 virtual void unserialize(Checkpoint *cp, const std::string §ion);
176 virtual unsigned int drain(Event *drain_event);
177 virtual void resume();
180 void takeOverFrom(BaseCPU *oldCPU);
182 virtual void activateContext(int thread_num, int delay);
183 virtual void suspendContext(int thread_num);
186 Fault read(Addr addr, T &data, unsigned flags);
189 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
192 void completeIfetch(Packet *);
193 void completeDataAccess(Packet *);
194 void advanceInst(Fault fault);
196 void completeDrain();
199 #endif // __CPU_SIMPLE_TIMING_HH__