2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
31 #ifndef __CPU_SIMPLE_TIMING_HH__
32 #define __CPU_SIMPLE_TIMING_HH__
34 #include "cpu/simple/base.hh"
35 #include "cpu/translation.hh"
36 #include "params/TimingSimpleCPU.hh"
38 class TimingSimpleCPU : public BaseSimpleCPU
42 TimingSimpleCPU(TimingSimpleCPUParams * params);
43 virtual ~TimingSimpleCPU();
48 DrainManager *drainManager;
53 * If an access needs to be broken into fragments, currently at most two,
54 * the the following two classes are used as the sender state of the
55 * packets so the CPU can keep track of everything. In the main packet
56 * sender state, there's an array with a spot for each fragment. If a
57 * fragment has already been accepted by the CPU, aka isn't waiting for
58 * a retry, it's pointer is NULL. After each fragment has successfully
59 * been processed, the "outstanding" counter is decremented. Once the
60 * count is zero, the entire larger access is complete.
62 class SplitMainSenderState : public Packet::SenderState
66 PacketPtr fragments[2];
73 } else if (fragments[1]) {
81 class SplitFragmentSenderState : public Packet::SenderState
84 SplitFragmentSenderState(PacketPtr _bigPkt, int _index) :
85 bigPkt(_bigPkt), index(_index)
93 SplitMainSenderState * main_send_state =
94 dynamic_cast<SplitMainSenderState *>(bigPkt->senderState);
95 main_send_state->fragments[index] = NULL;
99 class FetchTranslation : public BaseTLB::Translation
102 TimingSimpleCPU *cpu;
105 FetchTranslation(TimingSimpleCPU *_cpu)
112 assert(cpu->_status == BaseSimpleCPU::Running);
113 cpu->_status = ITBWaitResponse;
117 finish(Fault fault, RequestPtr req, ThreadContext *tc,
120 cpu->sendFetch(fault, req, tc);
123 FetchTranslation fetchTranslation;
125 void sendData(RequestPtr req, uint8_t *data, uint64_t *res, bool read);
126 void sendSplitData(RequestPtr req1, RequestPtr req2, RequestPtr req,
127 uint8_t *data, bool read);
129 void translationFault(Fault fault);
131 void buildPacket(PacketPtr &pkt, RequestPtr req, bool read);
132 void buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
133 RequestPtr req1, RequestPtr req2, RequestPtr req,
134 uint8_t *data, bool read);
136 bool handleReadPacket(PacketPtr pkt);
137 // This function always implicitly uses dcache_pkt.
138 bool handleWritePacket();
141 * A TimingCPUPort overrides the default behaviour of the
142 * recvTiming and recvRetry and implements events for the
143 * scheduling of handling of incoming packets in the following
146 class TimingCPUPort : public CpuPort
150 TimingCPUPort(const std::string& _name, TimingSimpleCPU* _cpu)
151 : CpuPort(_name, _cpu), cpu(_cpu), retryEvent(this)
157 * Snooping a coherence request, do nothing.
159 virtual void recvTimingSnoopReq(PacketPtr pkt) { }
161 TimingSimpleCPU* cpu;
163 struct TickEvent : public Event
166 TimingSimpleCPU *cpu;
168 TickEvent(TimingSimpleCPU *_cpu) : pkt(NULL), cpu(_cpu) {}
169 const char *description() const { return "Timing CPU tick"; }
170 void schedule(PacketPtr _pkt, Tick t);
173 EventWrapper<MasterPort, &MasterPort::sendRetry> retryEvent;
176 class IcachePort : public TimingCPUPort
180 IcachePort(TimingSimpleCPU *_cpu)
181 : TimingCPUPort(_cpu->name() + ".icache_port", _cpu),
187 virtual bool recvTimingResp(PacketPtr pkt);
189 virtual void recvRetry();
191 struct ITickEvent : public TickEvent
194 ITickEvent(TimingSimpleCPU *_cpu)
197 const char *description() const { return "Timing CPU icache tick"; }
200 ITickEvent tickEvent;
204 class DcachePort : public TimingCPUPort
208 DcachePort(TimingSimpleCPU *_cpu)
209 : TimingCPUPort(_cpu->name() + ".dcache_port", _cpu),
215 virtual bool recvTimingResp(PacketPtr pkt);
217 virtual void recvRetry();
219 struct DTickEvent : public TickEvent
221 DTickEvent(TimingSimpleCPU *_cpu)
224 const char *description() const { return "Timing CPU dcache tick"; }
227 DTickEvent tickEvent;
231 IcachePort icachePort;
232 DcachePort dcachePort;
234 PacketPtr ifetch_pkt;
235 PacketPtr dcache_pkt;
241 /** Return a reference to the data port. */
242 virtual CpuPort &getDataPort() { return dcachePort; }
244 /** Return a reference to the instruction port. */
245 virtual CpuPort &getInstPort() { return icachePort; }
249 virtual void serialize(std::ostream &os);
250 virtual void unserialize(Checkpoint *cp, const std::string §ion);
252 unsigned int drain(DrainManager *drain_manager);
256 void takeOverFrom(BaseCPU *oldCPU);
258 virtual void activateContext(ThreadID thread_num, Cycles delay);
259 virtual void suspendContext(ThreadID thread_num);
261 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
263 Fault writeMem(uint8_t *data, unsigned size,
264 Addr addr, unsigned flags, uint64_t *res);
267 void sendFetch(Fault fault, RequestPtr req, ThreadContext *tc);
268 void completeIfetch(PacketPtr );
269 void completeDataAccess(PacketPtr pkt);
270 void advanceInst(Fault fault);
272 /** This function is used by the page table walker to determine if it could
273 * translate the a pending request or if the underlying request has been
274 * squashed. This always returns false for the simple timing CPU as it never
275 * executes any instructions speculatively.
276 * @ return Is the current instruction squashed?
278 bool isSquashed() const { return false; }
281 * Print state of address in memory system via PrintReq (for
284 void printAddr(Addr a);
287 * Finish a DTB translation.
288 * @param state The DTB translation state.
290 void finishTranslation(WholeTranslationState *state);
294 typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
295 FetchEvent fetchEvent;
297 struct IprEvent : Event {
299 TimingSimpleCPU *cpu;
300 IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t);
301 virtual void process();
302 virtual const char *description() const;
305 void completeDrain();
308 #endif // __CPU_SIMPLE_TIMING_HH__