2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
31 #ifndef __CPU_SIMPLE_TIMING_HH__
32 #define __CPU_SIMPLE_TIMING_HH__
34 #include "cpu/simple/base.hh"
36 class TimingSimpleCPU : public BaseSimpleCPU
40 struct Params : public BaseSimpleCPU::Params {
43 TimingSimpleCPU(Params *params);
44 virtual ~TimingSimpleCPU();
53 class CpuPort : public Port
61 CpuPort(const std::string &_name, TimingSimpleCPU *_cpu, Tick _lat)
62 : Port(_name, _cpu), cpu(_cpu), lat(_lat)
69 virtual Tick recvAtomic(PacketPtr pkt);
71 virtual void recvFunctional(PacketPtr pkt);
73 virtual void recvStatusChange(Status status);
75 virtual void getDeviceAddressRanges(AddrRangeList &resp,
77 { resp.clear(); snoop = false; }
79 struct TickEvent : public Event
84 TickEvent(TimingSimpleCPU *_cpu)
85 :Event(&mainEventQueue), cpu(_cpu) {}
86 const char *description() const { return "Timing CPU tick"; }
87 void schedule(PacketPtr _pkt, Tick t);
92 class IcachePort : public CpuPort
96 IcachePort(TimingSimpleCPU *_cpu, Tick _lat)
97 : CpuPort(_cpu->name() + "-iport", _cpu, _lat), tickEvent(_cpu)
102 virtual bool recvTiming(PacketPtr pkt);
104 virtual void recvRetry();
106 struct ITickEvent : public TickEvent
109 ITickEvent(TimingSimpleCPU *_cpu)
112 const char *description() const { return "Timing CPU icache tick"; }
115 ITickEvent tickEvent;
119 class DcachePort : public CpuPort
123 DcachePort(TimingSimpleCPU *_cpu, Tick _lat)
124 : CpuPort(_cpu->name() + "-dport", _cpu, _lat), tickEvent(_cpu)
127 virtual void setPeer(Port *port);
131 virtual bool recvTiming(PacketPtr pkt);
133 virtual void recvRetry();
135 struct DTickEvent : public TickEvent
137 DTickEvent(TimingSimpleCPU *_cpu)
140 const char *description() const { return "Timing CPU dcache tick"; }
143 DTickEvent tickEvent;
147 IcachePort icachePort;
148 DcachePort dcachePort;
150 PacketPtr ifetch_pkt;
151 PacketPtr dcache_pkt;
157 virtual Port *getPort(const std::string &if_name, int idx = -1);
159 virtual void serialize(std::ostream &os);
160 virtual void unserialize(Checkpoint *cp, const std::string §ion);
162 virtual unsigned int drain(Event *drain_event);
163 virtual void resume();
166 void takeOverFrom(BaseCPU *oldCPU);
168 virtual void activateContext(int thread_num, int delay);
169 virtual void suspendContext(int thread_num);
172 Fault read(Addr addr, T &data, unsigned flags);
174 Fault translateDataReadAddr(Addr vaddr, Addr &paddr,
175 int size, unsigned flags);
178 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
180 Fault translateDataWriteAddr(Addr vaddr, Addr &paddr,
181 int size, unsigned flags);
184 void completeIfetch(PacketPtr );
185 void completeDataAccess(PacketPtr );
186 void advanceInst(Fault fault);
189 * Print state of address in memory system via PrintReq (for
192 void printAddr(Addr a);
196 typedef EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch> FetchEvent;
197 FetchEvent *fetchEvent;
199 struct IprEvent : Event {
201 TimingSimpleCPU *cpu;
202 IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t);
203 virtual void process();
204 virtual const char *description() const;
207 void completeDrain();
210 #endif // __CPU_SIMPLE_TIMING_HH__